1. Introduction

Owing to the rapid growth of data centers and cloud-based applications, the demand for chip-to-chip data transfer with high speed and high capacity has increased [1]. In this regard, optical rather than electronic interconnections were introduced owing to their great advantages in terms of high bandwidth and low power consumption [2,3]. Hence, enormous efforts have been made to develop silicon-based on-chip light sources as an essential component of optical interconnections [4]. However, the indirect bandgap in silicon emerged as a major obstacle to realize on-chip light sources. There were various alternative approaches to obtain on-chip silicon light sources, such as laser diodes (LDs). While telecommunication wavelength emission could be obtained through implantation of erbium ions into silicon, it was difficult to fabricate an electrically driven device and to control the emission wavelength [5]. In spite of an indirect bandgap of Ge, the LD was fabricated based-on epitaxially grown Ge on Si through generating a pseudo bandgap by applying strain [6]. However, it was difficult to achieve high light output efficiency compared to III-V semiconductor-based LDs. Highly efficient on-chip light sources could be realized by integration of III-V LDs on Si. There are two ways to accomplish such integration of III-V on Si: monolithic integration and heterogeneous integration. For heterogeneous integration, III-V device chips or wafers are attached to a Si by using adhesive-assisted wafer bonding or direct wafer bonding [7]. Heterogeneous integration has limitations in terms of difficult large-scale wafer integration and poor thermal conduction between III-V and Si wafers. By contrast, monolithic integration does provide large-scale integration and good thermal conductivity owing to direct growth. It is quite important to directly grow a III-V epitaxial layer on Si substrate, because III-V materials, such as GaAs or InP, are the essential material for high speed optoelectronic devices due to its high carrier mobility [8]. However, large mismatches in the lattice constant and thermal expansion coefficient between GaAs and Si lead to high threading dislocation density (TDD) in GaAs as high as 10⁸ ∼ 10¹⁰ cm⁻² [9,10], which is a major obstacle to carry out lasing operation. To improve the crystal quality and to reduce the dislocation density, various approaches have been proposed. Si_xGe_1-x based lattice-graded buffers were adopted as a buffer layer to release the lattice mismatch [11,12]. GaP on Si was also used as a buffer layer and GaAs was epitaxially grown on the GaP/Si [13,14]. And the threading dislocations or stacking faults can be reduced by growing GaAs on an inclined facets of patterned Si substrate [15,16]. It was reported that employing superlattices as a dislocation filtering layer effectively reduces the TDD of GaAs [17–19]. Based on GaAs on Si of comparatively low TDD grown by these methods, LD structures were fabricated by growing quantum wells (QWs) and quantum dots (QDs) as active layers. On the one hand, InP on Si-based LD was also challenging. Because of the relatively larger lattice mismatch of InP-on-Si than GaAs-on-Si, directly grown InP on Si was more difficult. For achieving InP-based LD on Si, the InP-based LDs were epitaxially grown on wafer-bonded InP on Si [20,21], and InP distributed feedback laser was demonstrated by using the growth of InP on V-grooved inclined facet of Si [22]. Recently there have been numerous reports of the epitaxially grown InP on Si by using intermediate GaAs buffer on Si after obtaining high-quality GaAs grown on the V-grooved Si. The InP-based quantum dash and QD lasers of 1.3 µm- and 1.55 µm-wavelength were demonstrated [23,24], and the InP-based QW laser of 1.55 µm-wavelength was also reported based-on the GaAs on V-grooved Si [25]. Thus, it is quite important to obtain epitaxially grown GaAs on Si with low TDD in term of telecom wavelength laser. However, the buffer layers become too thick to extremely reduce TDD, which is not suitable for a silicon photonics platform with an on-chip light source. Hence, it is critical to reduce the GaAs buffer thickness on Si as well as the TDD. Wang et al. reduced the thickness of buffer layers to 1.8 µm by using a three-step GaAs growth with carrying out thermal cycle annealing (TCA) [26]. The AlAs nucleation layer has suppressed three-dimensional growth and provided a superior seeding for III-V nucleation [27]. Chen et al. adopted an AlAs nucleation layer with a three-step growth technique to improve crystal quality of GaAs epitaxial layer and obtained InAs/GaAs QD LDs [28].

In this study, we suggested a hybrid technique of AlAs nucleation and TCA method to realize directly grown GaAs LDs on Si. We adopted the AlAs nucleation layer and the TCA methods to simultaneously achieve the advantages of good GaAs seeding and small thickness of GaAs buffer of low TDD. The GaAs on Si were grown with two-step growth and optical and structural properties were systematically studied for each step. We found that there is an optimal thickness of the AlAs nucleation layer. Moreover, we performed a quantitative analysis of the TDD through electron channeling contrast imaging (ECCI). The high-quality GaAs on Si was obtained with effectively reduced TDD and thin buffer thickness by using hybrid technique. Finally, GaAs LD on Si substrate was directly grown with low enough TDD. Broad stripe edge-emitting LDs on Si were successfully fabricated and operated at room temperature under continuous-wave (c.w.) and pulsed operation conditions.

2. Experiments

GaAs buffers and LD full structures on Si were grown by metalorganic chemical vapor deposition. We used Si substrate (100) with a 7° miscut towards (011) to suppress the formation of antiphase domains. AlAs nucleation layers were grown at 420 °C after removing the oxides on the Si by thermal annealing treatment with chemical etching. GaAs buffers were grown on the AlAs nucleation with varying the thickness of the AlAs from 0 to 7.48 nm. GaAs buffers were grown through a two-step growth varying the growth temperature. For a first-step GaAs buffer, GaAs was grown with low-temperature (LT) growth at 420 °C on AlAs nucleation.

We monitored the surface roughness of LT GaAs through atomic force microscopy (AFM). We set the thickness of LT GaAs as 17 nm, exhibiting a smooth surface roughness. We adopted the growth procedure of GaAs layers with increasing growth temperature and TCA process [26]. GaAs was sequentially grown under gradually increased temperature up to 640 °C. Then, middle-temperature (MT) GaAs was grown at 640 °C with 250 nm followed by high-temperature (HT) GaAs grown at 680 °C with 750 nm. For a second-step GaAs buffer, we performed the TCA process as the temperature of the wafer increased up to 800 °C, cooled down to 350 °C, and this cycle was repeated three period. And then, HT GaAs at 680 °C was grown with 500 nm followed by a second TCA process. The final thickness of the GaAs on Si was around 1.5 µm. After optimizing the growth condition of the GaAs buffer, the LD structure was grown on it. A schematic diagram of the GaAs buffer and the full LD structure is shown in Fig. 1(a) and (b), respectively. For the LD on Si, the n-type 500-nm-thick GaAs was grown as a contact layer. Three-period GaAs/Al_0.5Ga_0.5As multi-QWs (MQWs) were grown as an active layer, which were sandwiched by 1.4 µm-thick n-type Al_0.5Ga_0.5As and 1.4 µm-thick p-type Al_0.5Ga_0.5As as cladding layers. Finally, 200 nm-thick p-type GaAs was grown as a contact layer. To characterize the TDD of GaAs buffers and full LDs, we performed ECCI, which enable the visualization of the position of threading dislocations. ECCI was performed through scanning electron microscopy with an efficient backscattered electron detector. By AFM measurement, surface roughness of GaAs buffers was analyzed, whereas the optical characteristic was analyzed by photoluminescence (PL) measurement. The broad-stripe LD on Si structure was fabricated by a conventional semiconductor process with a cavity length and width of 1120 µm and 60 µm, respectively. Ge/Au/Ni/Au and Ti/Pt/Au metals were deposited on the n-type GaAs and p-type GaAs, respectively for the electrodes. For the edge-emitting LD, the Si wafer was thinned to 100 µm and cleaved to have mirror facets. Fabricated LDs were characterized through light output-current-voltage measurements.

 

Fig. 1. (a) Schematic diagram of epitaxial layer for GaAs full buffer on Si substrate with TCA process and AlAs nucleation and (b) full structure of GaAs LD on Si substrate.

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3. Results and discussion

We grew six series samples of first-step GaAs buffer before applying the TCA process, with varying AlAs nucleation thickness to observe the nucleation thickness dependence on the GaAs on Si. Six samples were prepared with different values of AlAs thickness of 0, 0.37, 0.56, 1.68, 3.74, and 7.48 nm. The AlAs nucleation thickness was extracted from this average growth rate where the measured average growth rate of AlAs was 0.62 Å/s. We measured the AFM of the GaAs buffer surfaces under an area of 10 × 10 µm². Figure 2(a) and (b) shows the root mean square roughness and AFM images of the GaAs surfaces with various AlAs nucleation thickness, respectively.

 

Fig. 2. (a) The root mean square roughness and (b) AFM images of the first-step GaAs buffer on Si substrate with different thickness of AlAs nucleation. The AFM data were shown with the same scale and the surface roughness was measured by AFM under an area of 10 × 10 µm². (c) The PL peak intensity and FWHM of the first-step GaAs buffer on Si with different thickness of AlAs nucleation measured at room temperature.

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The measured roughness of GaAs without AlAs nucleation was 7.28 nm. The roughness was reduced to 2.25 nm and 2.12 nm for the sample of 1.68- and 3.74-nm-thick AlAs, respectively. When the AlAs thickness increasing to 7.48 nm, the roughness increased again to 6.22 nm. The GaAs buffer on 1.68- and 3.74-nm AlAs had a relatively smooth surface as shown in the AFM images of the same vertical and lateral scale. The AlAs nucleation on Si enhanced the surface roughness of the GaAs because the AlAs nucleation enhanced lateral growth of GaAs. However, the roughness was rather degraded when exceeding certain nucleation thickness range from 1.68 nm to 3.74 nm. We consider that the optimal AlAs nucleation thickness would exist for superior surface of GaAs buffer. We performed the optical characterization of series samples of first-step GaAs buffers. The PL of these buffers was measured at room temperature with 532 nm wavelength laser excitation. We compared the PL peak intensity and full width at half maximum (FWHM) as shown in Fig. 2(c). The PL intensity was highly affected by AlAs thickness. Compared to the sample without AlAs nucleation, the sample of 1.68-nm- and 3.74 nm-thick AlAs showed a PL enhancement of 22.5% and 24.7%, respectively. When the AlAs thickness exceeded certain thickness, the PL intensity decreased again and the 7.48-nm-thick sample showed a notably degraded PL intensity. Because the PL of the all samples was measured under the same condition, it could be considered that the PL intensity reflected the quantum efficiency. It was considered that GaAs buffer with AlAs thickness between 1.68 nm and 3.74 nm would have maximum PL peak intensity. Moreover, for AlAs nucleation samples, the FHWM of PL peak was minimized at thickness of 1.68 nm where the FWHM reflect the uniformity of epitaxial layer. This is consistent with the result of surface roughness. The optimal condition of AlAs nucleation is estimated to be between 1.68 and 3.74 nm thickness. Moreover, a rough surface has the effect of enhancing the PL intensity due to light scattering [29]. These optimal samples of smoother surface have higher PL intensity although the smoother surface have less light scattering compared to others, which meaning a higher quantum efficiency. The AlAs thickness of 1.68 and 3.74 nm fulfilled great nucleation for high crystal quality of GaAs buffer in terms of quantum efficiency and surface roughness.

To characterize the TDD, there exist numerous techniques such as transmission electron microscopy, and defect-selective etch-pit density measurement, and cathodoluminescence [30]. An ECCI was reported as a suitable method to measure dislocations in epitaxial layers [31]. To implement ECCI, the electron beam was adjusted to have a high acceleration voltage and high current condition. The angle of the electron beam was tilted from 3° to 8° and the rotation angle to adjust electron channeling pattern. Figure 3(a) shows electron channeling pattern of GaAs buffer on Si. A white square mark indicates the excitation area consisting of both {0–40} and {−220} for ECCI measurement to satisfy a channeling condition. Figure 3(b) is measured ECCI image of first-step GaAs buffer of 1.68-nm-thick AlAs nucleation. Bright spots in the ECCI indicates threading dislocations where the density was measured to be 6.67 × 10⁸ /cm². We measured the ECCI of first-step GaAs buffer samples and the TDD was estimated to be 7.15, 5.44, 5.49, 6.67, 7.42, and 6.63 × 10⁸ /cm² for 0, 0.37, 0.56, 1.68, 3.74, and 7.48 nm-thick AlAs nucleation, respectively. Although AlAs nucleation thickness scarcely affected the TDD of first-step buffer, quantum efficiency and surface roughness were strongly enhanced for 1.68 nm- and 3.74 nm-thick AlAs nucleation. Thus, by using the first-step buffer with 0.56, 1.68, and 3.74 nm-thick AlAs nucleation, we grew three series samples of second-step GaAs full buffer on Si through repeating TCA and HT GaAs growth. The TDD was effectively reduced through the second-step GaAs buffer growth as shown in the ECCI of the full buffer of 1.68-nm-thick AlAs nucleation in Fig. 3(c). Figure 3(d) shows TDD from ECCI measurement of the GaAs full buffer samples of 0.56 nm-, 1.68 nm-, and 3.74 nm-thick AlAs nucleation. The measured TDD was 8.65, 5.45, and 5.57 × 10⁷ /cm² for AlAs nucleation thicknesses of 0.56, 1.68, and 3.74 nm, respectively. TDD of GaAs buffer was significantly reduced to about one-tenth of density of first-step buffer after repeating the TCA process and HT GaAs growth. As a result, we confirmed the optimal AlAs thickness for nucleation to be 1.68 nm, which provides the GaAs on Si of a low TDD as well as superior surface roughness and high quantum efficiency.

 

Fig. 3. (a) Electron channeling pattern of GaAs on Si with the white squared mark indicating the excitation area for ECCI. (b) ECCI image of first-step GaAs buffer on Si with 1.68-nm-thick AlAs nucleation. (c) ECCI image of second-step GaAs full buffer with 1.68-nm-thick AlAs nucleation. (d) TDD from ECCI measurement of the second-step GaAs buffer on Si after TCA process with different values of AlAs thickness. (e) Cross-section TEM image of the GaAs full buffer on Si with 1.68 nm-thick AlAs nucleation after TCA process. Dashed lines indicate interfaces of buffer layers.

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The GaAs full buffer on Si had as small total thickness as approximately 1.5 µm. By using the optimized GaAs on Si of 1.68 nm-thick optimal AlAs nucleation, a GaAs MQW LD structure was grown. We found that the measured TDD at the final LD layer was 2.5 × 10⁷ /cm². The cross-sectional TEM was measured to confirm threading dislocations of the GaAs full buffer on Si with optimized AlAs nucleation, as shown in Fig. 3(e). Large number of threading dislocations are shown in the LT/MT GaAs nearby the Si substrate. After growing HT GaAs and TCA, the TDD is markedly reduced where the upper guideline indicates the interface of first-step buffer. We confirmed that directly grown GaAs on Si had reduced TDD through TCA with HT GaAs. The edge-emitting broad stripe LD was fabricated with a cavity length and width of 1120 µm and 60 µm, respectively.

Figure 4(a) shows the light output power-current density-voltage (LIV) measurements for the GaAs MQW LD on Si, where the fabricated LD chip is shown in the inset image. The broad stripe LD was measured under c.w. and pulsed operation conditions with a pulse width of 1 µs and a duty cycle of 1% at 25°C. The IV curve shows typical diode behavior where series resistance was extracted as 2.8 Ω. Under pulsed operation condition, the measured threshold current density was 317 A/cm², which corresponded to 203.8 mA. The calculated slope efficiency was 0.12 W/A. Under c.w. operation at 25°C, the measured threshold current density was 643 A/cm², which corresponded to 432.4 mA, and the calculated slope efficiency was 0.082 W/A. Because the light output power was measured at a cleaved single side facet of the broad stripe LD, the light output power and slope efficiency could be improved after high reflection coating on the side facets. A maximum singe facet output power of 19.7 mW was obtained at an injection current density of 898.8 A/cm², where a thermal rollover of light output power was observed for c.w. operation at a higher current density than 898.8 A/cm². By contrast, under pulsed operation, the single facet output power of 138.1 mW was attained at an injection current density of 2.2 kA/cm² without rollover. Figure 4(b) shows emission spectra of the LD on Si at various injection currents under pulsed operation at 25 °C. We carried out an analysis of emission spectra under pulsed operation because of not sufficiently stable emission performance under c.w. operation at 25°C. At a lower injection current range than the threshold, broad spontaneous emission spectra were observed with full-width at half maximum (FWHM) of ∼ 28 nm with a peak wavelength of around 851 nm. As increasing current density higher than threshold, the peak intensity at 849 nm increased sharply with a narrow FWHM of ∼ 2.8 nm. We confirmed a typical lasing behavior of sudden linewidth narrowing with increasing current density than threshold as shown in the inset of Fig. 4(b). We measured various LD devices on Si to confirm the chip-to-chip uniformity. Seven different LD devices on Si had slope efficiencies of from 0.12 to 0.09 and threshold current densities of from 317 to 625 A/cm² under pulsed operation. We considered that the chip-to-chip variance was due to imperfection of fabrication and cleaving, where there were micro cracks and bowing in GaAs on Si originated from thermal expansion and lattice mismatch between GaAs and Si.

 

Fig. 4. (a) Light output-current-voltage characteristics of LD on Si under c.w. (red solid) and pulsed operation (red dash) at 25 °C. The inset is the optical microscope image of the broad stripe LD. (b) Emission spectra of LD on Si at various injection current densities under pulsed operation at 25 °C. The inset is FWHM as a function of injection current density.

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For a high TDD wafer, the QW laser was relatively difficult for laser operation compared to QD laser, because the carriers generated in QW have a higher possibility to meet defects, compared to carriers generated and highly confined in QDs. Therefore, the QW laser on Si suggested that the GaAs buffer had high enough quality. According to the reports about comparative studies of QD and QW lasers grown on Si, the QD lasers shows more superior lasing performance and more tolerable to TDD than QW lasers, due to efficient carrier capture and high thermal energy barriers in QDs preventing the carriers from migrating into defect states [32,33]. Thus, through adopting QD lasers on our GaAs buffer on Si, we could expect improved lasing performance such as threshold current density, slope efficiency, and operation temperature. We consider that the relatively low threshold current under pulsed operation of our LD structure was originated from the following reasons. The TCA process effectively reduces the TDD in spite of thin buffer thickness. A thin layer of GaAs on Si could avoid the issues of thermal expansion mismatch and crack in thick GaAs on Si. At the same time, AlAs nucleation enhanced the lateral growth of GaAs and the surface roughness. Moreover, the optimal thickness of AlAs nucleation founded in this study can aid in obtaining excellent performance of GaAs LD on Si. Our approach of hybrid technique of the TCA and optimized AlAs nucleation provided high-quality GaAs buffer and directly grown LDs on Si. Meanwhile, there were several reports that TDD could be additionally reduced by employing superlattice dislocation filtering layer combined with AlAs nucleation or TCA methods. Recently, low TDD was achieved by combining both the TCA and the dislocation filtering layer methods on V-groove patterned Si [28,34,35]. Consequently, we expect that GaAs LD on Si would be additionally improved, as a next step, by adopting the dislocation filtering layers together with both the TCA and optimized AlAs nucleation based-on this study.

4. Conclusion

We realized directly grown GaAs LD on Si(001) by implementing a hybrid technique of AlAs nucleation and TCA. This technique provides a twofold advantage, namely reducing the TDD with thin buffer thickness and improving surface roughness of GaAs on Si. We found that there exists the optimal AlAs thickness for nucleation through structural and optical analysis of a GaAs buffer by AFM and PL measurements. In particular, we quantitatively characterized the TDD of a GaAs on Si through ECCI measurement. The TDD was reduced to 5.45 × 10⁷ /cm² through optimized AlAs nucleation growth with TCA of GaAs buffer. Based on the optimized GaAs on Si, the GaAs MQW LD structure was grown with a TDD of 2.5 × 10⁷ /cm². An edge-emitting broad stripe LD on Si was successfully fabricated. The light output-current-voltage was measured for the LD on Si, and finally, the lasing operation at room temperature was confirmed with a threshold current density of 643 A/cm² under c.w. condition and 317 A/cm² under pulsed condition. The hybrid technique provides to obtain GaAs LDs directly grown on Si(001), which is a building block to realize silicon-based on-chip light sources.