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Conferences > OFC > 2015 > Th1G > Th1G.2

A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects

Akinori Hayakawa, Masaya Kibune, Asako Toda, Shinsuke Tanaka, Takasi Simoyama, Yanfei Chen, Tomoyuki Akiyama, Shigekazu Okumura, Takeshi Baba, Tomoyuki Akahoshi, Seiji Ueno, Kazunori Maruyama, Masahiko Imai, Jian Hong Jiang, Pradip Thachile, Tamer Riad, Shigeaki Sekiguchi, Suguru Akiyama, Yu Tanaka, Ken Morito, Daisuke Mizutani, Toshihiko Mori, Takuji Yamamoto, and Hiroji Ebe

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Abstract

We present a novel configuration of hybrid-integrated silicon photonic interconnects employing a bridge structure, and demonstrate 25 Gbps error-free operation between transmitter and receiver with power efficiency of 9.6 mW/Gbps including a serializer chip.

© 2015 Optical Society of America

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