Abstract

We present photonics technology based on a bulk-Si substrate for cost-sensitive dynamic random-access memory (DRAM) optical interface application. We summarize the progress on passive and active photonic devices using a local-crystallized Si waveguide fabricated by solid phase epitaxy or laser-induced epitaxial growth on bulk-Si substrate. The process of integration of a photonic integrated circuit (IC) with an electronic IC is demonstrated using a 65 nm DRAM periphery process on 300 mm wafers to prove the possibility of seamless integration with various complementary metal-oxide-semiconductor devices. Using the bulk-Si photonic devices, we show the feasibility of high-speed multidrop interface: the Mach–Zehnder interferometer modulators and commercial photodetectors are used to demonstrate four-drop link operation at 10Gb/s, and the transceiver chips with photonic die and electronic die work for the DDR3 DRAM interface at 1.6Gb/s under a 14 multidrop configuration.

© 2014 Chinese Laser Press

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2013 (3)

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

2012 (2)

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

R. Ramakrishnan, “CAP and cloud data management,” Computer 45, 43–49 (2012).
[CrossRef]

2010 (1)

S. Assefa, F. Xia, and Y. A. Vlasov, “Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects,” Nature 464, 80–84 (2010).
[CrossRef]

2009 (2)

M. E. Tolentino, J. Turner, and K. W. Cameron, “Memory MISER: improving main memory energy efficiency in servers,” IEEE Trans. Comput. 58, 336–350 (2009).
[CrossRef]

H. Fredriksson and C. Svensson, “Improvement potential and equalization example for multidrop DRAM memory buses,” IEEE Trans. Adv. Packag. 32, 675–682 (2009).
[CrossRef]

2008 (1)

S. Palermo, A. Emami-Neyestanak, and M. Horowitz, “A 90  nm CMOS 16  Gb/s transceiver for optical interconnects,” IEEE J. Solid-State Circuits 43, 1235–1246 (2008).
[CrossRef]

2007 (1)

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
[CrossRef]

2000 (3)

R. Forster, “Manchester encoding: opposing definitions resolved,” Eng. Sci. Educ. J. 9, 278–280 (2000).
[CrossRef]

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728–749 (2000).
[CrossRef]

L. Liao, D. Lim, A. Agarwal, X. Duan, K. Lee, and L. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29, 1380–1386 (2000).
[CrossRef]

1994 (1)

J. S. Custer, A. Polman, and H. M. van Pinxteren, “Erbium in crystal silicon: segregation and trapping during solid phase epitaxy of amorphous silicon,” J. Appl. Phys. 75, 2809–2817 (1994).
[CrossRef]

1993 (1)

J. S. Im, H.-J. Kim, and M. O. Thompson, “Phase transformation mechanisms involved in excimer laser crystallization of amorphous silicon films,” Appl. Phys. Lett. 63, 1969–1971 (1993).
[CrossRef]

Agarwal, A.

L. Liao, D. Lim, A. Agarwal, X. Duan, K. Lee, and L. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29, 1380–1386 (2000).
[CrossRef]

Andreotti, C.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Assefa, S.

S. Assefa, F. Xia, and Y. A. Vlasov, “Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects,” Nature 464, 80–84 (2010).
[CrossRef]

Bae, W.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Baehr-Jones, T.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Blum, A.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Bok, J.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Bok, J. K.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Bruennert, M.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Byun, H.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Byun, H. I.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

Cameron, K. W.

M. E. Tolentino, J. Turner, and K. W. Cameron, “Memory MISER: improving main memory energy efficiency in servers,” IEEE Trans. Comput. 58, 336–350 (2009).
[CrossRef]

Celli-Urbani, B.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Chetrit, Y.

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
[CrossRef]

Cho, C.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

Cho, K.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Cho, K. S.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Cho, K. Y.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

Cho, M.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

Choi, G.-H.

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

Choi, H.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Choi, H. M.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Choi, J.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Choi, J. S.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Choi, J.-H.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Choi, S.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Choi, S. H.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Choi, Y.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

Chokkalingam, S.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Chun, J.-H.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

Chung, C.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Chung, C. H.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

Chung, H.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Ciftcioglu, B.

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
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Custer, J. S.

J. S. Custer, A. Polman, and H. M. van Pinxteren, “Erbium in crystal silicon: segregation and trapping during solid phase epitaxy of amorphous silicon,” J. Appl. Phys. 75, 2809–2817 (1994).
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Ding, R.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Duan, X.

L. Liao, D. Lim, A. Agarwal, X. Duan, K. Lee, and L. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29, 1380–1386 (2000).
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Emami-Neyestanak, A.

S. Palermo, A. Emami-Neyestanak, and M. Horowitz, “A 90  nm CMOS 16  Gb/s transceiver for optical interconnects,” IEEE J. Solid-State Circuits 43, 1235–1246 (2008).
[CrossRef]

Forster, R.

R. Forster, “Manchester encoding: opposing definitions resolved,” Eng. Sci. Educ. J. 9, 278–280 (2000).
[CrossRef]

Fredriksson, H.

H. Fredriksson and C. Svensson, “Improvement potential and equalization example for multidrop DRAM memory buses,” IEEE Trans. Adv. Packag. 32, 675–682 (2009).
[CrossRef]

Friebe, D.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Galland, C.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Gopalakrishnan, K.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Gregorius, P.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Gu, Z.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Ha, K.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Ha, K. H.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

Han, J.-D.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

Han, S.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Hochberg, M.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Holzwarth, C. W.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies (Optical Society of America, 2008), paper CThKK5.

Hong, G.-M.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

Hong, S.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Hong, S. Y.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

Horowitz, M.

S. Palermo, A. Emami-Neyestanak, and M. Horowitz, “A 90  nm CMOS 16  Gb/s transceiver for optical interconnects,” IEEE J. Solid-State Circuits 43, 1235–1246 (2008).
[CrossRef]

Hoyt, J. L.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies (Optical Society of America, 2008), paper CThKK5.

Hyun, S.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Hyung, Y. W.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

Im, J. S.

J. S. Im, H.-J. Kim, and M. O. Thompson, “Phase transformation mechanisms involved in excimer laser crystallization of amorphous silicon films,” Appl. Phys. Lett. 63, 1969–1971 (1993).
[CrossRef]

Izhaky, N.

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
[CrossRef]

Jang, S.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

Jang, S.-J.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Jeong, D.-K.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

Jeong, G. T.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

Jeong, T.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Jeoung, H.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Ji, H.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Ji, H. C.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Ji, H.-C.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

Jin, G. Y.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

Joe, I.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Joe, I. S.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

Joe, I.-S.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Jun, I.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Jung, D.-H.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Jung, E.

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

Jung, E. S.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

Jung, H.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Kang, H.

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

Kang, S.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Kehrer, D.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Kim, B.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Kim, B. S.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

Kim, C.-W.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Kim, D.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Kim, H.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

Kim, H.-J.

J. S. Im, H.-J. Kim, and M. O. Thompson, “Phase transformation mechanisms involved in excimer laser crystallization of amorphous silicon films,” Appl. Phys. Lett. 63, 1969–1971 (1993).
[CrossRef]

Kim, J.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Kim, J. H.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Kim, J. M.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Kim, K.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Kim, S.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Kim, S. G.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

Kim, S. S.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

Kim, S.-G.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Kimerling, L.

L. Liao, D. Lim, A. Agarwal, X. Duan, K. Lee, and L. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29, 1380–1386 (2000).
[CrossRef]

Koren, I.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Kuh, B.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Kuh, B. J.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Kwon, H.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Lange, U.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Lee, B.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Lee, B. S.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Lee, D.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Lee, E.

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

Lee, H.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Lee, J.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Lee, J.-B.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Lee, K.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

L. Liao, D. Lim, A. Agarwal, X. Duan, K. Lee, and L. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29, 1380–1386 (2000).
[CrossRef]

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

Lee, K.-H.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

Lee, K.-W.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Lee, M.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

Lee, S.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Lee, S. Y.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Li, H.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies (Optical Society of America, 2008), paper CThKK5.

Liao, L.

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
[CrossRef]

L. Liao, D. Lim, A. Agarwal, X. Duan, K. Lee, and L. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29, 1380–1386 (2000).
[CrossRef]

Lim, A. E.-J.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Lim, D.

L. Liao, D. Lim, A. Agarwal, X. Duan, K. Lee, and L. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29, 1380–1386 (2000).
[CrossRef]

Lim, D.-H.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

Lim, J.

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

Lim, J. S.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Lindt, P.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Liu, A.

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
[CrossRef]

Liu, Y.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Lo, P. G.-Q.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Miller, D. A. B.

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728–749 (2000).
[CrossRef]

Na, K.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Na, K. W.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

Na, T.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Nam, J.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Nejadmalayeri, A.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Neumann, L.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Neuscheler, E.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Nguyen, H.

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
[CrossRef]

Novack, A.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Orcutt, J. S.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies (Optical Society of America, 2008), paper CThKK5.

Palermo, S.

S. Palermo, A. Emami-Neyestanak, and M. Horowitz, “A 90  nm CMOS 16  Gb/s transceiver for optical interconnects,” IEEE J. Solid-State Circuits 43, 1235–1246 (2008).
[CrossRef]

Paniccia, M.

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
[CrossRef]

Park, J.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Park, J.-S.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Park, K.-S.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

Park, S.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

Park, Y.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Park, Y. D.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

Parmar, S.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

Partovi, H.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Polman, A.

J. S. Custer, A. Polman, and H. M. van Pinxteren, “Erbium in crystal silicon: segregation and trapping during solid phase epitaxy of amorphous silicon,” J. Appl. Phys. 75, 2809–2817 (1994).
[CrossRef]

Popovic, M. A.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies (Optical Society of America, 2008), paper CThKK5.

Prete, E.

E. Prete, D. Scheideler, and A. Sanders, “A 100  mW 9.6  Gb/s transceiver in 90  nm CMOS for next-generation memory interfaces,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 253–262.

Pyo, J.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Pyo, J. H.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

Ram, R. J.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies (Optical Society of America, 2008), paper CThKK5.

Ramakrishnan, R.

R. Ramakrishnan, “CAP and cloud data management,” Computer 45, 43–49 (2012).
[CrossRef]

Ravezzi, L.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Rickes, T.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Rubin, D.

A. Liu, L. Liao, D. Rubin, H. Nguyen, B. Ciftcioglu, Y. Chetrit, N. Izhaky, and M. Paniccia, “High-speed optical modulation based on carrier depletion in a silicon waveguide,” Opt Express 15, 660–668 (2007).
[CrossRef]

Ruckerbauer, H.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Sanders, A.

E. Prete, D. Scheideler, and A. Sanders, “A 100  mW 9.6  Gb/s transceiver in 90  nm CMOS for next-generation memory interfaces,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 253–262.

Scheideler, D.

E. Prete, D. Scheideler, and A. Sanders, “A 100  mW 9.6  Gb/s transceiver in 90  nm CMOS for next-generation memory interfaces,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 253–262.

Schledz, R.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Schumacher, O.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Shim, D.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

Shim, Y.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Shin, D.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Shin, D. J.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

Shin, J.

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

Shin, J. H.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Shin, W.-Y.

W.-Y. Shin, G.-M. Hong, H. Lee, J.-D. Han, K.-S. Park, D.-H. Lim, S. Kim, D. Shim, J.-H. Chun, D.-K. Jeong, and S. Kim, “4-Slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8  Gb/s memory controller transceiver,” IEEE Trans Compon, Packag Manuf Technol, Part A 3, 858–869 (2013).
[CrossRef]

Shin, Y.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Shin, Y. H.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

Smith, H. I.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies (Optical Society of America, 2008), paper CThKK5.

Sohn, K.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Song, I.

K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, S. Hyun, H. Jeoung, K.-W. Lee, J.-S. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D.-H. Jung, B. Kim, J.-H. Choi, S.-J. Jang, C.-W. Kim, J.-B. Lee, and J. S. Choi, “A 1.2  V 30  nm 3.2  Gb/s/pin 4  Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” IEEE J. Solid-State Circuits 48, 168–177 (2013).
[CrossRef]

Stojanovic, V.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies (Optical Society of America, 2008), paper CThKK5.

Streibl, M.

Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

Streshinsky, M.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, C. Galland, A. E.-J. Lim, P. G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “The road to affordable, large-scale silicon photonics,” Opt. Photon. News 24, 32–39 (2013).
[CrossRef]

Suh, S.

K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
[CrossRef]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

Suh, S. D.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

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H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

Xia, F.

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K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
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K. Ha, D. Shin, H. Byun, K. Cho, K. Na, H. Ji, J. Pyo, S. Hong, K. Lee, B. Lee, Y. Shin, J. Kim, S. Kim, I. Joe, S. Suh, S. Choi, S. Han, Y. Park, H. Choi, B. Kuh, K. Kim, J. Choi, S. Park, H. Kim, K. Kim, J. Choi, H. Lee, S. Yang, S. Park, M. Lee, M. Cho, S. Kim, T. Jeong, S. Hyun, C. Cho, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, S. Jang, J. Choi, and C. Chung, “Si-based optical I/O for optical memory interface,” Proc. SPIE 8267, 82670F (2012).
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H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

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[CrossRef]

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[CrossRef]

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J. S. Custer, A. Polman, and H. M. van Pinxteren, “Erbium in crystal silicon: segregation and trapping during solid phase epitaxy of amorphous silicon,” J. Appl. Phys. 75, 2809–2817 (1994).
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H.-C. Ji, K. Cho, B. Lee, K. Cho, S. Choi, J. Kim, Y. Shin, S.-G. Kim, S. Lee, H. Byun, S. Parmar, A. Nejadmalayeri, D. Kim, J. Bok, Y. Park, D. Shin, I.-S. Joe, B. Kuh, B. Kim, K. Kim, H. Choi, and K. Ha, are preparing a manuscript to be called “Box-less waveguide Ge PD for bulk-Si based silicon photonic platform,” to be presented at Optical Fiber Communication Conference/National Fiber Optic Engineers Conference.

B. S. Lee, K. S. Cho, Y. H. Shin, J. H. Kim, J. K. Bok, S. G. Kim, D. J. Shin, S. Y. Lee, S. H. Choi, H. C. Ji, K. Y. Cho, H. I. Byun, I. S. Joe, B. J. Kuh, A. Nejadmalayeri, P. Sunil, J. H. Shin, J. S. Lim, B. S. Kim, H. M. Choi, K. H. Ha, G. T. Jeong, G. Y. Jin, and E. S. Jung, “Integration of photonic circuits with electronics on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 1–2.

J. Pyo, D. J. Shin, K. Lee, H. Ji, K. W. Na, K. S. Cho, S. G. Kim, I. S. Joe, S. D. Suh, Y. H. Shin, Y. Choi, S. Y. Hong, H. I. Byun, B. S. Lee, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s, 1 × 4 optical link for DRAM interconnect,” in 8th IEEE International Conference on Group IV Photonics (GFP) (2011), pp. 368–370.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J.-H. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 5–6.

D. J. Shin, K. S. Cho, H. C. Ji, B. S. Lee, S. G. Kim, J. K. Bok, S. H. Choi, Y. H. Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, B. J. Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, K. H. Ha, Y. D. Park, and C. H. Chung, “Integration of Si photonics into DRAM process,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference (Optical Society of America, 2013), paper OTu2C.4.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference and Exposition, and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

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Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer, “Cascading techniques for a high-speed memory interface,” in IEEE International Solid-State Circuits Conference (ISSCC 2007). Digest of Technical Papers (2007), pp. 234–599.

H. Partovi, W. Walthes, L. Ravezzi, P. Lindt, S. Chokkalingam, K. Gopalakrishnan, A. Blum, O. Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, and U. Lange, “Data recovery and retiming for the fully buffered DIMM 4.8  Gb/s serial links,” in IEEE International Solid-State Circuits Conference (ISSCC 2006). Digest of Technical Papers (2006), pp. 1314–1323.

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H.-C. Ji, K. H. Ha, K. W. Na, S. G. Kim, I. S. Joe, D. J. Shin, K.-H. Lee, S. D. Suh, J. K. Bok, Y. S. You, Y. W. Hyung, S. S. Kim, Y. D. Park, and C. H. Chung, “Bulk silicon photonic wire for one-chip integrated optical interconnection,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 96–98.

J. Shin, B. Kuh, J. Lim, B. Kim, E. Lee, D. Shin, K. Cho, B. Lee, K. Ha, H. Choi, G.-H. Choi, H. Kang, and E. Jung, “Epitaxial growth technology for optical interconnect based on bulk-Si platform,” in IEEE 10th International Conference on Group IV Photonics (GFP) (2013), pp. 3–4.

D. J. Shin, K.-H. Lee, H.-C. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “Mach–Zehnder silicon modulator on bulk silicon substrate: toward DRAM optical interface,” in 7th IEEE International Conference on Group IV Photonics (GFP) (2010), pp. 210–212.

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10  Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) (2011), pp. 1–3.

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Figures (20)

Fig. 1.
Fig. 1.

Simulated eye diagrams of memory bus with 4 DIMMs in one DDR3 memory channel.

Fig. 2.
Fig. 2.

Process steps for fabricating the waveguide on a bulk-Si substrate. C-Si: crystallized silicon, PR: photoresist.

Fig. 3.
Fig. 3.

SEM images after crystallization of deposited a-Si depending on annealing condition: (a) low, (b) medium, and (c) high temperature.

Fig. 4.
Fig. 4.

VSEM images of fabricated waveguide on the bulk-Si substrate.

Fig. 5.
Fig. 5.

Cross section of inlaid structure for LEG process.

Fig. 6.
Fig. 6.

High resolution TEM image and diffraction pattern: (a) SPE-Si and (b) LEG-Si.

Fig. 7.
Fig. 7.

(a) Cross-sectional diagram of the active part of the bulk-Si MZI modulator. (b) SEM image of the dotted region in (a). The inclined arrows indicate the boundary of the local oxide undercladding formed underneath the active part. (c) Microscope image. Dotted line indicates the location of (a) and (b).

Fig. 8.
Fig. 8.

Optical eye diagrams at NRZ 2311 PRBS signal at (a) 5Gb/s without de-emphasis and (b) 10Gb/s with de-emphasis.

Fig. 9.
Fig. 9.

(a) Lateral design of racetrack modulator with metal boundary illustrated. (b) Eye diagram at 1559.24 nm with 2.5Vpp driving.

Fig. 10.
Fig. 10.

(a) Microscope photography, (b) SEM image, and (c) 25Gbp/s eye diagram of Ge/Si surface photodetector.

Fig. 11.
Fig. 11.

Schematic diagram of waveguide-type photodetector (a) along the light propagation, and (b) perpendicular to the light propagation. (c) VSEM image, (d) 15Gb/s eye diagram at 1V bias, and (e) 25Gb/s eye diagram at 7V bias.

Fig. 12.
Fig. 12.

(a) Optical microscope image of EPIC, (b) schematic of EPIC vertical structure, and (c) SEM images of transistors, modulator, and Ge photodiode.

Fig. 13.
Fig. 13.

Performance of the bulk-Si photonic devices integrated into the DRAM process.

Fig. 14.
Fig. 14.

1×4 optical link configuration for multidrop memory bus.

Fig. 15.
Fig. 15.

Electrical eye diagram measured at channel 1–4 receiver: (a) through (d) with the transmitter in a QFP package, (e) through (h) on a bare die.

Fig. 16.
Fig. 16.

Block diagram of an optical interconnect transceiver. PD: photodiode, MOD: modulator.

Fig. 17.
Fig. 17.

(a) Photograph of dies for PIC and EIC. (b) Photograph of copackaged optical transceiver chip.

Fig. 18.
Fig. 18.

(a) Experiment setup to verify link operation using two optical transceivers. (b) and (c) Eye diagram at the output of optical amplifier at data rate of 1.5 and 2.5Gb/s.

Fig. 19.
Fig. 19.

(a) Photograph and (b) block diagram of the experiment setup to verify optically interconnected DRAM interface. A: optical amplifier.

Fig. 20.
Fig. 20.

(a) Block diagram of the experiment setup and (b) oscilloscope traces for DQ0 (blue) and DQS signals (red) at controller side and DRAM side with output enable signals (green).

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