Abstract

We simulate a simplified optical stack model with Lumerical FDTD over wide ranges of optical parameters: wavelength, 550 nm to 1.4 μm, and pixel array pitch, 1 to 10 μm. By increasing the lens and the planarization layer refractive indices from the usual 1.5 to 2, we study the improved lens focalization abilities, in terms of spot width, power, and depth below the micro-lens. We show an NIR wavelength range benefit from slightly increasing the optical stack index to 1.7 while visible wavelengths have less interest. Indeed, increasing the lens and planarization layer index enables thinner back-side illuminated optical stacks for higher quantum efficiencies and angular response improvement.

© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

1. Introduction

Complementary Metal Oxide Semiconductor (CMOS) imager market is always looking forward to increase the pixel quantum efficiency (QE) [13]. Previously, the light was entering through the metal stack which became thicker and thicker with increasing architecture complexity [4]. Optical systems were engineered in order to avoid light losses before reaching the photosensitive silicon volume [5]. Back-side illumination (BSI) together with 3D-stacking technologies are now well developed on the image sensor market [611]. These innovations enable a direct access of the light to the pixel pinned photodiode, now free of the back-end-of-line (BEOL) stack constraints. However, there is still room for improvement in the BSI optical stack when dealing with Near Infrared (NIR) wavelengths. Indeed, longer wavelengths are more easily diffracted than visible range so it is more challenging to have a satisfying light focus for maximal QE. Even with shorter photon path to the photosensitive region, this QE gain comes along with counterparts, the pixel crosstalk and the Parasitic Light Sensitivity (PLS) [1214]. This corresponds to absorbed photons in an unwanted region (neighboring pixels, floating diffusion memories, etc.) and this effect worsens in NIR. Metal shield is necessary to protect those regions, while having little metal reflection and metal absorption constraints. Indeed photons need to be strongly focused towards the photodiode through the metal window. Specifically, the micro-lens array can be optimized for focusing all the incoming light over the full pixel area towards the metal opening. This depends on target wavelength, pixel pitch, aperture size and optical stack refractive index engineering. In this paper, we simplify the optical stack to its essential features, in order to cover a wide range of applications. We discuss how to define the focalization power of a micro-lens array from 2D Finite Difference Time Domain (FDTD) simulation power profiles [15]. We optimize micro-lenses for a wide range of wavelengths (visible to $\lambda =1.4\,\mu m$ NIR) and a wide range of pixel pitch ($1\,\mu m$ to $10\,\mu m$). Indeed, the study is not limited to silicon based imagers, including Short-Wave Infrared (SWIR) applications. More importantly the interest in increasing micro-lens index from 1.5 to 2 is discussed.

Our interest is first to understand the different regimes of a micro-lens, then compare its behavior in the visible and the NIR ranges. Finally, our goal is to demonstrate the need for higher organic material refractive index, especially in NIR which is particularly constraining in terms of light focalization. We show that there is an interest in designing the planarization layer, its refractive index and its thickness together with the micro-lens to optimize the focalization power of the stack and in return the pixel QE.

2. Simulation set-up description

The study relies on 2D FDTD simulations with Lumerical software with only 4 parameters: the pixel pitch $P$, the wavelength $\lambda$, the lens refractive index $n_{lens}$ and aspect ratio $H$ (the lens height over the pitch). The objective is to find the focal point below the lens in order to set the planarization layer thickness between the lens and the silicon surface or the metal aperture. The model of the micro-lens (Fig. 1) is half an ellipse with variable aspect ratio up to 0.5 (half sphere) and variable refractive index $n_{lens}$. The lens is simply laid on a thick silicon oxide ($15\,\mu m$). An ideal anti-reflective coating is added on top of the lens, which refractive index is $\sqrt {n_{lens}}$ and its thickness being $\lambda /4\sqrt {n_{lens}}$. The background index above the lens is 1. A plane wave is injected with 0° polarization angle (P-polarization). Top and bottom boundaries of the simulated region (orange box in Fig. 1) are perfectly matched layers, serving to absorb any light outgoing from the simulated window. Left and right boundaries are periodic. The width of the region determines the pixel pitch and the ellipse width. As a 2D simulation, the third dimension is supposed infinitely uniform. The simulations do not include a photosensitive material beneath the lens and the effect of an interface between a low index optical stack and a higher index absorbing material, usually silicon. The center wavelength is variable from $550\,nm$ in the visible to $1.4\,\mu m$ in NIR, with $40\,nm$ wavelength width (the plane wave source span). From 2D Poynting vector profiles versus wavelength (Fig. 2(a)), the power profile is convolved with a Lorentzian weighting $h(\lambda )$ (Fig. 2(b)), chosen to giving a realistic temporal coherence for a source $FWHM = 40\,nm$ ($25\,fs$ coherence time at $500\,nm$ wavelength, $70\,fs$ at $940\,nm$, $150\,fs$ at $1.4\,\mu m$) [15]. This is consistent with the LED light sources that are used in our characterization laboratory for green and NIR illumination.

The focalization power of the micro-lens must be defined from power profiles. In order to find the best figure of merit, different metrics can be derived from the encircled energy (Fig. 2(c)). To do so, we integrate the power along the horizontal direction. After normalization, one can derive:

  • • A spot width with $90\,\%$ encircled energy $W$, at the shallowest depth possible $D$
  • • A focalization power given by the average power between 0 and $90\,\%$ of encircled energy $FP$, minimized against depth at $D'$

 figure: Fig. 1.

Fig. 1. (a) 2D FDTD simulation set-up and (b) refractive index profile as input to the solver.

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 figure: Fig. 2.

Fig. 2. Processing of the power profile simulation results for a $1.9\,\mu m$ pitch at $550\, nm$ wavelength ($H=0.46\times \,P$, $n_{lens}=1.5$): (a) 2D profile at peak wavelength, (b) wavelength averaging and (c) encircled energy derivation.

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A thin-lens model can be used comparatively with FDTD simulations [16]. The lens maker formula predicts that the focal length is inversely proportional to the lens refractive index. However, as micro-lenses are generally thin optical elements of a thickness comparable to the incident light wavelength, diffraction effects may apply. FDTD numerical solution of the Maxwell equations is hence expected to give more accurate results. In paragraph 4.1 discussion, the results are compared with the lens maker equation predictions. In order to evaluate the contribution of diffraction to our results, the simulation setup is compared with another trial where periodic boundaries are up to five times wider than the lens footprint. Due to periodic boundaries, there are some cases where the micro-lens array itself generates secondary focal spots along the depth (Fig. 2). This effect disappears when the FDTD region width is large. The array periodicity is creating these constructive interferences in the case of an infinite non absorbing substrate. Indeed, only the first spot below the lens is interesting, thus a fast Fourier transform is used to identify any periodicity against depth in the encircled energy profile and limit the analysis to its first period.

3. Preliminary analysis at $1\,\mu m$ depth

In a first study, we assume that the optical stack thickness is constrained by a fixed planarization layer thickness in-between the lens and the silicon surface (or the metal shield layer). The planarization layer thickness, between the lens and the metal aperture, is fixed at $1\,\mu m$, where the focalization is aimed. The simulation is still as simple as a lens on silicon oxide substrate, without metal nor silicon. The planarization layer refractive index is silicon oxide. Unlike in the final section, it is not adjusted to the variable lens index (1.5 to 2). For simplicity, Fig. 3 shows only the extreme cases of lens refractive indices (1.5 and 2) and wavelengths ($550\,nm$ and $1.4\,\mu m$). Color scales are shared on all width graphs of Fig. 3(a) and black line levels are $1\,\mu m$ width of spot size apart. We can see that the spot width is nearly half the pitch for $90\,\%$ encircled energy ($W$) when the aspect ratio is the highest. We see that the higher the aspect ratio, the smaller (better) the spot diameter is ($W\approx 25\,\%$ of the pitch). Finally, we show that increasing the lens refractive index decreases the spot width at any wavelength. These conclusions are confirmed when looking at power focalization profiles (Fig. 3(b)), the focal power increases when the spot width decreases.

In order to know whether a metal shield can be used at $1\, \mu m$ depth below the lens, we consider a typical metal shield, usually $400\,nm$ wide around the pixel. To highlight this, the overlaid white line at the bottom right of the graphs (Fig. 3)) indicates spot widths exceeding $pitch - 2\times 400\,nm$. Below this line, the spot size is obviously too large, leading to absorption or reflection on the metal shield, this amount of light is not getting through the metal aperture to the photosensitive layer.

 figure: Fig. 3.

Fig. 3. Simulation results at $1\,\mu m$ thick optical stack: (a) spot width $W\,(\mu m)$ and (b) Poynting power (normalized to source power).

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In summary, apart from very small micro-lens aspect ratios, the metal aperture is not limiting the light transmission. In this case, integrating high refractive index lenses in CMOS imager technology is not worth the effort, but it helps to decrease further the spot diameter.

4. Optimized optical stack thickness results and discussion

A second analysis consists in using the planarization layer thickness as a parameter which controls the distance between the lens and the metal shield. First, the lens index alone is tuned while the planarization layer material is still silicon oxide. In this new study, the lens focal length does not matter anymore, only focalization performances do. Indeed, only the minimum spot width against depth and the maximum focalization power are extracted. As a summary, the best design is chosen among all simulated lens aspect ratios ($H$) in terms of minimum spot width for a given pixel pitch, lens index and wavelength.

4.1 Visible wavelengths

In the visible range ($550\,nm$), two behaviors are observed (Fig. 4). For small pitch optical stacks (below $4\,\mu m$), the optimal designs showing minimal spot widths are not always the half sphere. Thanks to a closer look at power profiles (Fig. 5) of additional simulations embedding a silicon interface (with an ideal anti-reflective layer), we assume that the lattice may contribute to focalization along with the lens, so that the aspect ratio needs to be engineered accordingly. The focalization depth is indeed near $1-2\,\mu m$ (half the pitch $P$), significantly lower than the thin lens approximation of the focal length: $f=ROC\times n_{planar}/(n_{lens}-1)\approx 3-6\,\mu m$ where $n_{planar}$ is the planarization layer refractive index and $ROC$ is the radius of curvature of the lens (its height $H\times P$) [16]. The $90\,\%$ energy spot width is around $0.2\times P$, much lower than the diffraction limits, as compared with the Airy pattern far field spot diameter ($d=2.44\times f_\sharp \times \lambda$, where $f_\sharp$ is the f number) [17].

In summary, for small pitch targeting visible applications, there is no need to increase the lens refractive index. It is important to note that as the pitch decreases, the optimal spot width increases. It is explained by diffraction limits [2]. The lens starts to be much thinner than the wavelength so that the wave does not feel the curved surface anymore but an average refractive index between air and lens index.

 figure: Fig. 4.

Fig. 4. Simulation results at focal depth for varying lens refractive index ($1.5$ to $2$) at $550\,nm$ wavelength: (a) minimal spot width $W_1$, corresponding (b) optimal lens height, (c) focal depth and (d) Poynting power.

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 figure: Fig. 5.

Fig. 5. (a) Encircled energy width $W$ inside $2\,\mu m$ thick planarization layer with lens on top and silicon layer below for a $4\,\mu m$ pixel pitch at $550\,nm$ wavelength, (b) and (c) corresponding power profiles showing equivalently optimal spot widths at silicon interface.

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In the visible range, increasing the lens refractive index has only an interest for larger pitch (Fig. 4). We can see that the aspect ratio optimization is not at stake anymore 4(b). However, affording the highest refractive index for the lens ($n_{lens}=2$), we can almost pin the focal point depth below $2\,\mu m$ with an encircled energy width around $P/10$ up to $P=10\,\mu m$, while it was beyond process capabilities (above $4\,\mu m$ planarization layer thickness) with $n_{lens}=1.5$.

4.2 Near-infrared BSI optical stack optimization

In NIR ($940\,nm$ and $1400\,nm$), the same simulations were carried out with another constraint: the planarization layer refractive index must match the lens index (Fig. 6). Indeed, the final optical stack with high index lens, low index planarization layer and again a high index photosensitive layer creates a cavity within the planarization layer, leading to unwanted interferences for longer wavelengths. By matching the planarization layer and the lens indices, the NIR wavelengths ($940\,nm$ and $1.4\,\mu m$) show the same kind of optimizations than in the previous section in the case of large pitch optimization. In summary, the higher the lens and the planarization layer refractive indices, the better the focalization depth and the spot width. This extends to improving pixel angular response since thinner planarization layer means wider angular acceptance to the photosensitive zone. It is noticed that the small pitch diffraction limit is even more sensitive than at $550\,nm$ wavelength. Using higher organic layer refractive index, we show an improvement in NIR stacks featuring a realistic optical stack with all necessary layers and an accurate micro-lens profile obtained from physical characterizations. By increasing the lens and planarization layer refractive index to 1.7, simulations show that both the lens aspect ratio and the planarization layer thickness can be decreased by 30% without penalty on quantum efficiency. The metal absorption losses at the pixel entrance are decreased by more than $30\,\%$ and the pixel angular response is extremely good at $940\,nm$: $-31\,\%$ of transmission at 30° source angle as compared to on-axis transmission through the silicon interface ($-66\,\%$ with $n_{lens}=1.5$). Overall off-axis pixel response can be further improved by using lens shifting on the array’s periphery.

5. Conclusion

In conclusion, we demonstrated the use of a simple simulation setup for micro-lens array optical stack optimization. Visible applications have little interest in higher index micro-lenses. Nevertheless, the study shows the different regimes of the lens: the lower the pitch the wider the focal spot (normalized to the pitch, $W/P$) because of diffraction limits, while for larger pitch the focal spot diameter saturates near $10\,\%$ of the pitch. The main outcome is the interest in a higher organic material refractive index than usual for NIR imaging applications. This drastically improves the focalization abilities of the lens array in NIR range, in order to pass the metal shield pixel entrance, showing $400\,nm$ to $100\,nm$ focal spot width (depending on pixel array pitch), defined as $90\,\%$ of encircled energy. The added benefit is a drastic improvement of the BSI pixel angular response, even in NIR.

 figure: Fig. 6.

Fig. 6. Simulation results at focal depth for varying lens (and planarization layer) refractive indices ($1.5$ to $2$) at $940\,nm$ wavelength: (a) minimal spot width $W$, (b) corresponding optimal lens height, (c) corresponding focal depth and (d) corresponding Poynting power.

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Disclosures

The authors declare no conflicts of interest.

References

1. A. Theuwissen, “CMOS image sensors: State-of-the-art,” Solid-State Electron. 52(9), 1401–1406 (2008). [CrossRef]  

2. A. Brückner and M. Schöberl, “Diffraction and photometric limits in today’s miniature digital camera systems,” Proc. SPIE 8616, 861617 (2013). [CrossRef]  

3. A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J.-P. Carrere, F. Hirigoyen, L. Grant, and F. Roy, “Pixel-to-pixel isolation by deep trench technology : application to CMOS image sensor,” IISW R5, (2011).

4. I. Mizuno, M. Tsutsui, T. Yokoyama, T. Hirata, Y. Nishi, D. Veinger, A. Birman, and A. Lahav, “A high-performance 2.5 μm charge domain global shutter pixel and near infrared enhancement with light pipe technology,” Sensors 20(1), 307 (2020). [CrossRef]  

5. S. Velichko, J. Hynecek, R. S. Johnson, V. Lenchenkov, H. Komori, H. W. Lee, and F. J. Chen, “CMOS global shutter charge storage pixels with improved performance,” IEEE Trans. Electron Devices 63(1), 106–112 (2016). [CrossRef]  

6. R. Fontaine, “The state-of-the-art of smartphone imagers,” International Image Sensors Workshop R01, (2019).

7. F. Lalanne, P. Malinge, D. Hérault, C. Jamin-Mornet, and N. Virollet, “A 750 k photocharge linear full well in a 3.2 μm HDR pixel with complementary carrier collection,” Sensors 18(2), 305 (2018). [CrossRef]  

8. S. Yokogawa, “Nanophotonics contributions to state-of-the-art CMOS image sensors,” 2019 IEEE International Electron Devices Meeting 16(1), 1–4 (2019). [CrossRef]  

9. C. T. Ko and K. N. Chen, “Wafer-level bonding/stacking technology for 3D integration,” Microelectron. Reliab. 50(4), 481–488 (2010). [CrossRef]  

10. S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

11. G. Park, L. A. Grant, A. C.-W. Hsuing, K. Mabuchi, J. M. Yao, Z. Lin, V. C. Venezia, T. Yu, Y.-S. Yang, and T. Dai, “A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor,” 2019 IEEE Int. Electron Devices Meet.16(4), 1–4 (2019).

12. F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. B. de Boisanger, R. M. Sauvage, and P. Magnan, “An efficient method for modeling parasitic light sensitivity in global shutter CMOS image sensors,” 2019 Int. Conf. on Simul. Semicond. Process. Devices, pp. 1–4 (2019).

13. T. Yokoyama, M. Tsutsui, M. Suzuki, Y. Nishi, I. Mizuno, and A. Lahav, “Development of low parasitic light sensitivity and low dark current 2.8 μm global shutter pixel,” Sensors 18(2), 349 (2018). [CrossRef]  

14. Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, and T. Asami, “Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor,” 2012 Int. Electron Devices Meet.24(2), 1–4 (2012).

15. X. Lumerical, “CMOS image sensors - list of examples,” https://support.lumerical.com/hc/en-us/articles/360043165614-CMOS-image-sensors-list-of-examples.

16. Y. Huo, C. C. Fesenmaier, and P. B. Catrysse, “Microlens performance limits in sub-2μm pixel CMOS image sensors,” Opt. Express 18(6), 5861–5872 (2010). [CrossRef]  

17. J. D. Jackson, Classical electrodynamics, (John Wiley & Sons, Inc., 1999).

References

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  • |

  1. A. Theuwissen, “CMOS image sensors: State-of-the-art,” Solid-State Electron. 52(9), 1401–1406 (2008).
    [Crossref]
  2. A. Brückner and M. Schöberl, “Diffraction and photometric limits in today’s miniature digital camera systems,” Proc. SPIE 8616, 861617 (2013).
    [Crossref]
  3. A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J.-P. Carrere, F. Hirigoyen, L. Grant, and F. Roy, “Pixel-to-pixel isolation by deep trench technology : application to CMOS image sensor,” IISW R5, (2011).
  4. I. Mizuno, M. Tsutsui, T. Yokoyama, T. Hirata, Y. Nishi, D. Veinger, A. Birman, and A. Lahav, “A high-performance 2.5 μm charge domain global shutter pixel and near infrared enhancement with light pipe technology,” Sensors 20(1), 307 (2020).
    [Crossref]
  5. S. Velichko, J. Hynecek, R. S. Johnson, V. Lenchenkov, H. Komori, H. W. Lee, and F. J. Chen, “CMOS global shutter charge storage pixels with improved performance,” IEEE Trans. Electron Devices 63(1), 106–112 (2016).
    [Crossref]
  6. R. Fontaine, “The state-of-the-art of smartphone imagers,” International Image Sensors Workshop R01, (2019).
  7. F. Lalanne, P. Malinge, D. Hérault, C. Jamin-Mornet, and N. Virollet, “A 750 k photocharge linear full well in a 3.2 μm HDR pixel with complementary carrier collection,” Sensors 18(2), 305 (2018).
    [Crossref]
  8. S. Yokogawa, “Nanophotonics contributions to state-of-the-art CMOS image sensors,” 2019 IEEE International Electron Devices Meeting 16(1), 1–4 (2019).
    [Crossref]
  9. C. T. Ko and K. N. Chen, “Wafer-level bonding/stacking technology for 3D integration,” Microelectron. Reliab. 50(4), 481–488 (2010).
    [Crossref]
  10. S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).
  11. G. Park, L. A. Grant, A. C.-W. Hsuing, K. Mabuchi, J. M. Yao, Z. Lin, V. C. Venezia, T. Yu, Y.-S. Yang, and T. Dai, “A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor,” 2019 IEEE Int. Electron Devices Meet.16(4), 1–4 (2019).
  12. F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. B. de Boisanger, R. M. Sauvage, and P. Magnan, “An efficient method for modeling parasitic light sensitivity in global shutter CMOS image sensors,” 2019 Int. Conf. on Simul. Semicond. Process. Devices, pp. 1–4 (2019).
  13. T. Yokoyama, M. Tsutsui, M. Suzuki, Y. Nishi, I. Mizuno, and A. Lahav, “Development of low parasitic light sensitivity and low dark current 2.8 μm global shutter pixel,” Sensors 18(2), 349 (2018).
    [Crossref]
  14. Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, and T. Asami, “Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor,” 2012 Int. Electron Devices Meet.24(2), 1–4 (2012).
  15. X. Lumerical, “CMOS image sensors - list of examples,” https://support.lumerical.com/hc/en-us/articles/360043165614-CMOS-image-sensors-list-of-examples .
  16. Y. Huo, C. C. Fesenmaier, and P. B. Catrysse, “Microlens performance limits in sub-2μm pixel CMOS image sensors,” Opt. Express 18(6), 5861–5872 (2010).
    [Crossref]
  17. J. D. Jackson, Classical electrodynamics, (John Wiley & Sons, Inc., 1999).

2020 (1)

I. Mizuno, M. Tsutsui, T. Yokoyama, T. Hirata, Y. Nishi, D. Veinger, A. Birman, and A. Lahav, “A high-performance 2.5 μm charge domain global shutter pixel and near infrared enhancement with light pipe technology,” Sensors 20(1), 307 (2020).
[Crossref]

2019 (1)

S. Yokogawa, “Nanophotonics contributions to state-of-the-art CMOS image sensors,” 2019 IEEE International Electron Devices Meeting 16(1), 1–4 (2019).
[Crossref]

2018 (2)

T. Yokoyama, M. Tsutsui, M. Suzuki, Y. Nishi, I. Mizuno, and A. Lahav, “Development of low parasitic light sensitivity and low dark current 2.8 μm global shutter pixel,” Sensors 18(2), 349 (2018).
[Crossref]

F. Lalanne, P. Malinge, D. Hérault, C. Jamin-Mornet, and N. Virollet, “A 750 k photocharge linear full well in a 3.2 μm HDR pixel with complementary carrier collection,” Sensors 18(2), 305 (2018).
[Crossref]

2016 (1)

S. Velichko, J. Hynecek, R. S. Johnson, V. Lenchenkov, H. Komori, H. W. Lee, and F. J. Chen, “CMOS global shutter charge storage pixels with improved performance,” IEEE Trans. Electron Devices 63(1), 106–112 (2016).
[Crossref]

2013 (1)

A. Brückner and M. Schöberl, “Diffraction and photometric limits in today’s miniature digital camera systems,” Proc. SPIE 8616, 861617 (2013).
[Crossref]

2010 (2)

Y. Huo, C. C. Fesenmaier, and P. B. Catrysse, “Microlens performance limits in sub-2μm pixel CMOS image sensors,” Opt. Express 18(6), 5861–5872 (2010).
[Crossref]

C. T. Ko and K. N. Chen, “Wafer-level bonding/stacking technology for 3D integration,” Microelectron. Reliab. 50(4), 481–488 (2010).
[Crossref]

2008 (1)

A. Theuwissen, “CMOS image sensors: State-of-the-art,” Solid-State Electron. 52(9), 1401–1406 (2008).
[Crossref]

Aikawa, H.

Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, and T. Asami, “Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor,” 2012 Int. Electron Devices Meet.24(2), 1–4 (2012).

Asami, T.

Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, and T. Asami, “Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor,” 2012 Int. Electron Devices Meet.24(2), 1–4 (2012).

Birman, A.

I. Mizuno, M. Tsutsui, T. Yokoyama, T. Hirata, Y. Nishi, D. Veinger, A. Birman, and A. Lahav, “A high-performance 2.5 μm charge domain global shutter pixel and near infrared enhancement with light pipe technology,” Sensors 20(1), 307 (2020).
[Crossref]

Brückner, A.

A. Brückner and M. Schöberl, “Diffraction and photometric limits in today’s miniature digital camera systems,” Proc. SPIE 8616, 861617 (2013).
[Crossref]

Carrere, J.-P.

A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J.-P. Carrere, F. Hirigoyen, L. Grant, and F. Roy, “Pixel-to-pixel isolation by deep trench technology : application to CMOS image sensor,” IISW R5, (2011).

Catrysse, P. B.

Chao, Y. P.

S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

Chen, F. J.

S. Velichko, J. Hynecek, R. S. Johnson, V. Lenchenkov, H. Komori, H. W. Lee, and F. J. Chen, “CMOS global shutter charge storage pixels with improved performance,” IEEE Trans. Electron Devices 63(1), 106–112 (2016).
[Crossref]

Chen, K. N.

C. T. Ko and K. N. Chen, “Wafer-level bonding/stacking technology for 3D integration,” Microelectron. Reliab. 50(4), 481–488 (2010).
[Crossref]

Cherault, N.

A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J.-P. Carrere, F. Hirigoyen, L. Grant, and F. Roy, “Pixel-to-pixel isolation by deep trench technology : application to CMOS image sensor,” IISW R5, (2011).

Chou, K. Y.

S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

Chou, P. S.

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S. Velichko, J. Hynecek, R. S. Johnson, V. Lenchenkov, H. Komori, H. W. Lee, and F. J. Chen, “CMOS global shutter charge storage pixels with improved performance,” IEEE Trans. Electron Devices 63(1), 106–112 (2016).
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S. Velichko, J. Hynecek, R. S. Johnson, V. Lenchenkov, H. Komori, H. W. Lee, and F. J. Chen, “CMOS global shutter charge storage pixels with improved performance,” IEEE Trans. Electron Devices 63(1), 106–112 (2016).
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F. Lalanne, P. Malinge, D. Hérault, C. Jamin-Mornet, and N. Virollet, “A 750 k photocharge linear full well in a 3.2 μm HDR pixel with complementary carrier collection,” Sensors 18(2), 305 (2018).
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S. Velichko, J. Hynecek, R. S. Johnson, V. Lenchenkov, H. Komori, H. W. Lee, and F. J. Chen, “CMOS global shutter charge storage pixels with improved performance,” IEEE Trans. Electron Devices 63(1), 106–112 (2016).
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S. Velichko, J. Hynecek, R. S. Johnson, V. Lenchenkov, H. Komori, H. W. Lee, and F. J. Chen, “CMOS global shutter charge storage pixels with improved performance,” IEEE Trans. Electron Devices 63(1), 106–112 (2016).
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A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J.-P. Carrere, F. Hirigoyen, L. Grant, and F. Roy, “Pixel-to-pixel isolation by deep trench technology : application to CMOS image sensor,” IISW R5, (2011).

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S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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G. Park, L. A. Grant, A. C.-W. Hsuing, K. Mabuchi, J. M. Yao, Z. Lin, V. C. Venezia, T. Yu, Y.-S. Yang, and T. Dai, “A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor,” 2019 IEEE Int. Electron Devices Meet.16(4), 1–4 (2019).

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F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. B. de Boisanger, R. M. Sauvage, and P. Magnan, “An efficient method for modeling parasitic light sensitivity in global shutter CMOS image sensors,” 2019 Int. Conf. on Simul. Semicond. Process. Devices, pp. 1–4 (2019).

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F. Lalanne, P. Malinge, D. Hérault, C. Jamin-Mornet, and N. Virollet, “A 750 k photocharge linear full well in a 3.2 μm HDR pixel with complementary carrier collection,” Sensors 18(2), 305 (2018).
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F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. B. de Boisanger, R. M. Sauvage, and P. Magnan, “An efficient method for modeling parasitic light sensitivity in global shutter CMOS image sensors,” 2019 Int. Conf. on Simul. Semicond. Process. Devices, pp. 1–4 (2019).

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F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. B. de Boisanger, R. M. Sauvage, and P. Magnan, “An efficient method for modeling parasitic light sensitivity in global shutter CMOS image sensors,” 2019 Int. Conf. on Simul. Semicond. Process. Devices, pp. 1–4 (2019).

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Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, and T. Asami, “Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor,” 2012 Int. Electron Devices Meet.24(2), 1–4 (2012).

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T. Yokoyama, M. Tsutsui, M. Suzuki, Y. Nishi, I. Mizuno, and A. Lahav, “Development of low parasitic light sensitivity and low dark current 2.8 μm global shutter pixel,” Sensors 18(2), 349 (2018).
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I. Mizuno, M. Tsutsui, T. Yokoyama, T. Hirata, Y. Nishi, D. Veinger, A. Birman, and A. Lahav, “A high-performance 2.5 μm charge domain global shutter pixel and near infrared enhancement with light pipe technology,” Sensors 20(1), 307 (2020).
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T. Yokoyama, M. Tsutsui, M. Suzuki, Y. Nishi, I. Mizuno, and A. Lahav, “Development of low parasitic light sensitivity and low dark current 2.8 μm global shutter pixel,” Sensors 18(2), 349 (2018).
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G. Park, L. A. Grant, A. C.-W. Hsuing, K. Mabuchi, J. M. Yao, Z. Lin, V. C. Venezia, T. Yu, Y.-S. Yang, and T. Dai, “A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor,” 2019 IEEE Int. Electron Devices Meet.16(4), 1–4 (2019).

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A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J.-P. Carrere, F. Hirigoyen, L. Grant, and F. Roy, “Pixel-to-pixel isolation by deep trench technology : application to CMOS image sensor,” IISW R5, (2011).

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A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J.-P. Carrere, F. Hirigoyen, L. Grant, and F. Roy, “Pixel-to-pixel isolation by deep trench technology : application to CMOS image sensor,” IISW R5, (2011).

Roy, F.

A. Tournier, F. Leverd, L. Favennec, C. Perrot, L. Pinzelli, M. Gatefait, N. Cherault, D. Jeanjean, J.-P. Carrere, F. Hirigoyen, L. Grant, and F. Roy, “Pixel-to-pixel isolation by deep trench technology : application to CMOS image sensor,” IISW R5, (2011).

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F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. B. de Boisanger, R. M. Sauvage, and P. Magnan, “An efficient method for modeling parasitic light sensitivity in global shutter CMOS image sensors,” 2019 Int. Conf. on Simul. Semicond. Process. Devices, pp. 1–4 (2019).

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F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. B. de Boisanger, R. M. Sauvage, and P. Magnan, “An efficient method for modeling parasitic light sensitivity in global shutter CMOS image sensors,” 2019 Int. Conf. on Simul. Semicond. Process. Devices, pp. 1–4 (2019).

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T. Yokoyama, M. Tsutsui, M. Suzuki, Y. Nishi, I. Mizuno, and A. Lahav, “Development of low parasitic light sensitivity and low dark current 2.8 μm global shutter pixel,” Sensors 18(2), 349 (2018).
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S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, and T. Asami, “Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor,” 2012 Int. Electron Devices Meet.24(2), 1–4 (2012).

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Tran, L.

S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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I. Mizuno, M. Tsutsui, T. Yokoyama, T. Hirata, Y. Nishi, D. Veinger, A. Birman, and A. Lahav, “A high-performance 2.5 μm charge domain global shutter pixel and near infrared enhancement with light pipe technology,” Sensors 20(1), 307 (2020).
[Crossref]

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S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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Y. Kitamura, H. Aikawa, K. Kakehi, T. Yousyou, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, and T. Asami, “Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor,” 2012 Int. Electron Devices Meet.24(2), 1–4 (2012).

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I. Mizuno, M. Tsutsui, T. Yokoyama, T. Hirata, Y. Nishi, D. Veinger, A. Birman, and A. Lahav, “A high-performance 2.5 μm charge domain global shutter pixel and near infrared enhancement with light pipe technology,” Sensors 20(1), 307 (2020).
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G. Park, L. A. Grant, A. C.-W. Hsuing, K. Mabuchi, J. M. Yao, Z. Lin, V. C. Venezia, T. Yu, Y.-S. Yang, and T. Dai, “A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor,” 2019 IEEE Int. Electron Devices Meet.16(4), 1–4 (2019).

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F. Lalanne, P. Malinge, D. Hérault, C. Jamin-Mornet, and N. Virollet, “A 750 k photocharge linear full well in a 3.2 μm HDR pixel with complementary carrier collection,” Sensors 18(2), 305 (2018).
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S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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S. G. Wuu, C. C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh, and L. Tran, “A leading-edge 0.9 μm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” Tech. Dig. - Int. Electron Devices Meet. IEDM332-335, (2010).

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Figures (6)

Fig. 1.
Fig. 1. (a) 2D FDTD simulation set-up and (b) refractive index profile as input to the solver.
Fig. 2.
Fig. 2. Processing of the power profile simulation results for a $1.9\,\mu m$ pitch at $550\, nm$ wavelength ( $H=0.46\times \,P$ , $n_{lens}=1.5$ ): (a) 2D profile at peak wavelength, (b) wavelength averaging and (c) encircled energy derivation.
Fig. 3.
Fig. 3. Simulation results at $1\,\mu m$ thick optical stack: (a) spot width $W\,(\mu m)$ and (b) Poynting power (normalized to source power).
Fig. 4.
Fig. 4. Simulation results at focal depth for varying lens refractive index ( $1.5$ to $2$ ) at $550\,nm$ wavelength: (a) minimal spot width $W_1$ , corresponding (b) optimal lens height, (c) focal depth and (d) Poynting power.
Fig. 5.
Fig. 5. (a) Encircled energy width $W$ inside $2\,\mu m$ thick planarization layer with lens on top and silicon layer below for a $4\,\mu m$ pixel pitch at $550\,nm$ wavelength, (b) and (c) corresponding power profiles showing equivalently optimal spot widths at silicon interface.
Fig. 6.
Fig. 6. Simulation results at focal depth for varying lens (and planarization layer) refractive indices ( $1.5$ to $2$ ) at $940\,nm$ wavelength: (a) minimal spot width $W$ , (b) corresponding optimal lens height, (c) corresponding focal depth and (d) corresponding Poynting power.