We demonstrate three ultra-compact integrated-photonics devices, which are designed via a machine-learning algorithm coupled with finite-difference time-domain (FDTD) modeling. By digitizing the design domain into “binary pixels,” these digital metamaterials are readily manufacturable using traditional semiconductor foundry processes. By showing various devices (beam-splitters and waveguide bends), we showcase our approach's generality. With an area footprint smaller than λ02, our designs are amongst the smallest reported to-date. Our method combines machine learning with digital metamaterials to enable ultra-compact, manufacturable devices, which could power a new “Photonics Moore's Law.”
© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
Silicon photonics has witnessed major breakthroughs in recent years . A critical enabler for its unprecedented success can be attributed to device designs that demonstrated favorable characteristics like high sensitivity, low-loss, and high index-contrast [1–5]. CMOS-compatible integrated-photonic systems have also contributed to this progress [1,2], and have led to the miniaturization of optical circuits. In contrast to integrated electronics, scalable design methods for ultra-dense integrated photonics are still missing [6,7].
Conventional nanophotonic design is often based upon theoretical intuition [8–11]. This approach has two drawbacks. First, its application is constrained to known structures and well modeled light-matter interactions . Second, device designs based on such methods might not satisfy practical performance requirements like compactness, efficiency, bandwidth, and low-loss. In order to solve these problems, a variety of numerical approaches have been developed. These include inverse-design , evolutionary algorithms , objective-first algorithms [15–18], topology optimization , and direct-binary-search algorithms [20–26]. The latter approach utilized digital metamaterials (DMMs), where the design domain is discretized in sub-units (pixels) based upon the fabrication capabilities, which allows for robust, manufacturable devices. Machine learning (ML) has recently been applied to this design problem [27–32]. ML has proven to be a powerful design approach primarily due to (a) easy hardware parallelization, (b) relative independence from the choice of initial solutions, and (c) potential for generating manufacturable designs.
Recently, we applied an ML method, binary-Additive Reinforcement Learning Algorithm (b-ARLA), to design one of the smallest T-junction splitters reported to date . To showcase the general nature of this design approach, here we extend b-ARLA to design three fundamental DMM devices: a 50:50 Y-junction beam-splitter, a 90˚ waveguide bend, and a 180˚ waveguide bend, as shown in Fig. 1.
The other contributions of this work are careful analysis of the impact on device performance of (i) the number of guesses during training, that is the trade-off between performance and computational cost; and (ii) the dimension of the digitized pixels, which define the number of degrees of freedom. We acknowledge that the devices reported here show among the smallest footprints, but not necessarily the best performance (for instance, the insertion loss is higher than that of other devices proposed in the literature). However, these devices are presented as examples of our design approach, and further improvements in the algorithm and loss function formulations could mitigate these deficiencies.
2. Design and optimization
The binary-Additive Reinforcement Learning Algorithm combines both the “additive updates” feature of a perceptron algorithm as well as the “reward for state idea” associated with reinforcement learning [5,33]. As previously described elsewhere [5,27], the algorithm essentially consists of two stages: training and inference. The training stage initiates with the creation of a set of random designs (guesses). The figure of merit for these designs are used to predict an optimized device design in the inference stage. Details of the algorithm have been described previously [5,27]. The devices, as well as the input and output waveguides, are designed on the traditional Silicon-on-Insulator (SOI) platform with a device (Si) height of 0.22 µm. In the examples reported here, we considered square domains (1.2 µm × 1.2 µm in size) comprised of N × N pixels for designing the devices. We also considered N = 12, and hence, the size of each individual pixel in these devices is 0.1 µm × 0.1 µm. Each pixel is randomly assigned to be either air (refractive index = 1) or Silicon (refractive index = 3.46). The input and output Silicon waveguides are 1 µm long and 0.44 µm wide. The thickness of the Silica substrate is 2 µm. Detailed schematic illustrations of the devices are presented in Fig. 1. We would like to point out that the dimensions of the individual pixels that have been employed here can be readily fabricated using electron beam lithography, projection photolithography, which is common in the semiconductor industry, as well as focused-ion-beam lithography. We have demonstrated this in the past [20–26]. Following the discretization of the design space, a 2.5D varFDTD (variational FDTD, Lumerical) method  calculated the steady-state electromagnetic fields at an operating wavelength, λ0 = 1.55 µm. TE polarization (with non-zero components of Ex, Ey, and Hz) was assumed. Perfectly matched layers (PML) surrounded the boundaries of the computational domain. During the training as well as the inference stages, Lumerical MODE solutions was employed to extract the steady-state response of the structures with 2.5D varFDTD. An additional post-validation step after the inference stage was done to crosscheck the obtained results using full 3D FDTD with Lumerical FDTD solutions. The insertion loss, defined as the ratio (in dB) of power transmitted through the device to the incident power, was computed, which in our case serves as the figure of merit for optimization of the devices.
First, we analyzed the predicted insertion loss for the Y-junction beam-splitter as a function of the number of guesses employed during the training phase (Fig. 2(a)). It can be seen that the final prediction of insertion loss decreases as the number of random designs employed in the training stage is increased. Moreover, from the slope of the curve, it can also be seen that the improvement in the solution approaches asymptotic behavior. That is, from a certain point, an increase in computational cost would not significantly pay off in benefits. From this perspective, we chose 10,000 guesses as a reasonable trade-off between computational cost and predicted device performance.
Next, we analyzed the impact of the number of pixels on the predicted insertion loss for the Y-junction beam-splitter. For this purpose, we ran the algorithm discretizing the domain geometry in 4 × 4 (N = 4), 6 × 6 (N = 6), and 12 × 12 (N = 12) pixels. As expected, the predicted insertion loss decreases with an increase in the number of pixels (Fig. 2(b)). In general, by increasing the number of degrees of freedom, either by decreasing pixel size (keeping constant the device footprint) or increasing the device footprint (keeping constant pixel size), it is possible to reduce insertion loss.
Finally, it is to be noted that the advantage of this technique lies in its ability to parallelly calculate the figures of merit from a large number of starting (random) pixel layouts. In the future, we can take advantage of high-performance computing centers and multiple processors to design devices faster than serially-advancing optimization algorithms such as direct binary search.
3. Results and discussion
Figure 2 (c-e) shows the insertion loss during design for the three devices. The value for each guess is shown as red dots, while that of the final device is in green (2D var FDTD) and blue (3D FDTD). The achieved insertion losses are 0.92 dB, 1.07 dB, and 1.73 dB for the Y-junction beam-splitter, the 90˚ bend, and the 180˚ bend, respectively. The symmetry of the beam-splitter allowed for fewer guesses and better performance (see Fig. 1(d)).
The steady-state-field distribution of the Y-junction beam-splitter is shown in Fig. 3(a). Although the device was designed for one wavelength at λ0 = 1.55 µm, its operating bandwidth is quite broad (1.54 µm to 1.56 µm), as depicted in Fig. 3(d). The field-distribution confirms efficient splitting of the input mode and strong modal match at the output waveguide, resulting in good transmission efficiency. Figures 3(b) and 3(c) show the steady-state-field distributions for the 90˚ and 180˚ bends, respectively. Similar operating bandwidths, as in the beam-splitter, are also observed (see Figs. 3(e) and 3(f)).
We note that larger bend devices (2 orders of magnitude larger than our devices) with somewhat better performance have been reported elsewhere . Furthermore, the bend devices reported here are 60% smaller than the smallest bend device reported before  and, e.g., for the 180˚ bend provide for a remarkably small bend radius of just ∼λ0/10 (the input and output waveguides are spaced by 0.32 µm, which corresponds to an effective bend radius of 0.16 µm ∼ λ0/10).
We proposed a general design framework for ultra-compact digital metamaterial devices through the employment of a machine-learning algorithm, b-ARLA. This approach is general and can be applied to both passive and active devices. We presented designs of some of the smallest in-class devices: beam-splitters and waveguide bends reported so far with a footprint of only 1.2 µm × 1.2 µm thus < λ02 along with careful and detailed analyses of the performances of both the design algorithm as well as the designed devices. The possibility of designing and integrating such ultra-compact and efficient nanophotonic structures will allow to increase the density of on-chip photonic components dramatically and therefore enable more complex photonic integrated circuits, thereby enabling a new “Photonics Moore's Law.”
National Science Foundation (ECCS 1936729, MRI 1828480).
The authors declare no conflicts of interest.
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