Heterogeneous integration of III-V semiconductor materials on a silicon-on-insulator (SOI) platform has recently emerged as one of the most promising methods for the fabrication of active photonic devices in silicon photonics. For this integration, it is essential to have a reliable and robust bonding procedure, which also provides a uniform and ultra-thin bonding layer for an effective optical coupling between III-V active layers and SOI waveguides. A new process for bonding of III-V dies to processed silicon-on-insulator waveguide circuits using divinylsiloxane-bis-benzocyclobutene (DVS-BCB) was developed using a commercial wafer bonder. This “cold bonding” method significantly simplifies the bonding preparation for machine-based bonding both for die and wafer-scale bonding. High-quality bonding, with ultra-thin bonding layers (<50 nm) is demonstrated, which is suitable for the fabrication of heterogeneously integrated photonic devices, specifically hybrid III-V/Si lasers.
©2012 Optical Society of America
SOI is an emerging platform for photonic integrated circuits; it offers the potential of realizing low-cost and compact optical circuits. Moreover, standard complementary metal oxide semiconductor (CMOS) processing infrastructure can be used to process these optical components . This allows high-yield fabrication and a reduction of the component cost through economies of scale. However, the fabrication of efficient light sources in silicon photonics is challenging due to silicon’s indirect bandgap. Because of this indirect bandgap, the probability for an excited electron-hole pair to recombine and emit a photon is strongly reduced as a result of the much higher non-radiative recombination rate. Advances are being made to achieve light emission from silicon, either by modifying the silicon on a nanoscale or by exploiting its nonlinear optical properties . However, those devices are not good enough for use in high-performance sensing and communication systems. In order to create photonic integrated circuits comprising both opto-electronic and passive optical components, the heterogeneous integration of passive silicon-on-insulator waveguide circuits and active InP/InGaAsP components has been proposed [3,4], for applications in the telecommunication wavelength range.
There are three main routes to the integration of III-V material on top of SOI, namely flip-chip integration , hetero-epitaxial growth , and bonding technology [3,4,7,8]. In the first approach, individual laser diode dies are flip-chipped on and coupled to an SOI waveguide circuit. While flip-chip integration is the most rugged technology, individual dies need to be aligned with sub-micrometer precision and placed on the surface. Also, the integration density is limited by the pitch and size of the solder bumps. Recently, edge-emitting laser diodes coupled to waveguide circuits were demonstrated using pick and place assembly to position them on the substrate [9,10]. Hetero-epitaxial growth of InP/InGaAsP, the material system of interest for telecommunication wavelength applications, is hampered by the large lattice mismatch of 8% between the III-V material and the silicon host substrate. Semiconductor wafer bonding on the other hand allows the integration of high-quality III-V epitaxial layers on top of the silicon platform by transferring the III-V layer stack from its original growth substrate to the SOI wafer. Full wafer bonding, multiple die-to-wafer bonding or single die bonding can be envisaged, depending on the application. In all cases, an unprocessed III-V semiconductor epitaxial layer stack is transferred, which reduces the time required to complete the integration process compared to a flip-chip process, as no stringent alignment accuracy is needed, because of the absence of structures on the III-V dies or wafers. After removal of the growth substrate, the optoelectronic components can be fabricated in the bonded epitaxial layer.
While there are various methods to transfer an InP/InGaAsP epitaxial layer structure onto an SOI waveguide wafer (molecular bonding, adhesive bonding, anodic bonding, metallic bonding), adhesive bonding offers some significant advantages over the other bonding methods. The relaxed requirements on surface cleanliness, contamination and surface roughness combined with the planarizing action of the adhesive spin coating process, offer a significant reduction in surface preparation. Moreover, the integration process is a low-temperature process, reducing the stress in the bonded stack due to the difference in thermal expansion coefficients between silicon and III-V semiconductor.
Both thermoplastic polymers, like SU-8  and thermosetting polymers, such as spin-on glass , polyimide and DVS-BCB (divinylsiloxane-bis-benzocyclobutene), are used as adhesives . DVS-BCB is a good candidate for hybrid bonding because of its excellent physical properties such as low dielectric constant, low moisture absorption, low curing temperature, high degree of planarization, low level of ionic contaminants, high optical clarity, good thermal stability, excellent chemical resistance, and good compatibility with various metallization systems [13,14]. Early work by Frank Niklaus investigated the influence of different bonding parameters on void formation in low-temperature full-wafer adhesive bonding using DVS-BCB as the intermediate bonding material, both on unpatterned and patterned substrates, using micrometer thick bonding layers . Subsequently, die-to-wafer and die-to-die bonding based on both manual and machine-based DVS-BCB bonding were reported by our group [8,16]. The major challenge in the bonding process is the fact that deep submicrometer layer thicknesses are required to achieve optical coupling from the top active III-V layer into the bottom SOI waveguides. This optical coupling can be achieved in various ways, including the use of hybrid modes [8,17] and the use of a double taper structure, using taper-based mode transformers both in the III-V and silicon waveguides [7,18–20]. Both approaches can be made tolerant to bonding layer thickness variations on the order of tens of nanometer.
In this paper, we describe a new adhesive wafer bonding process scheme that involves partial curing of the DVS-BCB prior to bonding and attaching the III-V substrate at room temperature prior to curing in a vacuum atmosphere. This “cold bonding” method significantly simplifies the bonding preparation for machine-based bonding, both for die and wafer-scale bonding. This approach shows high yield for ultra-thin bonding thicknesses below 50 nm, as well as a good uniformity of the DVS-BCB layer thickness after wafer bonding over the full wafer area. This process was applied to achieve ultra-thin DVS-BCB bonding layers for the fabrication of several photonic devices, such as III-V/SOI lasers [7,18–21].
2. DVS-BCB wafer bonding processes
The bonding process was developed for a wafer level epitaxial layer transfer; however, as will be shown later, it can also be applied to a multiple die-to-wafer bonding and a single-die bonding. A Suss MicroTec ELAN CB6L wafer bonder was used for bonding experiments. Commercial DVS-BCB solutions are limited in available spin-coated layer thicknesses down to 1μm (for Cyclotene® 3022-35 from Dow Chemical) . Since this work deals with bonding layer thicknesses that are an order of magnitude smaller, mesitylene is added to Cyclotene 3022-35 to reduce the spin-coated layer thickness substantially.
The processing procedure is schematically illustrated in Fig. 1 . The bonding process starts with the cleaning of the SOI substrate and the III-V dies. The SOI cleaning is performed by immersing the substrate for 15 minutes into a Standard Clean 1 (SC-1) solution, comprising aqueous ammonia (NH4OH), hydrogen peroxide (H2O2) and deionized (DI) water in volume ratios of 1:1:5, respectively, which is heated to 70 °C. After this, the DVS-BCB:mesitylene solution is spin-coated onto the SOI substrate. The SOI substrate is then baked for 10 min at 150 °C, to let mesitylene evaporate, after which the substrate is slowly cooled down to room temperature. Finally, the SOI is mounted on a carrier wafer made of Pyrex glass (1200 um thick, 100 mm diameter). Meanwhile, prior to bonding, an InP/InGaAs sacrificial layer pair on the III-V wafer/die is removed by selective wet etching using HCl:H2O and H2SO4:H2O2:H2O solutions, in volume ratios of 4:1 and 1:1:18 respectively. This procedure removes particles and contaminants from the III-V die surface. The III-V die is then rinsed with DI water, dried and mounted on the SOI die. Since, in the presented method, the dies are contacted at room temperature, individual dies can easily be pick-and-placed onto the silicon target wafer. They can be aligned manually with an accuracy of 500µm without any extra tools or can be placed more accurately using a flip-chip machine. After that, the SOI substrate on its carrier wafer is mounted on the transport fixture and is loaded into the processing chamber of the wafer bonding tool. The chamber is pumped-down (target pressure 10−3 mbar) and heated to 150°C with a ramp of 15 °C/min for 10 min, while applying pressure on the III-V/SOI stack. The actual bonding pressure (the applied force per area of the III-V die) is kept in the range of 200 to 400 kPa. After keeping the pressure on the dies for 10 min at 150 °C, the temperature is increased up to 280 °C, with a ramp of 1.5 °C/min. Upon reaching 280 °C, the dies are kept at this temperature for 60 min in a nitrogen atmosphere. After the curing, the bonded samples are cooled down (at 6-10 °C/min) and unloaded from the processing chamber. The InP substrate of the III-V die is then removed by a selective wet etching using HCl, leaving a thin III-V film with the functional layers bonded to the SOI die, ready for further processing. An alternative method has been reported earlier by our group , in which adhesive die-to-wafer bonding was demonstrated in a commercial wafer bonder. In this method spacers are used to keep the die and substrate separate prior to loading the stack in the bonding tool. In this new method no carrier is required to load the top wafer/die into the machine and no vacuum or heating is required prior to contacting the wafers in the bonding chamber. This makes the process more straightforward. Moreover, with the previous recipe, it was not possible to perform multiple die-to-wafer bonding for dies with different thickness. Using this new method, we demonstrate that multiple-die bonding with different die thickness is feasible.
3. Bonding experiments
Several bonding experiments were performed to evaluate the bonding quality and the DVS-BCB thickness uniformity after wafer bonding. The experimental results are discussed in the following sections. Wafer-to-wafer, die-to-wafer and multiple die-to-wafer bonding are reported.
3.1. Wafer-to-wafer bonding
The bonding quality was first assessed by bonding 2 inch InP wafers to 4 inch Pyrex glass wafers (with a thermal expansion coefficient similar to that of silicon). In this way, the bonding interface can be inspected through the Pyrex substrate using a standard microscope with a polarization filter. The InP wafer was etched away after bonding using a selective wet etching solution (HCl) to measure the thickness and uniformity of the DVS-BCB bonding layer. The results of 5 wafer bonding experiments are summarized in Table 1 , showing a good uniformity over the wafer (the bonding layer thickness was measured in 18 points all over the wafer area using a profilometer) and a good reproducibility of the nominal bonding layer thickness, even when there is a variation in applied pressure. A DVS-BCB:mesitylene dilution of 1:8 (v/v) was used in the experiment; spin coated at 3000 rpm, this results in a 35 nm DVS-BCB bonding layer thickness. Even with such thin bonding layers, the bonded area is above 99%. The non-bonded parts are due to the presence of particles at the bonding interface. This is related to the fact that bulk InP wafers were used without a sacrificial InP/InGaAs layer pair to remove particle contamination from the surface.
Additional bonding experiments were carried out, transferring a 300 nm thick InP membrane to a Pyrex handle wafer, to a silicon wafer with a 1.5 μm-thick layer of SiOx on top and to a silicon-on-insulator wafer with a 220 nm high silicon pattern. For this we used InP-substrates with a 300 nm InP layer grown onto a 300 nm InGaAs etch stop layer, provided by III-V lab, France. The resulting InP membrane after transfer can be used as an optical waveguide layer for ultra-compact III-V membrane photonic integrated circuits [23,24]. A nice and uniform 2 inch diameter film appeared after removing the substrate (Figs. 2(a) -2(c)). To measure the DVS-BCB thickness and uniformity, 4 cross-sections were made through the bonded stack 2 cm away from each other, using a focused ion beam (FIB) tool, and inspected using scanning electron microscopy (SEM). A uniform DVS-BCB thickness for different points distributed over the bonded surface is obtained, with an average bonding layer thickness of 29 nm, varying by ±3 nm over the cross-sections.
For cost-effective utilization of the expensive III-V semiconductor material, often a full-wafer bonding is not the preferred approach. Therefore, in the subsequent sections we will elaborate on quarter-wafer bonding, multiple die-to-wafer bonding and single die-to-wafer bonding. We will start off with the results obtained on Pyrex glass wafers, after which the application of the developed process to bond onto patterned and planarized SOI waveguide circuit wafers is demonstrated.
3.2. Quarter-to-wafer bonding
To show the reliability of the presented method even for a quarter wafer bonding, 5 bonding experiments were performed by bonding a quarter of an InP wafer to a Pyrex glass wafer. A similar analysis of the bonding quality and thickness uniformity was performed, which is summarized in Table 2 . These results illustrate that the uniformity and reproducibility of the process is similar to that of the full wafer bonding. The bonding interface is shown in Fig. 3(a) , showing a large bonded surface yield. The interference fringes at the rounded edge of the quarter wafer are due to the tapering of the InP wafer near its edges.
While the bonding recipe was originally developed for ultra-thin DVS-BCB bonding layers, some applications require thicker bonding layers, i.e. several hundreds of nm to micrometers thick. In this case, after choosing the right DVS-BCB dilution, the same method was applied for bonding. To achieve a good bonding uniformity, the DVS-BCB was partially cured at 180°C prior to bonding (instead of at 150°C). Figures 3(b) and 3(c) show two bonding interfaces with partial curing at 150°C and 180°C for 15 minutes respectively. The DVS-BCB thickness in the first bonding has an average thickness of 130 nm and a variation of around 70 nm, while the second pair has average thickness of 113 nm and variation less than 10 nm, clearly illustrating the need to partially cure at higher temperatures for uniform bonding layer thicknesses. The same procedure was applied on two other quarters with less diluted DVS-BCB to achieve a bonding layer thickness around 1000 nm. The results, illustrated in Figs. 3(d)-3(e) show an average thickness around 1050 nm and variation around 250 nm for the first pair and an average thickness of 1050 nm and around 30 nm variation for the second pair. In this case, a 180°C soft-bake was applied for 15 min and 30 min for both samples respectively. This illustrates again that a well-adapted pre-curing time and temperature is required to obtain a uniform bonding interface.
While the bonding process was developed on Pyrex glass wafers for ease of bonding interface assessment, III-V epitaxial layer transfer in a photonic integrated circuit context is mostly geared towards the integration of the III-V material on a SOI waveguide circuit, as discussed in the introduction, for the realization of hybrid III-V/silicon photonic integrated circuits. For this, the III-V epitaxial layer stack needs to be transferred to the silicon waveguide circuit.
Given the relatively high topography (400 nm) of the silicon waveguide circuit, the waveguide trenches were filled with oxide, in order to obtain a planarized waveguide circuit, to which the III-V layer can be transferred. The DVS-BCB was spin-coated on the III-V side, to avoid the presence of DVS-BCB on the parts of the SOI wafer not covered with III-V. The quasi-planar SOI waveguide circuits were fabricated in a CMOS pilot line in CEA-LETI on 8 inch wafers . The original SOI wafer had 100-150 nm planarized SiOx on top of the waveguides. However, to achieve an ultra-thin separation between the III-V layer and the silicon waveguide, needed for most III-V/SOI laser structures, the SiOx was etched back using a HF-based wet etching process on a die-scale. The results are shown in Fig. 4 , showing a well transferred epitaxial layer stack, with bonding layer thicknesses, uniformity and surface yield comparable to those achieved on a Pyrex wafer. Again, the tapering of the InP wafers near the edge of the wafer compromises the bonding quality there, which cannot be avoided.
3.3. Multiple die-to-wafer bonding
Commercial silicon and CMOS production is carried out on wafer diameters of 200 mm and above, while III-V substrates used in photonics applications have typical diameters of less than 100 mm, indicating that wafer-to-wafer bonding will often not be the preferred approach. Moreover, bonding of large III-V areas would result in a waste of material in chip areas were the transferred material is not needed. Therefore, a cost-effective approach in heterogeneous integration requires III-V material to be bonded in small areas of the SOI photonic wafer. We focus on a multiple die-to-wafer bonding process where III-V dies would be bonded to a SOI die or a full SOI wafer. Since the presented method uses contacting of the dies at room temperature, individual dies can easily be pick-and-placed onto a silicon target wafer. They can be aligned with an accuracy of 500μm without any extra tools or can be placed more accurately using a flip-chip machine.
In order to demonstrate multiple die-to-wafer bonding, 0.3 cm2 III-V dies were transferred to a quasi-planarized SOI die (fabricated by CEA-LETI), using the ultra-thin bonding recipe. The results are shown in Figs. 5(a) -5(d). Results show a two-die and four-die bonding with a bonding layer thickness less than 50 nm. The III-V dies in this case were still relatively large (0.5 cm2). In order to demonstrate the true potential of die-to-wafer bonding, dies of 1.3 mm by 4 mm were transferred (which is a typical III-V die space one would need to make a 32 channel laser array), using the ultra-thin bonding recipe. This is shown in Figs. 5(e)-5(f). A cross-section of the bonding interface illustrating the ultra-thin bonding layer thickness is shown in Fig. 5(g). Figure 5(h) shows six III-V dies bonded to a 50 mm silicon wafer with 1.5μm-thick layer of SiOx on top. The InP films were afterwards etched away using a wet etching solution to measure the thickness and uniformity of the DVS-BCB bonding layer. A DVS-BCB: mesitylene dilution of 1:8 (v/v) was used in the experiment, spin coated at 2500 rpm, resulting in an average bonding layer thickness of 50 nm, varying by ±5 nm over all six dies. This shows the good uniformity over the whole bonding area and a high reproducibility of the nominal bonding layer thickness from die to die.
While in the previous experiments nominally identical III-V dies were used, in particular situations there is a need for bonding different types of III-V dies on a single SOI die or wafer (e.g. a die containing laser epitaxy and a die containing photodetector epitaxy). This typically results in dies of different height and size to be bonded, which is difficult to achieve using the classical bonding recipe. Here we show that by applying the new bonding recipe, in combination with a graphite foil between the dies and the bonding head, four-die bonding using two different epitaxial layer stacks (with about 50 μm difference in substrate thickness) can be achieved. The graphite foil is used to compensate for these thickness variations in order to distribute the pressure evenly over all dies during the bonding, as is illustrated in Fig. 6 . Recently, heterogeneously integrated III-V/silicon lasers and photodetectors, using this 'cold bonding' method have been demonstrated [7,19–21]. The results illustrate the robustness and solid bonding strength during the III-V opto-electronic component fabrication and we believe it can provide a promising alternative to a direct bonding technique for the fabrication of integrated photonic components.
3.4. Characterization of the bonded film
Beside the characterization of the bonding quality, the quality of the transferred epitaxial film also needs to be assessed. This is performed in this work by evaluating the photoluminescence and X-ray diffraction rocking curves of the epitaxial film before and after the bonding. For this study, a quasi-planarized SOI die with 400 nm silicon height was used and a III–V epitaxial wafer consisting of an InGaAsP-based MQW laser structure was grown on a semi-insulating InP substrate by metallorganic vapor phase epitaxy (MOVPE).
The structure consists of a 200 nm n-type InP layer, a 6 quantum well In0.81Ga0.19As0.24P0.76 (8 nm) active region with In0.76Ga0.24As0.53P0.47 (10 nm) barriers, sandwiched in between two 100 nm thick In0.76Ga0.24As0.53P0.47 separate confinement heterostructure layers followed by a 1.5 μm thick p-type InP layer and a 100nm thick In0.76Ga0.24As0.53P0.47 etch stop layer. Figure 7(a) shows the direct comparison of the measured rocking curves at the center of the as-grown and the bonded epitaxial layer stack. All MQW satellites can be probed at nearly identical positions with no peak broadening, indicating well-preserved crystalline structural integrity.
Photoluminescence (PL) characteristics of the as-grown and transferred epitaxial layers were also compared as a measure for epitaxial layer quality. Measurements were performed at 300 K using a 980 nm, 0.5 mW pump source and each sample was measured three times at different spots, both for the bonded sample (after InP substrate removal) and for the reference as-grown sample. Figure 7(b) shows the photoluminescence spectra for both cases. Compared to the as-grown epilayer, the well-preserved photoluminescence intensity, peak emission wavelength and full width at half maximum (52 nm after bonding and 48 nm before bonding) indicates that the bonding process does not deteriorate the optical performance of the transferred epitaxial layer stack. The different peak intensities in PL measurements is due to the different substrate for the bonded and non-bonded samples. Bonding strength measurements have not been performed in this work; however, in earlier work it has been reported , in which shear stress tests were performed on bonded samples. These measurements indicate that there is no significant impact of the DVS-BCB thickness on the maximum shear stress values, which are around 2 MPa, which suggests a high bonding strength.
In this paper a new method for the integration of InP-based semiconductor epitaxy onto silicon substrates and silicon photonic integrated circuits is presented. The “cold bonding” method significantly simplifies the preparation process for machine-based bonding in a wafer-to-wafer, die-to-wafer and multiple die-to-wafer adhesive bonding procedure. The demonstrated DVS-BCB bonding layer thickness is very uniform and ultra-thin DVS-BCB bonding layers (<50 nm) can be achieved. Additionally, we developed the process for simultaneous bonding of multiple III-V dies with different thicknesses, suitable for the heterogeneous integration of different types of III-V components on a SOI photonic circuit. While this process was originally developed for InP-based compounds, the bonding of other III-V semiconductors and other epitaxial materials in general can be envisioned.
This work was supported by a grant from the European Commission Seventh Framework Programme (FP7/2007-2013) under grant agreement no. 224312 HELIOS, and by the FP7-ERC-MIRACLE project. The authors thank Guang-Hua Duan and Francois Lelarge (III-V lab, Paris) for delivering the III-V epitaxial material used in developing this process and also Jean-Marc Fedeli and Sonia Messaoudene (CEA-LETI) for SOI fabrication. Liesbet Van Landschoot from the Photonics Research Group at Ghent University made SEM images, while Steven Verstuyft, from the same group, provided technical assistance in the cleanroom work.
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