Fabrication and chemical lift-off of sub-micron scale III-nitride LED structures

1. Introduction

Flexible, transparent, near-eye, and high density display technologies for next generation mobile and wearable electronics will require efficient micro- and nanoscale self-emissive pixels, i.e., pixels made up of devices that directly emit light rather than color convert a white light emitting back-plane. With the development of III-nitride microscale light emitting diodes (LEDs), or microLEDs [1–3], GaN/InGaN devices have shown promise in these applications due to their high efficiency and luminance. Currently, organic LEDs (OLEDs) are being used or are envisioned for these proposed display technologies due to their low-cost and scalable manufacturing. However, OLEDs suffer from low efficiency and lifetimes [4,5]. Higher efficiency III-nitride LEDs could potentially solve these issues, but scalable fabrication of micron and sub-micron scale GaN/InGaN devices that emit at different wavelengths, and implementing such devices onto display platforms, is challenging. Substrate thinning and/or separating individual devices from their rigid growth substrates for subsequent high-throughput printing onto alternate substrates is also required for flexible and transparent display applications.

High density and transparent displays require small pixels (<100 µm for TVs, <50 µm for watches and smartphones, and <5 µm for augmented reality/virtual reality (AR/VR)) [6] for both visual and cost constraints. For instance, large devices are not compatible with near-eye displays and more costly compared to small devices. Additionally, sub-micron patterning can theoretically increase the internal quantum efficiency (IQE) of the device by reducing strain and built-in piezoelectric fields, thus reducing quantum confined Stark effects (QCSE) [7]. Scalable nanopatterning is thus needed to fabricate sub-micron scale LEDs. Colloidal lithography, combined with plasma etching, can be a wafer-scale, cost-effective, and reproducible nanopatterning technique [8,9]. This approach has been implemented to roughen the outcoupling surfaces of InGaN/GaN LEDs [10] to enhance light extraction and to fabricate nanorod light emitters, where an individual LED is composed of multiple nanorods [11–13]. Researchers have also used colloidal lithography to produce individual, optically-active nanoscale devices [14], and others have suspended them in solution, using dielectrophoresis to align them onto metal electrodes for electroluminescence [15,16]. In the latter case, devices were physically removed from the sapphire growth substrate using a diamond blade, a process step that is not necessarily scalable.

Separation of GaN devices from their growth substrates has also been demonstrated using laser lift-off [17–20], selective etching of the growth substrate itself (GaN on Si) [21], and selective etching of a sacrificial material (BN [22,23], CrN [24], ZnO [25–27], Si doped n-GaN [28], or InGaN [29]) placed between the growth substrate and the device. Of these methods, selective etching of an InGaN sacrificial layer is easy, given that conventional LEDs already employ InGaN in multi-quantum well (MQW) light emitting layers. Hwang et al. has also demonstrated chemical lift-off of LEDs grown on sapphire using photoelectrochemical (PEC) etching [30,31] of a sacrificial InGaN/GaN MQW [32].

In this work, we developed a fabrication method to produce submicron scale c-plane LEDs (diameter = 500 nm), or nanoscale LEDs (nanoLEDs), that combines colloidal lithography with selective PEC undercut etching to separate nanoLEDs from a sapphire growth substrate. PEC etching conditions were optimized for minimal undercut surface roughness to mitigate damage to the active light emitting MQWs. By combining these methods, hexagonally close-packed (HCP) arrays of GaN/InGaN nanoLEDs were fabricated and released into solution for potential high-throughput solution-based assembly. Post-processing photoluminescence (PL) measurements were done to show that nanofabricated devices were optically active and X-ray diffraction (XRD) measurements suggest that strain relaxation occurs upon nanopatterning. Such devices address the aforementioned manufacturing challenges because they satisfy the small pixel dimension requirement, can be separated from their rigid growth substrates, and can potentially be assembled onto display platforms, all using low-cost and potentially scalable methods.

2. Experiment

GaN/InGaN LED device stacks, which consisted of a 2 µm n-GaN buffer, six-period sacrificial MQWs (2 nm In_0.11Ga_0.89N well + 13 nm GaN barrier, T_growth = 873 °C), 1.6 μm GaN spacer, 20-period superlattice (2 nm In_0.02Ga_0.98N + 2 nm GaN, T_growth = 940 °C), six period active MQWs (2 nm In_0.14Ga_0.86N + 17 nm GaN barrier, T_growth = 865 °C), and a 170 nm thick GaN cap, were epitaxially grown by metal organic chemical vapor deposition (MOCVD) on sapphire. All compositions are nominal and estimated from the growth recipe, and believed to be within ±1-2% In. A schematic of the device fabrication procedure and SEM micrographs at various process steps are presented in Fig. 1. Colloidal lithography, described in detail in previous work [33–36], was used to define HCP arrays of nanoLEDs. Briefly, silica colloids (d = 960 nm) were functionalized with allyltrimethoxysilane (ATMS, Sigma-Aldrich, >98%) in ethanol (pH = 5.5, acetic acid, 10% H₂O, and 10-20 mM ATMS), washed in ethanol after functionalization, cured in a vacuum oven (65°C, 12 hours), and redispersed in 3:1 chloroform:ethanol. The functionalized colloids (i.e., the lithographic mask) were then suspended on a water subphase and dip-coated onto the GaN/InGaN device stack in a Langmuir-Blodgett (LB) trough (KSV Nima) at constant surface pressure; the end result was an HCP monolayer of silica colloids on the device substrate. LB deposition was performed on 1 × 1 cm² pieces as a proof-of-concept, but the technique can be scaled to full 4-inch wafers [37].

 

Fig. 1. Process schematic for c-plane nanoLED fabrication and lift-off using colloidal lithography for patterning and PEC etching of a sacrificial InGaN MQW for release.

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After LB deposition, the nanosphere silica mask particles were size reduced using an isotropic inductively coupled plasma reactive ion etch (ICP-RIE) with CF₄/Ar (40:10 sccm), 900 W RF power, no substrate bias, and a pressure of 30 mTorr. HCP conical frusta were then etched into the device stack using a Cl₂/N₂ (37.5:12.5 sccm) ICP-RIE at 500 W RF power (“etch #1”), 200 W bias power, and a pressure of 9 mTorr. The pattern transfer etch time was adjusted to fully poke through the p-GaN and active MQW layers, but stop within the n-GaN buffer layer such that the sacrificial MQW was not exposed (approximately 1.5 µm deep). The SiO₂ colloids were subsequently stripped in HF. A heated KOH etch (70 °C for 3 minutes) was performed after plasma etching to strip plasma damaged material [38], leaving behind cylindrical nanorod structures. An SiO₂ PEC etch mask was then sputter deposited while rotating the sample to achieve a conformal layer, where the SiO₂ layer was thicker near the top and thinner near the bottom of the nanorods due to the close-packed geometry. The SiO₂ layer was used to cover the surface of the nanoLEDs to protect the active MQWs from further chemical etching in later PEC processing. The same Cl₂/N₂ plasma etch described previously was repeated (“etch #2”) to etch through the remaining n-GaN buffer and the sacrificial MQW without etching through the SiO₂ mask at the top of the nanorods. Finally, a PEC contact was deposited in a grid pattern (20 µm wide lines, 500 µm spacing) via photolithography (nLOF-2020 resist), e-beam metal deposition of Ti/Au (20/300 nm), and metal lift-off. PEC etching was done in 0.02 M KOH at room temperature (25 °C) while stirring under an LED array (λ_max = 405 nm, FWHM ∼15 nm, ∼40 mW/cm²) to chemically etch the sacrificial MQW and release the nanoLEDs into solution. The nanoLEDs were then washed in water 3 times using centrifugation and dried in a vacuum oven. After drying, the SiO₂ mask was stripped with an HF vapor etch, which is necessary for electrical contact (if desired, but not presented here).

PL measurements were done at 292K and 14K using a 405 nm continuous-wave InGaN laser to optically excite the MQWs. The pump source was incident at ∼45° and the PL was measured normal to the sample surface with a high numerical aperture collector and 405 nm band-stop filter coupled to a UV-vis spectrometer (Ocean Optics USB 2000+) via fiber; pump power was ∼10 mW. The samples were cooled in a home-built closed-cycle He refrigerator based on a CT-8 coldhead (CTI Cryogenics). XRD measurements (ω-2θ scans) were performed on the as-grown and post-KOH wet etched devices using monochromatic CuKα radiation (λ = 1.5405 Å) on a Panalytical MRD Pro with a 3D Pixcel detector.

3. Results and Discussion

PEC etching was used to remove the buried sacrificial InGaN/GaN MQW layer to release individual nanoLEDs from their sapphire growth substrate. However, PEC etching at the exposed N-face of c-plane GaN results in large hexagonal pyramid features due to faceting, with length scales on the order of the size of the nanoLEDs themselves. This roughness is problematic because a significant portion of the nanoLED material volume may be etched out, rendering the device inactive if the active MQW is damaged. To solve this problem, the PEC etch process was optimized for minimal interfacial roughness by varying the concentration (0.02 M – 0.5 M) and temperature (3-65 °C) of the KOH etchant. Two test structures were fabricated on sapphire substrates to study the interfacial roughness as a result of PEC undercut etching; the test stack consisted of 1 µm n-GaN, a sacrificial InGaN MQW, and an n-GaN buffer layer. The first test structure was fabricated using colloidal lithography to produce nanorods (diameter ∼1 µm), and the second test structure was fabricated using traditional photolithography to produce large mesas (diameter ∼80 µm).

SEM images (Figs. 2(a,e)) of submicron test structures after 30 minutes of PEC etching show that the roughness dramatically decreased at low KOH concentration (0.02 M). Figures 2(b,f) show corresponding optical images of the large mesa test structures after 3 hours of PEC etching, where gray regions are unetched and bright regions are etched. Based on these images, low concentration PEC etching also resulted in higher lateral etch rate uniformity. Two anchor points held the mesas onto the growth substrate such that mesas would not float off into solution after PEC etching the entire sacrificial MQW layer. A polydimethylsiloxane (PDMS) stamp was used to pick up the undercut mesas from the substrate, where anchors were snapped upon pick up, revealing the bottom interface of the mesas. The bottom interfaces of the mesas were then analyzed using SEM and AFM, as shown in Figs. 2(c,d,g,h).

 

Fig. 2. (a,e) SEM images of n-GaN/InGaN MQW/n-GaN nanorod test structures after 30 min of PEC undercut etching of the InGaN MQW using 0.25 M and 0.02 M KOH, respectively. (b,f) Bright-field optical images of microscale n-GaN/InGaN MQW/n-GaN mesa test structures after 3 hours of PEC etching using 0.25 M and 0.02 M KOH. White and grey areas correspond to fully undercut and unetched regions, respectively. (c,g) SEM images of the bottom-side of mesas after PEC etching using 0.25 M and 0.02 M KOH. Mesas were removed from the sapphire substrate using a PDMS stamp after full undercut of the entire sacrificial InGaN MQW. (d,h) AFM topography images of the mesa bottom-side after PEC etching using 0.25 M and 0.02 M KOH show RMS roughness of ∼100 nm and ∼30 nm, respectively.

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The SEM images of the bottom interface of the mesas show roughness reduction when performing PEC etching at low concentration, even for long etch times and large areas. AFM results confirm a substantial reduction in interfacial roughness with a root mean square of ∼100 nm and ∼30 nm for the 0.25 M and 0.02 M KOH etched samples, respectively. Lower temperatures (results not shown) resulted in less overall roughness, but this effect was minor compared to KOH concentration. The reduced roughness and increased uniformity of the lateral etch at low [KOH] is thought to be related to a reduction in the overall etch rate and thus the faceting rate. We hypothesize that rapid faceting in the high [KOH] case leads to (large) variations in etchant and etch product (e.g., InO₃^3- and GaO₃^3- [39])) concentrations; all these species must diffuse out of the < 60 nm thick sacrificial MQW channel, and moreover, the inability to effectively remove etch products may even inhibit local etching, hence the lower lateral etch uniformity in the high concentration case.

Optimized PEC etch conditions were used to undercut nanoLEDs, with diameters of approximately 500 nm, after fabrication. Figure 3(a) shows an SEM image of a group of devices after fabrication, undercut, wash, and removal of the residual SiO₂. Devices were drop-cast onto an Si substrate and dried before SEM imaging. Individual nanoLEDs had a “rivet” or “screw-like” shape because of the two-step pattern transfer process and intermediate KOH etch. The initial plasma etch to define the nanorods was carried out with a stop ∼1 μm into the n-GaN layer above the sacrificial wells, so as to not expose the sacrificial layer; the rods were then KOH etched to remove plasma damage, making their diameters smaller, and then covered with the SiO₂ PEC etch mask. The second plasma step (etch #2) was then carried out to etch down through the rest of the n-GaN layer and through the sacrificial wells to expose their sidewalls, thus making the head of the “rivet” structure. Ultimately, when the rods were HF vapor etched to remove the SiO₂, the full rivet structure was formed, with part of the n-GaN layer having a larger diameter than the rest of the rod containing the active wells (which necessarily had a smaller diameter due to the KOH step).

 

Fig. 3. (a) SEM image of c-plane nanoLEDs with active InGaN/GaN MQW after their removal from the growth substrate via PEC etching of the sacrificial MQW + washing + stripping the SiO₂ mask + drying. (b) Normalized PL emission at 292 K of the as-grown, planar device stack (flat, red) and nanoLEDs after liftoff and deposition on Si (nanoLEDs, green), as shown in (a). (c) Room (292 K) and low (14 K) temperature PL emission [counts/ms] of the as-grown, planar device stack (red, purple) and nanoLEDs after liftoff and deposition on Si (green, blue). The 405 nm pump line, sacrificial well, and active well emissions are denoted P, SW, and AW, respectively. An ∼10 nm blueshift is seen for the nanoLEDs, likely resulting from strain relaxation due to nanopatterning.

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Normalized and absolute PL signals from the as-grown device stack and lifted-off nanoLEDs on Si, measured under the same pump conditions at 292K and 14K, are presented in Figs. 3(b)–3(c). Panel (b) shows strong emission from the active wells (AWs) at ∼468 nm and a smaller peak at ∼425 nm from the sacrificial wells (SWs) in the as-grown unpatterned (flat) sample (red), the latter being lower due to pump light absorption in device layers above the SW. PL from the nanoLEDs after full lift-off processing is also shown in green, where the SW emission is absent, as it should be. The AW emission from the lifted nanoLEDs is clearly blue-shifted by ∼10 nm from the as-grown material. This effect is likely attributed to reduction of QCSE, where compressively strained material can relax laterally after nanopatterning, reducing piezoelectric fields in the MQW, which both blue-shifts the emission and potentially increases the IQE [38,40–42].

Direct comparison of IQE for the as-grown (flat) material vs. lifted nanoLEDs is not feasible due to differences in the amount of active material being excited, pump light recycling, and angular distribution of emission (i.e., due to a flat sample vs. a pile of nanoLEDs on Si (see Fig. 3(a)). However, one can use temperature-dependent PL (TDPL) to get a quick estimate [43] as IQE_TDPL = I(T)/I(Low T), where I(T) is the integrated emission intensity at temperature T. Using the AW emissions in Fig. 3(c) for the lifted nanoLEDs and as-grown (flat) device stack, IQE_TDPL (I_292K/I_14K) values were 29% and 50%, respectively. The former indicates that the lifted nanoLEDs were reasonably efficient, i.e., ∼60% of the as-grown, pristine (flat) material device stack, despite extensive processing. IQE_TDPL for the as-grown sample is also similar to previously reported values for InGaN/GaN LED structures at room temperature [43,44].

XRD ω-2θ scans of the as-grown planar and on-wafer nanoLED (after etch #1 + KOH etching) samples were used to assess potential changes in material strain that occurred upon nanopatterning. Figure 4 shows high resolution scans of the symmetric (0002) reflection; spectra are rather complex due to interference of the 6x active well, 6x sacrificial well, and 20x (2 nm In_0.02GaN_0.98N / 2 nm GaN) superlattices. Deconvolving these spectra is challenging without detailed confirmation of layer compositions and thicknesses. However, we can offer the following. Fringes F1 and F2 (blue arrows) in the planar and nanoLED scans have a spacing of Δθ = 0.31° or T = 14.8 nm by way of T = λ/(2Δθcosθ) [45], which agrees reasonably well with the 1x sacrificial well + barrier bilayer period of T = 15 nm (2 nm In_0.11Ga_0.89N + 13 nm GaN). It is believed that both the sacrificial and active well superlattices in the planar sample (blue) are highly strained and result in these broad fringes. Note that the sacrificial wells are not patterned in the nanoLED sample because etch #1 was stopped in the 1.6 μm GaN spacer layer. Upon nanopatterning, F1 and F2 appear to split, with new fringes (red arrows) appearing at slightly higher angles and with smaller separation (0.24°). This latter separation gives a 19.2 nm separation, which is close to the 1x active well + barrier bilayer period = 19 nm (2 nm In_0.14Ga_0.86N + 17 nm GaN). Since a shift to higher angles equates to a smaller c-axis (0002) d-space, which would result from a-axis relaxation (lowering c) due to nanopatterning, it is likely that the nanopatterned active wells have less strain than the planar case. Lower strain in the patterned active wells should manifest as a blueshift in PL, which did occur, as seen in Figs. 3(b) and 3(c).

 

Fig. 4. XRD ω-2θ scans of the symmetric (0002) reflection for planar and on-wafer, nanopatterned LEDs (after etch #1 + KOH etching). “GaN” peak is from the 2 μm GaN buffer and 1.6 μm GaN spacer. F1 (∼16.6°) and F2 (∼16.9°) are fringes associated with overlap/interference of the active and sacrificial well superlattices, which appear to split upon nanopatterning (see red arrows), likely due to relaxation of strain in the active wells.

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4. Summary

The nanoLEDs fabrication process presented in this work may be a promising route to create RGB “pixel” light emitters for future applications in next generation display technologies. Optically active nanoscale devices were fabricated and separated from their rigid growth substrate using easy and scalable methods, namely colloidal lithography and PEC etching. Colloidal lithography with plasma etching was used to define device geometry and PEC etching was used to selectively etch a sacrificial InGaN MQW to release devices into solution. PEC etch parameters were optimized for minimal faceting on the exposed N-face of c-plane GaN, which was achieved at low concentration (∼0.02 M KOH), allowing for large-scale release of nanoLEDs without damaging the active, light emitting layers. After release into solution, nanoLEDs had a 10 nm blueshift in PL compared to the planar device stack case, likely due to strain relaxation in the active wells. Temperature-dependent PL also demonstrated that the lifted nanoLEDs were reasonably efficient with an estimated IQE of 29%. The fabrication method presented herein may be a viable approach for scalable fabrication and lift-off of self-emissive LEDs for next generation displays in emerging mobile and wearable electronics.