Future space telescopes, especially X-ray telescopes, will require thin mirrors to achieve high optical throughput. Thin mirrors are more difficult to fabricate than thick mirrors, but recent advances have made accurate fabrication of thin mirrors possible. However, mirrors must have a reflective coating, which typically has non-repeatable and non-uniform intrinsic stress that deforms a thin mirror. Reducing coating stress by controlling deposition parameters typically reduces reflectivity. Non-uniform integrated stress compensation (NISC) methods, in which spatially controlled stress is applied to the mirror substrate backside to balance the frontside coating stress, decouple the film stress from the reflectivity. Ion implantation is one NISC method, where high-energy ions are implanted into a glass or silicon substrate to generate stress near the substrate surface. In this paper, we demonstrate the use of ion implantation for stress compensation of 30 nm thick chromium films applied to the front of five silicon wafers. The reflective films have mean integrated stress between −8 and −35 N/m, which cause deformations between 400 and 1600 nm RMS. We demonstrate that these wafers can be restored to the pre-coating shape to within 60 nm RMS, in most cases within 1/20th of the coating deformation.
© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
For optical applications where mass is constrained, such as in space telescopes, the use of thin mirrors may allow larger collecting area and/or lower cost than thick mirrors. In addition to benefiting from mass reduction, X-ray telescope mirrors have a nested architecture as shown in Fig. 1, where the use of thin mirrors reduces blockage from the mirror edges and allows a denser nesting. The Lynx X-ray Observatory (or Lynx), which is being studied as a concept for the 2020 NASA Astrophysics Decadal Survey , will require thin accurately-figured grazing-incidence mirrors with a high-reflectivity X-ray coating in order to provide the large collecting area (~2 m2 effective area) and high angular resolution requirements (~0.5 arc-second half-power diameter) that enable the mission to achieve its science objectives. The required mirrors will be approximately 0.5 mm thick and may require axial slope errors on the order of 0.1 arc-second root mean-square (RMS).
Thin mirrors are more difficult to fabricate than thick mirrors, but recent advances, such as magneto-rheological finishing (MRF)  and ion-beam figuring (IBF), have made figuring thin mirrors possible. For example, Zhang et al.  have successfully fabricated thin silicon X-ray mirrors using polishing  and IBF  that are rapidly approaching the accuracy requirements of Lynx. However, mirrors (for reflecting any wavelength of light) must usually be coated with thin films to meet reflectivity requirements, and thin films typically exhibit intrinsic stress, which deforms the mirrors. Applying finishing processes, such as IBF or MRF, after coating deposition would cause additional deformation from the removal of stressed material.
For X-ray telescope mirrors, reflective films are either single-layer dense metals such as iridium [6–8], or multilayer films [9–12]. Single-layer iridium films, typically at least 15 nm thick, are deposited using magnetron sputtering to maximize reflectivity (which requires film roughness less than about 5 Å and density near that of bulk iridium). Using low argon gas pressure during the deposition results in low roughness and high density, but very large intrinsic stress around −3 GPa (compressive) . The integrated stress, defined as the film stress integrated over the coating thickness, is therefore usually around −45 N/m. The coupling between high optical quality and large stress requires a compromise of one or both of these properties. Currently, Lynx does not have an error budget with quantitative allocations to effects such as film stress. However, recent simulations by Chalifoux, et al. have shown that for segmented mirrors, Lynx may require integrated stress magnitudes <0.2 N/m, depending on the error allocation . In addition, as discussed below, for Lynx, iridium film thickness non-uniformity would likely need to be significantly better than ± 1%, a difficult task on a curved substrate.
Several approaches to addressing the film stress problem are under development. The most direct approach is to adjust deposition conditions that result in minimum integrated film stress while maintaining acceptable X-ray reflectivity. Relying on in situ curvature measurement, Broadway et al. have deposited an iridium film with integrated stress of −0.05 N/m, and 5 Å roughness . This approach may meet Lynx requirements if it can be applied to curved mirrors with similar results. However, one concern with this method is that even minor film thickness non-uniformity and non-repeatability (which were not measured by Broadway et al.) will significantly affect the mirror figure .
Annealing an iridium film can reduce (but not eliminate) stress , but can also affect the film composition, roughness, and density . Multilayer films may also change as a result of annealing , which will impact reflectivity. Another approach is to deposit films on both sides of the mirror, with the goal of balancing the stress from each film [7,8,16]. The effectiveness of this approach will be degraded by film integrated stress non-repeatability or non-uniformity (which can arise from film thickness variation, for example).
In addition to ion implantation, there are several non-uniform integrated stress compensation (NISC) methods under development, which are intended to balance a non-uniform film stress. These methods include silicon oxide patterning [17,18], active mirrors , differential deposition [20,21], substrate bias during deposition , magneto-strictive films , and laser micro-stressing . Currently there is no approach that, on its own, has been shown to be sufficient for Lynx, and it will likely be necessary to combine one or more stress mitigation approaches (such as adjusting deposition parameters or balancing front- and back-side film stresses) with one of the NISC methods . One major advantage of the NISC methods, compared with adjusting the deposition parameters, is that they decouple the optical quality of the coating and the deformation from the coating stress, so they can be optimized separately.
Implanting high-energy (~MeV) ions into the backside of a substrate, to generate a controllable stress , is another method of compensating for coating stress, and is illustrated in Fig. 2. We demonstrate that ion implantation is capable of reducing film stress-induced deformation by a factor of about 20 on flat wafers. We have demonstrated elsewhere that oxide patterning offers better film stress compensation , but ion implantation offers a simpler process that may be compatible with front- and back-side film stress balancing approaches, and may enable multiple cycles of correction. Further improvement to the accuracy of ion implantation may also be possible.
2. Process overview
We demonstrate the use of ion implantation for film stress compensation by restoring five flat wafers, coated with stressed chromium films, close to their pre-coating shape. While X-ray telescope mirrors have iridium or multilayer coatings, we used chromium as a low-cost surrogate for this demonstration. Rather than using curved X-ray mirrors, we also chose to demonstrate the technique using low-cost flat silicon wafers (0.52 mm thick, 100 mm diameter, <100> orientation, double-side polished). Flat wafers are easier to measure than curved mirrors, and our measurement sensitivity is better since flat wafers deform more than curved mirrors in response to a given integrated stress.
We measured the surface topography of the front side of each wafer, then sputtered about 30 nm of chromium (with compressive stress) onto the front surface, and measured the wafer again. From the measured deformation, we calculated the integrated stress distribution in the chromium film. We then implanted a non-uniform distribution of ions into the back (uncoated) surface to generate an integrated stress distribution that compensates for the film integrated stress distribution. Finally, we measured the wafer again, and compared it with the original measurement. Ideally, the film stress compensation process results in no difference between the initial and final measurements. The entire process is summarized in Table 1. Some of these process steps are already required for making a mirror, and we highlight the three additional steps required for film stress compensation using ion implantation.
This process may be used to compensate for film stress in a variety of reflective films, whether single-layer or multilayer. The requirements for the film are that: it exhibits compressive integrated stress, its integrated stress is stable over time, and its stress and optical properties are not significantly degraded by annealing at 120 °C.
3. Metrology and stress calculation
We used a Shack-Hartmann surface topology metrology system, developed by Forest et al. , with a 635 nm diode laser source. This metrology tool measures surface slopes, with a 2D sampling period of 2.24 mm. We fit derivatives of Zernike polynomials to the measured slopes, using a pseudoinverse, to calculate the surface height. The measurement repeatability, determined by measuring a flat (~λ/4 peak to valley) reference block over the course of two weeks and comparing measurements from sequential days, was 14.1 nm RMS over a 100 mm diameter. The metrology system was enclosed in a box to reduce air turbulence (which introduces noise into the measured wave front). There was no precision temperature control, and room temperature variations were around ± 2 °C. There was no vibration isolation, but for each measurement, we averaged 100 images over about 1 minute.
During measurement, wafers were held in a low-stress mount developed by Akilian et al. . We developed a careful procedure to repeatably align wafers and minimize distortion imposed by the mount. A reference silicon wafer, 0.4 mm thick, was measured daily over two weeks. The measurement repeatability of this wafer, as calculated by comparing measurements from sequential days (with one outlying measurement removed), was 18.4 nm RMS. The spectrum of this variation, in terms of normalized Zernike polynomial coefficients, is included in Fig. 3 and Fig. 11. In both figures, Zernike polynomials (labeled ) of the same radial degree () and frequency (), were added as a root-sum-of-squares to condense the figures. The mount causes a small amount of deformation, especially astigmatism ().
We calculated the non-uniform stress distribution in the chromium film and in an implanted layer from the deformation caused by those process steps (i.e., the difference between a measurement taken before and after each step). We calculated the integrated stress using an analytical method  or using a pseudoinverse method . With perfect metrology, the non-uniform equibiaxial stress distribution (an equibiaxial stress state is where the in-plane normal stress is the same in all directions) calculated from the measured deformation would be unique and there would be no difference between the measured deformation and the deformation calculated from the stress distribution. However, even a small amount of metrology noise results in a non-unique stress distribution, with different stress distributions causing slightly different deformations. Using stress distributions with higher-order Zernike terms allows slightly better fitting to the measured deformation, but results in unrealistic stress distributions (with large-amplitude alternating tensile and compressive stresses, especially at the edges). We therefore limit the deformation measurements to the first 4 orders of Zernike polynomials (14 terms, excluding piston), and the stress distribution to the first 2 orders of Zernike polynomials (6 terms). The difference between the measured deformation and the deformation calculated from the stress distribution is <10 nm RMS in all cases, smaller than the measurement noise.
Substrate thickness variation (<5 μm for these wafers) will cause some stress calculation error , but this is below our current metrology noise level. We deduce the mean wafer thickness from the wafer mass, with an uncertainty less than ± 0.1 μm. The uncertainty of mean integrated stress from this error is small compared to the ~0.2 N/m uncertainty from measurement noise.
4. Coating and annealing
The purpose of the coating, for this demonstration, is to provide a stable compressive stress that we can compensate with ion implantation. We did not measure the reflectivity of the coating, but aside from the annealing cycles that are necessary to stabilize the implanted stress (see Section 6), we assume there is no reason ions implanted into the back surface would affect the coating deposited on the front surface. Annealing at 120 °C could potentially affect film morphology and roughness, and this should be considered when using this technique to compensate for film stress. One of the benefits of stress compensation, compared to optimizing deposition parameters to reduce coating stress, is that the optical quality of the film can be optimized without having to worry about the intrinsic stress. Thus, we are only concerned with the film stress in this demonstration.
The stress from ion implantation arises due to damage to the crystal lattice. There may be residual surface damage from grinding and polishing of the wafers, which could affect how much stress is generated from ion implantation. Prior to coating with chromium, we removed surface damage on the wafers (except wafers 1 and 2) by growing a 1.2 μm layer of wet thermal silicon dioxide at 1050 °C on each side of the wafer. The oxide grows partially into the silicon, so when we strip the oxide film using dilute hydrofluoric acid, the top ~0.5 μm of the original silicon is removed. This process caused an average of 34 nm RMS height change of the wafers, dominated by astigmatism () and spherical deformation (). In previous experiments , we had found that additional oxidation and stripping cycles result in deformation below our metrology noise floor, leading us to stop after one cycle in this work.
The five wafers were cleaned and then coated with chromium using a sputtering tool, produced by AJA International, with a radio-frequency (RF) magnetron sputtering source. The background pressure was 1.5 × 10−5 Torr, the sputtering gas was argon at 3 mTorr, and the sputter gun power was 150 W, resulting in a 0.095 nm/sec deposition rate (as measured by a crystal microbalance prior to deposition). The wafers were RF biased with negative voltage during coating to ensure a compressive film stress, due to the atomic peening effect [22,30]. A compressive stress is necessary for this demonstration since ion implantation also generates compressive stress. Coatings with high reflectivity also typically exhibit compressive stress [6,31].
The coated wafers were annealed at 200 °C for 2 hours in a tube furnace with nitrogen flow, to stabilize the coatings . This also reduces the stress in the coatings, which others have used to reduce iridium film stress without affecting reflectivity . The deformation caused by the coating is listed in Table 2 for each wafer. The large variability in integrated stress is a result of a coating chamber calibration error, which resulted in run-to-run coating thickness variation. This variation is not a problem for stress compensation using ion implantation, and demonstrates the flexibility of this process.
The coating stress is not perfectly uniform. A uniform stress produces a measured deformation entirely composed of spherical deformation (). Figure 3 shows the Zernike spectrum of the coating deformation after annealing, for all deformation components that are produced by non-uniform coating stress. Several terms, especially , are far above the metrology noise.
After coating and annealing, the coated wafers were annealed again, at 120 °C for 4 hours in a nitrogen atmosphere, to determine whether changes would occur in the coatings during the post-implantation annealing cycle (Section 6). We measured no significant deformation from this second annealing step. This annealing step would not normally be necessary, but was used in this demonstration to ensure that residual error after compensation would not be a result of coating stress relaxation during the post-implantation annealing cycle.
5. Ion implantation
The ion implantation was performed at the MIT Plasma Science and Fusion Center, using a tandem linear ion accelerator. Negative silicon ions are generated from a solid silicon sputter target, and accelerated to a high potential terminal (set to 660 kV), where electrons are stripped by nitrogen gas bled into the terminal region. The resulting positive ions, which have varying charge states ranging from + 1 to + 3 or more, are accelerated away from the high potential terminal to reach their final energy. The desired ion beam energy is selected using a magnetic field and an aperture. In this demonstration, we used an ion beam composed of 2 MeV Si++ ions. The ion beam is focused using an electrostatic quadrupole lens, located about 4 meters from the wafer, to a diameter of ~3 mm on the wafer. The ion beam is electrostatically steered to any position on the wafer. The pressure in the beamline, measured near the steering plates, was (8 ± 1) × 10−6 Torr during all implantations.
The wafer was fixed in position, with its back surface normal to the ion beam, on an electrostatic chuck (detailed below). The ion beam current was continuously monitored using a pico-ammeter (RBD Instruments model 9103), and the implanted dose was calculated by integrating the ion current over time. To ensure accurate ion dose measurement, secondary electron emission from the wafer surface due to ion impact was suppressed by floating the wafer and picoammeter at + 1 kV potential (any potential above around + 0.5 kV results in the same current measurement, indicating that secondary electron emission is suppressed). This potential also provided the electrostatic force to chuck the wafer.
The wafers were implanted on the back-side with a non-uniform dose, which was determined using the stress-dose calibration shown in Fig. 4, and stress maps as described in Section 3. The number of ions to implant at each point on the wafer (the implant points were on a grid with 2 mm pitch) was calculated from the dose map by de-convolving the ion beam profile. After calculating the dwell time at each point, we re-calculated the expected dose distribution, then stress distribution, and finally the expected deformation of the wafer. In all cases, the simulated deformation error resulting from the dose variation was less than 5 nm RMS.
Prior to implanting each wafer, the ion beam position and profile on the wafer were measured as a function of the beam steering plate voltages, using images of an aluminum oxide plate, which fluoresces from the ion beam. We calculate the beam profile assuming the fluorescent intensity is proportional to the ion flux. For the calibration wafers (Fig. 4), 50% of the ion flux is contained within a 3.04 mm diameter, and for the compensation wafers, 50% of the ion flux is contained within a 3.29 mm diameter.
The total implanted dose for the compensation wafers was in the range of (0.4 - 1.0) × 1014 ions/cm2. During the implantation, the ion current was held to 1.5 ± 0.1 μA. Using computer control, the ion beam was steered to a point on the wafer and held until the desired number of ions at that point was accumulated, then moved to the next point in the scan. For each wafer, the total dose was accumulated over 10 scan cycles, to ensure that any drift in the ion beam profile over time affects the wafer evenly over the surface.
The ion beam generates about 1.5 W of heat in the wafer, and we have found that wafer temperature during implantation can strongly affect the final stress. Prior to this demonstration, we used a chuck (called the kinematic chuck) that contacted the wafer at only 6 points: 3 balls contacting the back surface and 3 pins contacting the wafer flats. With the kinematic chuck, the heat loss was primarily through radiation, and the wafer temperature depended strongly on the ion beam current. We measured wafer temperature for a range of ion beam currents, shown in Fig. 5, using a thermocouple taped to the back of a test wafer (with thermal paste to ensure good thermal contact with the wafer). We measured the beam current after the temperature measurement was completed, since the secondary electron suppression potential interferes with the thermocouple measurement. We also implanted several other wafers with the same ion dose and measured the implanted stress, after annealing for 4 hours at 80 °C (a previous annealing protocol), with results shown in Fig. 6.
To allow for varying ion current, we built an electrostatic chuck (called the solid chuck) to keep the wafer near room temperature. The solid chuck, shown in Fig. 7, consists of an aluminum plate (6.35 mm thick) covered in a layer of polyimide tape (25 μm thick). The wafer is constrained laterally by a metal ring (with three points of contact with the two wafer flats), which also enables biasing the wafer at + 1 kV to provide an electrostatic force between the wafer and aluminum plate. Figure 5 shows that the solid chuck kept the temperature much lower than the kinematic chuck, and Fig. 6 demonstrates that the integrated stress repeatability does not depend on the ion beam current for the solid chuck.
6. Post-implantation annealing
Annealing after ion implantation is critical for stabilizing the post-implantation stress. Ion implantation causes damage to the silicon crystal lattice , which generates the observed stress. In the semiconductor industry, this damage is often undesirable, so implanted wafers are annealed to heal this damage. In our case, we require that some damage remains and is stable.
Figure 8 shows the effect of annealing on stress from ion implantation over time. Annealing at higher temperatures reduced the mean integrated stress, but also reduces the drift in stress over time. Annealing at both 100 °C and 120 °C showed no significant drift over about 1 week, so we chose to anneal all implanted wafers at 120 °C for 4 hours in a quartz tube furnace (200 mm diameter, 8 SCCM nitrogen gas flow). The tube furnace temperature is held constant to within 1 °C, as measured by three thermocouples located between the quartz tube and the thermal insulation. We previously measured the temperature inside the tube using a thermocouple, and found the internal thermocouple to be 2.5 °C lower than the external thermocouples, but steady to within ± 0.5 °C.
To further understand the stability of the post-implantation stress, we monitored five wafers, which were implanted to achieve integrated stress between −20 and −30 N/m (compressive) and then annealed at 120 °C for 4 hours, over four months. The change in spherical curvature (the Zernike component) over this time is shown in Fig. 9. Three of the wafers (RT1, RT2, and RT3) were held at room temperature. Two of the wafers (HT1 and HT2) were baked three times, for 4 hours at 70 °C each time. For these two wafers, the 4th-6th data points in Fig. 9 were measured after each baking cycle. We found no significant drift for any of the wafers, and all variation was consistent with metrology noise (which is about 12 nm RMS for , as shown in Fig. 11).
7. Stress compensation results
Figure 10 shows the coating deformation for one wafer along with the difference between the pre-coating and the post-compensation surface measurement. Ideally, after ion implantation and annealing, the wafer shape would be identical to the pre-coating shape, to within metrology noise. The Zernike spectrum of the residual error for each wafer is shown in Fig. 11. For all but one wafer, the residual error spectrum is dominated by spherical curvature error (). Wafer 1 and wafer 2 were not oxidized and stripped (as described in Section 4), which may explain the astigmatism () observed in these wafers. Wafer 4 also exhibits significant astigmatism, but we do not know the cause of this. Table 2 summarizes the results from the five wafers used for this demonstration.
Two possible causes of the spherical curvature error () in the compensation wafers are: an error in the implanted dose, and an error in the annealing temperature. The data in Fig. 8 suggest that the integrated stress decreases approximately 0.6% per 1 °C change in annealing temperature, so the spherical curvature error we observe would correspond to a difference in annealing temperature between the calibration and compensation wafers of about 6 °C, on average. This error is far larger than would be expected from the tube furnace (see Section 6), so this is unlikely to be the primary cause of the observed spherical curvature error.
Dose measurement error, which is the difference between the measured ion dose and the true ion dose, could also cause the spherical curvature error. Using the data in Fig. 4, we estimate that the dose error that would cause the observed spherical curvature error is about 4% ± 1% for each wafer. This suggests that, for a given true dose, the measured dose for the compensation wafers may have been 4% higher than the measured dose for the calibration wafers (each set was implanted on different days). Since the ion dose measurement is based on the ion current, and we assume all ions have a + 2 charge state, charge exchange with residual gas in the beamline could result in a dose measurement error. In addition, the electrostatic chuck (see Fig. 7) has a conductive rim, and ions that impact this rim are also included in the measured dose. This could cause dose measurement error as the ion beam profile varies day-to-day; in this experiment, the ion beam profile diameter was 8% larger for the compensation wafers than for the calibration wafer (see Section 5).
We also attempted to correct one wafer that was coated on both front and back with chromium. The front-side coating was 30 nm and the back-side coating was thinner, 20 nm, to ensure a net compressive stress that can be compensated by ion implantation. The net deformation from the coatings was 597.5 nm RMS, and the difference between the pre-coating and post-compensation measurements was 157.1 nm RMS. We used the stress-dose calibration of Fig. 4 to implant this wafer, despite the fact that the implanted side was coated. The resulting deformation was different from the bare silicon wafers, suggesting that the stress in the back-side coating changed as a result of the implanted ions, or the energy loss of the ion passing through the coating affects the damage to the underlying silicon. However, with proper calibration, it may be possible to accurately implant double-side coated wafers. This could make ion implantation compatible with other stress-balancing approaches [7,8].
8. Conclusions and future work
Ion implantation is an effective method of compensating for compressive film stress in silicon mirrors. The process is simple, since only three process steps beyond the normal mirror production process are required. We demonstrated reduction of coating stress deformation using ion implantation by a factor of over 20. While this is currently not quite as effective as the patterned oxide method , there are a few advantages of ion implantation. The simplicity of the process may be beneficial for X-ray telescopes like Lynx, where many mirrors must be produced. We also showed that film stress that has run-to-run variation has no detrimental effect on the ability to compensate. Further improvement to the compensation process may be possible, for example through better ion dose control, better measurement of the ion beam profile, and better metrology.
We have demonstrated that ion-implanted wafers annealed at 120 °C are stable, to within our metrology repeatability, over more than four months. We have also shown that there is no measurable effect of baking these wafers for 12 hours at 70 °C. For a mission like Lynx, more repeatable metrology and wafer mounting would be required to ensure that the stability of implanted silicon is sufficient. We have shown that increasing the annealing temperature improves stability over time, but also increases the required implant dose to compensate for the additional stress reduction from annealing at higher temperatures. It may also be possible to use annealing to improve the stress compensation accuracy, by implanting wafers with a larger-than-desired integrated stress, then iteratively annealing them at successively higher temperatures (all above 120 °C to ensure stability) until the measured surface topography reaches the original surface topography.
We have shown that implanting ions through a chromium film does produce a compressive stress, but this stress is somewhat smaller than the stress generated in bare silicon. Using ion implantation on mirrors that have coatings on both sides could be advantageous because coating both sides of the mirror has been shown to reduce the coating-induced deformation of a curved mirror by a factor of ~20 . If we repeated the stress-dose calibration of Fig. 4 for ion implantation through such films, it may be possible to achieve accurate compensation of the residual error after coating both sides, using ion implantation.
NASA Research Opportunities in Space and Earth Science (ROSES), Astrophysics Research and Analysis (APRA) (NNX17AE47G).
The authors acknowledge William W. Zhang, Lester C. Cohen, Kai-Wing Chan, and David L. Windt for useful discussions.
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