We demonstrate the hybrid integration of an O-band vertical-cavity surface-emitting laser (VCSEL) onto a silicon photonic chip using a grating coupler that is optimized to simultaneously provide feedback to maintain the single emission polarization and efficient in-plane coupling. The grating coupler was fabricated on silicon-on-insulator using a standard silicon photonics foundry process, and integrated with a commercially available VCSEL. A transparent VCSEL submount was fabricated with femtosecond laser templating and chemical etching to simplify the passive and active alignment steps. A record-high VCSEL-to-chip coupling efficiency of −5 dB was obtained at a bias current of 2.5 mA. The slope efficiency and output power are competitive with microcavity hybrid silicon lasers. The results show the feasibility of VCSELs as low threshold current on-chip sources for silicon photonics.
© 2017 Optical Society of America
Silicon photonics (SiP) has the potential to satisfy the cost, volume, and integration requirements of photonic integrated circuits (PIC) for a wide range of applications including optical communications, computing, and sensing . Despite rapid developments in this field, laser integration remains a challenge. So far, monolithically integrated lasers on Si using germanium  and indium phosphide based quantum dots  either have low power efficiencies or require processing steps that are incompatible with conventional Si photonics fabrication. Therefore, hybrid integration has emerged as a more practical approach in the near term. One hybrid integration approach is to bond III-V gain material onto SiP and design hybrid III-V-Si waveguide modes that can be optically amplified [4–6]. The alignment precision required between the III-V device and features in the SiP is relaxed and the bonding can be done at the wafer-scale. The second approach is to mount pre-processed laser dies onto SiP chips using assemblies, flip-chip bonding, and wire bonding [7, 8]. Although this may require larger die areas and more manufacturing time, it has the major advantage that the lasers can be burnt-in and pretested prior to co-packaging with SiP.
Long-wavelength VCSELs offer a promising path for hybrid integration. Unlike edge-emitting lasers, the optical output position of a VCSEL is less sensitive to the cleaving or dicing conditions. VCSELs have low threshold currents, high direct modulation bandwidths, circular beam profiles, and can be manufactured at high densities [9–11]. VCSELs have been integrated with SiP using grating couplers (GCs) [12–15]. However, to the best of our knowledge, the lowest VCSEL-to-SiP reported coupling loss is about −10 dB . The integration of VCSELs onto SiP is challenging due to the low control over the modes and polarization state in generic VCSELs. Even if a VCSEL supports only a fundamental transverse mode, the degenerate linearly polarized (LP) states can lead to polarization switching (PS) . Since SiP devices are polarization sensitive, an unknown input polarization state and PS can lead to high insertion loss.
In this article, we report the hybrid integration of a commercial VCSEL at a wavelength near 1330 nm with a foundry-fabricated SiP chip where a vertical grating coupler (VGC) provided external optical feedback (OF) to maintain the VCSEL polarization state. The VGC was apodized to improve the coupling efficiency without phase-matched power combination  or tilted flip-chip bonding . A transparent silica VCSEL submount fabricated by femtosecond laser direct writing simplified the alignment process. The VCSEL polarization was stabilized to the fundamental transverse electric (TE) mode of the SiP waveguide. A record-high VCSEL-to-SiP coupling efficiency of −5 dB at 2.5 mA was demonstrated. The laser output power and efficiency are competitive against other microcavity hybrid lasers.
2. Design of VGC for VCSEL polarization control
The polarization of the VCSEL emission can be controlled by breaking the transverse symmetry in the device or by introducing polarized OF . Due to the strong birefringence and high index contrast, a Si VGC can be designed to simultaneously provide polarized OF into a VCSEL in the out-of-plane direction and efficient coupling of the VCSEL output into an in-plane waveguide. Figure 1 shows our integration scheme of a SiP chip with a VCSEL using a VGC. The VCSEL output is directed downward to the VGC, which couples a part of the optical power to an in-plane Si waveguide. A compound extremely short external cavity (ESEC) consisting of the VGC, buried oxide (BOX) layer, and Si substrate provides OF into the VCSEL. Lext is the length of the external cavity, which we define to be the distance between the bottom of the VCSEL and the VGC top surface. The bottom mirror of the VCSEL and the anti-reflection (AR) coated substrate are not part of the ESEC, but they are modeled with the ESEC to form an effective bottom mirror in the analysis to follow.
2.1 Simulation model
To simulate the VCSEL with feedback, we adopt ESEC VCSEL model in , which is summarized in the Appendix A.1. This model applies when the round-trip time of photon in the external cavity is much shorter than the photon lifetime of the VCSEL. This condition can be verified by simulating the reflectivities of the ESEC. Briefly, the ESEC model assumes phenomenological rate equations for the two degenerate polarization modes of the VCSEL and includes a coupling term between the intracavity field in the VCSEL and the field in the ESEC to determine the conditions for single-mode TE (electric field parallel to the VGC grooves, in the direction of z-axis of Fig. 1), single-mode transverse magnetic (TM), and polarization switching (PS) operation. The OF is modeled by an effective reflection coefficient that accounts for the interference of light in the coupled cavities consisting of the internal cavity of the VCSEL and the external cavity (cladding layer), with an external mirror comprised of the VGC, BOX, and Si substrate. The Si VGC should simultaneously provide efficient coupling (for the TE mode) into an in-plane Si waveguide, and cause the external cavity to provide a higher TE back reflection (in the direction of y-axis of Fig. 1) than TM reflection to preferentially maintain TE emission from the VCSEL. The need for a stronger TE-polarized OF into the VCSEL leads to a trade-off in the coupling efficiency into the waveguide.
The effective field amplitude reflection, reff, as illustrated in Fig. 1, is a key parameter in the ESEC model. reff is the summation of the initial reflection of the bottom distributed Bragg reflector (DBR) mirror of the VCSEL and the successive reflections from the lower mirror of external cavity:Eq. (1). The coupling between the z-polarized (in TE direction) internal field (Ez1) that has been reflected at the bottom DBR mirror of VCSEL and the z-polarized field that has made p round-trips within the cladding (Ez2) is given asFig. 1. The expression of Ez1,2 is given in Appendix A.2. The coupling term for the x-component (for the TM polarization), κLLTM(y), is obtained similarly by replacing Ez1,2 by Ex1,2 in Eq. (2).
The VCSEL parameters for the ESEC simulations are summarized in Table 1. Generic values for VCSELs have been used where manufacturer values were not available. To model the VCSEL on SiP, the reflectivity of the lower mirror (rfTE, TM) of the ESEC was substituted with the back-reflection of a Gaussian beam incident on the VCG computed using the two-dimensional finite difference time domain (2D-FDTD) method. The SiP stack was included in the simulation. The VCSEL had a half-width half-maximum divergence angle (θ) of 5° [9,10] for the Gaussian field. The Gaussian beam was launched at the normal incidence (along -y in Fig. 1) to the VGC from the top of the cladding layer. In our design, the VCSEL and the VGC were mounted in near contact, separated by the thin cladding layer such that VCSEL beam diameter has not diverged significantly, which aids in the coupling efficiency.
To optimize for the coupling efficiency, the gratings were apodized by dividing the VGC into a periodic part characterized by a duty cycle, DCp, and period, Λp, and an aperiodic part with N grating tooth-groove pairs (Fig. 1). Particle swarm optimization (PSO) was utilized to search for the VGC designs with the highest VCSEL-to-SiP in-plane coupling efficiency for the TE polarization while maintaining a higher TE back reflectivity than for the TM polarization. As a higher OF (higher rf) leads to a stronger dependence of the onset current of PS on Lext , the external cavity can be used to control polarization of the VCSEL. The layer thicknesses were fixed by the SiP foundry process. The top Si layer was 300 nm thick; the partial etch depth was 150 nm thick; the BOX layer was 800 nm thick; and the oxide cladding was 250 nm thick. The SiP was designed for an operation wavelength near 1330 nm to match the VCSEL used in the experiment.
2.2 Simulation results
The PSO resulted in an optimal VGC design having Λp = 473 nm, and DCp = 36.8% with a repetition of 40 periods. The apodized gratings had two tooth-groove pairs (N = 2), with widths of the first and second teeth of T1 = 178 nm and T2 = 150 nm, and the first and second groove widths of W1 = 299 nm and W2 = 100 nm as shown in Fig. 1. The optimized VCSEL emission center position was 6.41 μm away from the start of the Si waveguide along x-axis. Figure 2(a) shows the computed back reflectivity, which is defined as the fraction of VCSEL power that is returned, upward propagating ( + y direction) at the VGC top surface. The in-plane coupling efficiency into the fundamental TE mode of the Si waveguide is −3.5 dB at 1331.3 nm as shown in Fig. 2(b). At this wavelength, the back reflectivities are −4.5 dB and −6.5 dB for the TE and TM polarizations, respectively; and the coupling efficiency remains higher than −5 dB even when the period varies between 472 nm and 482 nm as shown in Fig. 2(c). The 3-dB in-plane coupling efficiency bandwidth of the nominally designed VGC in Fig. 2(b) is 11.6 nm. The narrow optical bandwidth is a physical limitation of the VGC due to the blazed grating diffraction effect . Since the VCSEL wavelength accuracy could be guaranteed to within ± 2 nm [9,10], our design took the in-plane coupling efficiency a priority over the optical bandwidth. As shown in Fig. 2(d), the lateral (along x-axis) alignment tolerance of source over the VGC is ± 5.1 μm to maintain a coupling efficiency > −5 dB. The combination of the back reflectivity, VCSEL parameters (Table 1) and the SiP stack (Fig. 1) confirms the validity of the ESEC model. The round-trip time of photon in the external cavity is about 2.4 fs, which is much shorter than the VCSEL photon lifetime (ôp) of about 4 ps calculated by Eq. (7) in the Appendix A.1.
Figures 3(a) and 3(b) show the power and polarization of the VCSEL optical output at 1331.3 nm as predicted by the ESEC model by plotting the solutions of the VCSEL rate equations. For a better understanding of how OF from an ESEC affects the PS of the VCSEL, maps of the output polarization as a function of the bias current and external cavity length (Lext) without an ESEC are shown in Fig. 3(c) and with an ESEC in Fig. 3(d). The simulations assume that the VCSEL is polarization degenerate (refractive index, g0 and dg/dJ are the same for TE and TM polarizations) in order to demonstrate the effect of the ESEC.
Stable (unstable) solutions are shown in black (red). Stability means that when a perturbation is applied to the rate equations, the carrier and photon numbers remain bounded, and the starting steady-state solutions are recovered after the perturbation is turned off. In unstable solutions that have non-zero powers for both TE and TM modes (red dashed line, red triangles), PS occurs and the polarization state of the laser changes with time.
As shown in Figs. 3(a) and 3(c), when there is no OF from the ESEC (rf = 0), the VCESL supports both TE and TM modes and PS occurs for all bias currents. The threshold current of the laser (Ith) is 0.61 mA and the slope efficiency is 0.24 mW/mA. Figure 3(b) shows that with the ESEC providing polarization-dependent OF, single-mode operation with only the TM mode is unstable (red line) for a bias current between the threshold and 6.9 mA. Meanwhile, over this current range, the TE-only operation (black dot) is stable. The slope efficiency (0.22 mW/mA) and threshold current (0.64 mA) are similar to the case without the ESEC. When the current is > 6.9 mA, the PS occurs as we discussed in the case of Fig. 3(a). Figure 3(d) shows the VCSEL emits a single TE polarization with ± 175 nm tolerance of Lext at bias currents < 6.9 mA, which corresponds to I/Ith of 10.8. When Lext is between 437 nm and 500 nm, the VCSEL emission is TM polarized for bias currents less than 15 mA, which is the maximum working current of the VCSEL used in the experiment [9, 10].
Variation of the substrate thickness of the VCSEL would lead to a shift in the laser wavelength. From transfer matrix calculations, a ± 5 μm variation in the substrate thickness around 150 μm causes a reflection phase variation of ± 2.3° for the effective bottom mirror of the VCSEL. According to the round-trip phase condition of the composite VCSEL and external cavity , the phase variation leads to a wavelength shift of the fundamental laser mode (1331.3nm) of about ± 5 nm. Although the worst case in-plane coupling efficiency of the VGC drops to −6.7 dB as shown in Fig. 2(b), TE-only operation can still be maintained, because the TE reflection remains higher than the TM reflection (Fig. 2(a)). Over a wavelength of 1331.3 ± 5 nm, the VGC TE back reflection varies between −4.9 dB and −1.8 dB, and the TM back reflection varies between −6.6 dB and −6.3 dB. In the worst case, the tolerance of Lext is reduced to about ± 169 nm to achieve TE-only emission. Variation in the AR layer on the bottom side of the VCSEL would increase r2 and thus decrease the incident power onto the VGC, but the TE-only operation can be maintained if r2 increases by less than 1%. Thus, the simulation shows that the ESEC (VGC) can robustly and flexibly set the VCSEL emission polarization. In practice, the onset current of PS will be lower than the simulated value because the differential gain (g) and dg/dJ are slightly anisotropic due to the asymmetry resultant from stresses during epitaxial layer growth and device fabrication as well as birefringence of the semiconductor. Moreover, the gain compression coefficients may be different from the assumed values, which would also change the onset current of PS.
3. SiP fabrication and VCSEL assembly
The SiP chip was fabricated at CEA-Leti via a foundry process on an 8-inch silicon-on-insulator (SOI) wafer. Devices were patterned by 193 nm deep-UV lithography, followed by the dry etching. A 250 nm SiO2 cladding layer was deposited on top of the Si layer. Alignment marks in the top Si layer were designed to assist with the positioning of the VCSEL to the VGC as shown in Fig. 4(a). The VGC footprint was 12 × 18 μm2.
The VCSELs (RayCan) are bottom emitting, with anode and cathode contacts on the side opposite from the light emission surface [9, 10]. The VCSEL die with size of 450 × 250 × 150 μm3 as shown in Fig. 4(b) was precisely aligned with a novel transparent submount prior to bonding. The submount was fabricated by three-dimensional scanning of a tightly focused femtosecond laser (522 nm frequency doubled fiber IMRA America μJewel D-400-VR) to form a nanograting-template inside of a 250 μm thick silica plate and followed with chemical etching with 5% hydrofluoric acid  to open a through-hole for access to the anode and cathode contacts with needle probes. The transparent submount facilitated direct viewing of the SiP chip alignment marks that aligned to matching marks (<10 μm wide by 50 μm in depth) formed on the submount top surface and thus offered precise VCSEL to VGC positioning to around ± 3 μm. The VCSEL submount was diced to 0.8 × 0.8 mm2 area and is shown with through-hole and alignment marks, positioned over the SiP chip in Fig. 4(c).
The VCSEL die was first placed on a copper stage as shown in Fig. 4(d). Silver conductive epoxy (Epo-Tek H20E) was applied to the bonding pad of the VCSEL, which was aligned to the submount. The epoxy was cured by elevating the temperature of the copper stage to 90 °C and curing for three hours. Then the transparent submount was placed on top of the SiP chip to place the VCSEL output surface in contact with the cladding layer through a thin layer of UV curable epoxy (NOA 87) as shown in Fig. 4(e). The bare VCSEL chip emitted light in the quasi-TE polarization. A passive alignment step first used the alignment marks on the submount and SiP to position the VCSEL polarization axis to the VGC, was then followed by an active alignment step that maximized the output power of the GC, prior to bonding by UV curing of the epoxy. The flatness of the SiP chip surface is about ± 50 nm. The excellent flatness leads to the high coupling efficiency using the VCSEL-SiP vertical bonding process. The benefits of submount-assisted alignment compared with directly aligning the bare VCSEL chip are as follows: 1. The through-hole of the submount enables the VCSEL to be positioned by moving the probe tips that remain in contact with the VCSEL electrodes; 2. The alignment marks on the submount can help to improve the alignment accuracy between the VGC and the VCSEL; and 3. The larger size of the submount eases the manual handling of the small VCSEL die.
A schematic of the integrated assembly and measurement arrangement is shown in Fig. 4(f). The VGC coupled the VCSEL emission to an in-plane SiP waveguide. The optical output of the chip was collected through a TE grating coupler (GC) (from the CEA-Leti process design kit) with peak coupling efficiency near 1330 nm for coupling into a standard single-mode fiber with an 8° tilt angle. A 1.5 mm-long adiabatic linear rib waveguide taper connected the VGC output port to the input port of the standard GC. At the VGC end, the waveguide was wide and multimode; the strip (slab) width of the waveguide was 12 μm (18 μm). At the standard GC input port end, the waveguide was single-mode with a strip (slab) width of 400 nm (3 μm). The VGC coupling efficiency is reported at the end the rib waveguide taper. The output light of the standard GC was sent to an optical power meter and an optical spectrum analyzer. A sourcemeter was used to bias the VCSEL via electrical probing.
The light-current-voltage (L-I-V) and spectrum of the VCSEL on SiP chip at continuous-wave operation were measured at room temperature (24.5 °C) without thermal control. Before UV bonding onto the SiP chip, the VCSEL on submount had a slope efficiency of 0.24 mW/mA and a threshold current of 0.65 mA as shown by the black curve in Fig. 5(a). This is in good agreement with the simulation shown in Fig. 3(a). After integration and calibrating for the external test system loss, the on-chip slope efficiency was degraded to about 64 μW/mA near 2 mA and the threshold current was 0.7 mA as shown by the red curve in Fig. 5(a). In addition to the VGC coupling loss, the mismatch between the refractive index of the oxide cladding of SiP and the optimized index for the AR coating of the VCSEL would reduce the on-chip slope efficiency by making the bottom mirror of the VCSEL slightly more reflective. The measured coupling efficiency from the VCSEL to the SiP chip was > −5 dB for bias currents < 2.5 mA as shown in Fig. 5(b). The decreasing coupling efficiency with the increasing bias current was likely due to a red-shift of the laser emission from heating (Fig. 5(d)). Away from the optimal wavelength, the VGC in-plane coupling efficiency would be diminished.
Figure 5(a) shows the VCSEL to exhibit PS when the current exceeds 3.7 mA. The observed values for Ith, the onset current for PS and slope efficiency agreed well with the simulation shown in Fig. 3(b). The difference in the onset current of PS between the simulated result (6.9 mA) and the measured value (3.7 mA) may arise from the polarization dependence of the gain as discussed in Section 2.2. For example, the ESEC simulation assuming dg/dJ for TM polarized light is twice that of the TE polarization shows the PS onset is reduced to ~3.5 mA. Another factor that could contribute to the difference in the PS onset current is the limited thermal dissipation of the setup.
The VCSEL output polarization states were monitored with an InGaAs camera through a free-space polarization analyzer from the top of the assembly. TE corresponded to case when the polarization analyzer axis for maximum transmission was parallel to the VGC grooves, and TM corresponded to the orthogonal arrangement. Two camera images shown in Fig. 5(c) were recorded at a VCSEL bias of 2 mA. Spatial integration of the images over a 1 × 1 mm2 area centered at the VCSEL shows that the TE intensity was about 100 times higher than the TM intensity in the normal working current range (0.8~3 mA). The results show that the VCSEL emission was dominated by a single TE polarization. The on-chip VCSEL spectrum at various bias currents is shown in Fig. 5(d). The side-mode suppression ratio (SMSR) was 49 dB at a wavelength of 1333.1 nm at 2.76 mA. The wavelength shift was 0.62 nm/mA for currents < 3.5 mA, which corresponded to a shift of 0.23 nm per mW of power delivered to the device. In comparison, the standalone VCSEL had a redshift of only 0.18 nm/mW, indicating that the silica submount and bonding compromised the thermal conductivity.
The integrated VCSEL-on-SiP presented in this work has demonstrated the highest coupling efficiency, highest slope efficiency, and lowest current threshold compared to previous integrated VCSEL-on-SiP assemblies as summarized in Table 2 [14, 15]. This high efficiency was enabled by the polarization maintenance and in-plane coupling provided with an optimally designed VGC. A key benefit in our design is the absence of any additional components or features, such as microprisms and tilted bond angles to assist with coupling efficiency. The PS was observed at a moderately low current of 3.7 mA (5.3Ith), which may potentially be increased with further integration of heat sink. For comparison, when a similar VCSEL was bonded onto a thin copper strip in a separate assembly (not shown; the thermal conductivity of Cu is about 300 times higher than that of silica), although the observed coupling efficiency was lower (−8 dB at 2.5 mA), PS did not occur until the drive current exceeded 4.9 mA. Improved thermal conductivity can lead to a larger working current range for single TE polarization operation in the future.
Table 2 also shows the present VCSEL-on-SiP design to be a favorable low threshold current laser alternative to hybrid Si microcavities [5, 6] and VCSELs with Si high index contrast gratings . As summarized in the last three columns in Table 2, the on-chip output power, slope efficiency, and SMSR of our VCSEL-on-SiP are competitive with high index contrast grating VCSELs, as well as hybrid-Si microring and microdisk lasers.
For high volume production, active alignment can be entirely circumvented by using a precision die bonder. Placement accuracy of ± 0.5 μm can be achieved . Since the VGC can be designed to have a source position tolerance of a few microns (Fig. 2(d)), the VCSEL can be passively aligned and directly attached onto the SiP without the use of a submount.
In summary, we have demonstrated the VCSEL integration with a SiP chip using a specially designed, alignment-tolerant vertical grating coupler that simultaneously provided optical feedback to the VCSEL and efficient in-plane coupling. The on-chip coupling loss was reduced at the cost of optical bandwidth with an apodized grating design, but the laser wavelength was known a priori. A transparent submount was introduced for the VCSEL to simplify the passive and active alignment. In future work, a heat sink may be integrated with the submount to overcome the low thermal conductivity, and further improve the slope efficiency and polarization stability. Our VCSEL-on-SiP integration approach has a small footprint because no additional optical components or features are required. This approach combines the flexibility of SiP with known-good lasers, and can be scaled to higher power surface emitting lasers as well as other SiP platforms incorporating silicon nitride on silicon .
A.1 ESEC Model
The ESEC model  applies to VCSELs with an external cavity that has an optical round-trip time that is much shorter than the photon lifetime. The VCSEL is assumed to support two linearly polarized (LP) modes that are both fundamental transverse modes with nearly identical gain and loss. We associate the H-LP (high gain LP) and L-LP (low gain LP) modes of the VCSEL with the TE and TM incident modes onto the VGC, respectively, with the electric field of TE (TM) being parallel (perpendicular) to the VGC grooves. For greater clarity, TE and TM are used in the rate equations of a VCSEL, which are solved in the steady-state for the photon densities of two modes (PTE and PTM) as below:Eqs. (3) and (4), the photon lifetime is given by:Eq. (1) in the main text. The self-heating thermo-optic effect of the cavity modifies ng, TE, TM and shifts the VCSEL wavelength. This is modeled by ng TE, TM = ng0 TE, TM + (dn/dJ) J. The Gaussian emission profile of the VCSEL is split into two orthogonal polarization components (Ex, Ez), which can be coupled by the reflection from the external cavity as described in Eq. (2) in the main text. Parameters used in these equations are listed in Table 1. Photon density is converted to the optical power with the relationship: Power = Photon density ∙ hf∙dπS2/τp, TE, TM, where h is the Plank constant, and f is the optical frequency.
A.2 Gaussian beam model
In the 2D-FDTD simulations, the VCSEL emission profile was modeled as a Gaussian beam with parameters chosen to match the VCSEL used in the experiment [9,10]. Figure 6 illustrates the Gaussian beam parameters, such as the angular divergence, θx, z, position offset, δx, z, and beam spot size, Wx, z (defined to be half-width at half-maximum). The laser beam propagates in the -y direction starting from y = 0.
The Gaussian field (propagating in -y direction) and parameters are given by the following expressions, for the case of Ez (TE component),Eq. (8) – Eq. (10), with the difference that the expressions apply to Ex (x, y, z). For the VCSEL used in the experiment, the beam properties were W0x = W0z = 10 μm, and θx = θz = 5°. The Gaussian beam center was assumed to be at the center of the VCSEL aperture, such that δx = δz = 0.
A.3 Test calibration
In the measured coupling efficiency and emission spectra in Fig. 4, the transfer function of the standard GC, fiber array, and fiber connectors in the setup have been removed. The transfer function of the standard GC and fiber array was determined by a pair of calibration GCs connected to each other as shown below. The input light was TE polarized. The transfer function of a single standard GC measured with a fiber array is shown in Fig. 7. Fiber connectors and fibers in the setup had a total loss of 0.8 dB at the VCSEL working wavelength. After calibrating out the transfer function of the standard GC and loss of the test setup, we obtained the VGC coupling efficiency in Fig. 4(b).
The support of Natural Sciences and Engineering Research Council of Canada (NSERC) and Huawei Technologies Canada is gratefully acknowledged.
We thank Dr. Sylvie Menezo and Bertrand Szelag from CEA-Leti for layout support and fabrication.
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