The camera-based visible light communication (CVLC) exploiting rolling shutter effect (RSE) is a cost-efficient technique that ensures secured data transmission. By controlling the on-off state of the light emitting diode (LED), data can be modulated onto the emitting visible light. The corresponding data recovery can be realized by exploiting the RSE of the mobile-phone camera. In this paper, based on a commercial RGB-LED and a single mobile-phone camera, a wavelength division-multiplexing (WDM) CVLC system exploiting RSE is experimentally demonstrated. For the generation and reception of the WDM signals, a structure of three parallel-independent channels is applied to the system. To mitigate the sampling frequency offset (SFO) effect, a low-complexity sampling reconstruction (SR) scheme is proposed and used in each channel of the system. Experimental results show that with the help of the proposed SR scheme, the system can achieve a theoretical data rate up to 2.38 Kbits/frame, with the bit error rate (BER) lower than 3.8 × 10−3.
© 2017 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
Nowadays, visible light communication (VLC) has attracted attention from academia and industry since it has many advantages over the traditional radio frequency, including wide unregulated bandwidth, high security, and low cost. It is a promising complementary technique in 5G and beyond wireless communications, especially in indoor applications . Prior demonstrations have shown that VLC is capable of achieving a data rate beyond 1 Gbits/s in the indoor environment [2-3]. However, to achieve a high data rate, the photodiode (PD) is usually required in VLC systems, making this solution less cost-efficient as the PD is not yet integrated in the commercially available mobile-phone. Recently, instead of using PD, the camera image sensor has been reported to be used as the detector in VLC [4–10]. Meanwhile, it is reported that when camera image sensor is used as the VLC receiver, liquid crystal display (LCD) screen and light emitting diode (LED) array with special geometry feature can act as the VLC transmitter [4-5]. In the camera-based VLC (CVLC) system using LCD screen or special LED array, data transmission is usually based on two dimensional (2D) image information. As a result, these systems are sensitive to motion or geometrical distortion. Recently, LED-based CVLC system exploiting the rolling shutter effect (RSE) of camera image sensor has also been proposed and it is being studied extensively in academia [6–13]. In the CVLC system exploiting RSE, geometrical distortion doesn’t require to be considered any more. Moreover, the low-power LED based short-range CVLC exploiting RSE can be regarded as a relatively secure communication, since light propagation is directional and the communication coverage can be confined within a small area. At present, a number of LED-based CVLC systems with data rates of more than 1 Kbits/s have been experimentally demonstrated [6–8]. The prior demonstrations show that CVLC exploiting RSE has many prospective applications, such as encryption communication, short-range broadcast communication and near-field identification [10–12]. However, in most of the prior works [6–12], the issue of sampling frequency offset (SFO), which significantly affects the transmission performance and limits the transmission speed, has not been taken into account sufficiently. In , although an efficient demodulation scheme which is tolerant to SFO has been proposed, it requires extra sampling rate calculation at the receiver side.
In this paper, based on a commercial RGB-LED and a smartphone equipped with a camera of 13 million pixels (MP), a CVLC WDM system exploiting RSE is proposed and experimentally demonstrated. To generate and receive the WDM signal, three independent channels with the identical digital signal processing (DSP) processes are used in the system. Meanwhile, a low-complexity sampling reconstruction (SR) scheme is proposed to mitigate the SFO effect of the WDM CVLC system without requiring receiver-side sampling rate calculation, thus improving the transmission performance of the system. The WDM transmission over the CVLC system has been successfully realized with a theoretical data rate up to 2.38 Kbits/frame, while the bit rate error (BER) is below 3.8 × 10−3, the hard-decision forward error correction (HD-FEC) limit. To the best of our knowledge, we for the first time demonstrate a beyond 2 Kbits/frame CVLC system employing RSE.
2. Experimental setup
The experimental setup of the proposed CVLC system exploiting RSE is shown in Fig. 1(a). At the transmitter, an FPGA board based on Xilinx XC6SLX16 is used as the signal generator. Three independent digital I/O interfaces of the FPGA board are used to independently control the on-off state of three LED drivers, so as to realize simultaneous data modulation for the red, green and blue LED chips of the RGB-LED. After ~10-cm free space transmission, at the receiver, a lens is used for light collimation. Subsequently, a smartphone (Xiaomi Mi 4, which is equipped with a 13M-pixel camera, Sony IMX214) is deployed to capture the continuous state changes (on/off) of the light emitted from the RGB-LED. The photo mode of the smartphone is set as high dynamic range (HDR) mode with the corresponding resolution of 3120 × 4208. The captured photo is then uploaded to another personal computer (PC-2) for further off-line processing.
The WDM transmission scheme for the proposed CVLC system is illustrated in Fig. 1(b). At the WDM transmitter (TX), three parallel-independent branches are used to generate three signals to drive the red-LED, green-LED and blue-LED, respectively. In the following of this paper, the three branches are termed as R-channel, G-channel and B-channel, respectively. The processes of the signal generation in the three channels are identical, and it can be divided into the following three steps: (1) Pseudo-random binary sequence (PRBS) generation. A PRBS including 96 binary digits is pre-stored as the original data and is transmitted periodically. (2) 3B4B encoding. The encoding is used to mitigate the flicking effect of the system . (3) Header (Hd) insertion. After 3B4B encoding, there is no data symbol that contains more than four consecutive matching bits. Therefore, the sequence [0,1,1,1,1,1,1,0] is used as a header in the encoded data sequence and it can be used for synchronization at the receiver. After that, the output signals are used to independently drive the three RGB LED chips for data modulation.
The structure of the generated signals is shown in Fig. 2. For each sub-channel, the packet contains one synchronization header and one fragment of valid data. At the output of the RGB-LED, the emitted white light is the multiplexed signal of the red, blue and green lights from the RGB chips. Although the output light from the RGB-LED is in white color for human eyes sensing, the corresponding photo captured by the phone-camera is colorful due to the rolling shutter effect of the camera.
At the WDM receiver (RX), a row of pixels in the extracted colorful photo is selected and the corresponding RGB values of these pixels are extracted. The red/green/blue component of the RGB value is regarded as the received signal of the R/G/B channel. The received R/G/B signal can be recovered via DSP in each sub-channel.
The processes of the DSP for data demodulation are divided into the following four steps: (1) Pre-processing. In , to avoid blooming effect , the polynomial fitting is used to find the optimal thresholds for logic decision in the demodulation processes. Herein, based on the polynomial fitting, a preprocessing is implemented to mitigate the blooming effect. Firstly, the received signal is divided by the corresponding values of its 2-nd order polynomial fitting. Then, the DC component of the signal is removed. (2) Synchronization. The header in the received signal is used for timing synchronization in this step, such that the valid data in the received signal can be extracted. (3) Sampling Reconstruction (SR). In this step, we propose a low-complexity SR scheme to mitigate the SFO induced performance degradation of the CVLC system exploiting RSE. The principles of the proposed SR scheme will be discussed in details in Section 3. (4) Decision. A decision process is applied to recover the logic data 1 and 0. (4) 3B4B decoding. (5) BER analyzer. After the above (1)-(4) steps, the BER analyzer in each channel is used for error counting, so as to evaluate the transmission performance of the proposed WDM CVLC system.
3. SFO effect and sampling reconstruction
In the CVLC system exploiting RSE, because the sampling clock of the transmitter is different from that of the receiver, clock recovery (CR) based on synchronization header  is usually used in the receiver to estimate the bit duration. However, due to the fact that the sampling clock of the transmitter may not be an integer multiple of the sampling clock of the receiver and there is exposure overlapping effect  in CVLC system exploiting RSE, the duration of the received synchronization header may not be an integer multiple of bit duration. It is difficult to estimate an accurate bit duration and recover the sampling clock by using the conventional CR scheme. Especially, when the transmission speed of the CVLC system exploiting RSE is higher, the exposure overlapping effect will be more serious, so that the bit duration would be estimated inaccurately by using the CR scheme. Consequently, the estimated inaccurate bit duration by the CR will result in error propagation in the demodulation processes at the receiver. The corresponding illustration of the error propagation induced by the inaccurate CR is given in Fig. 3. It is seen that there will be an obvious SFO between the recovered clock and the original transmitter clock if the estimated clock is inaccurate. The SFO will increase with the increase in the number of transmitted symbols, and finally cause sampling errors, resulting in error bits during the demodulation processes.
In this work, a simple SR scheme is proposed for SFO mitigation in the CVLC system exploiting RSE. The proposed scheme is based on upsampling and the prior information of the packet structure. Specifically, after synchronization and valid data extraction in the receiver, the proposed scheme can be performed asEq. (1) would be N1⋅N2. Subsequently, the bit decision processing, which is used to recover the logic data 1 and 0, can be expressed asEq. (1) and (2), the D sequence obtained in Eq. (2) can be further processed for BER analysis.
4. Experimental results and discussions
By setting the sampling rate of the FPGA-based transmitter to be 25 KHz and adjusting the illuminance of the RGB-LED to ~2800 lux, the transmission performance of the proposed WDM-based CVLC system exploiting RSE is experimentally characterized. The detailed results are shown in Fig. 4.
Figure 4(a) shows a captured HDR photo in the experiment. By extracting the red/green/blue components of the pixels and then selecting a row of the pixels, i.e., Fig. 4(b), the received signal of the R/G/B channel can be obtained, as shown in Fig. 4(c). And then, the received signals of the three channels can be demodulated simultaneously by using the same demodulation processes. Figures 4(c)-4(g) mainly show the demodulation processes of the received signal in R-channel. As shown in Fig. 4(c), the black curve represents the received signal and the red curve represents the 2-nd order polynomial fitting of the received signal. The fitting curve is parabolic due to the blooming effect, which leads to an uneven distribution of the brightness in the captured HDR photo, and thereby results in an uneven distribution of the received signal. Figure 4(d) shows the pre-processed signal and the 2-nd order polynomial fitting of the pre-processed signal. After preprocessing, apparently, the distribution of the signal becomes relatively flat. After that, the signal is normalized and a fragment of the normalized signal is shown in Fig. 4(e). Meanwhile, by using the duration of the continuous high level as the indicator, the header in the signal can be found easily and then the timing metric can be obtained, as shown in Fig. 4(e). After extraction from the normalized signal, the received data signal of each packet is recovered into a binary logic sequence by using the proposed SR scheme and bit decision scheme. Figure 4(g) shows the recovered data sequence and the transmitted data sequence. Subsequently, decoding and analysis are performed for error counting to evaluate the BER performance of the transmission. For the results shown in Fig. 4, the corresponding BER of the R channel is about 7.81 × 10−4, no error bit occurs in the G channel and B channel. The corresponding data volume of each channel is 0.672 Kbits, hence the aggregate data rate of the WDM CVLC link is 2.016 Kbits/frame.
We further investigate the impact of the sampling rate on the BER performance, while the illuminance is unchanged. The measured BERs versus sampling rates and the measured data rates versus sampling rates are shown in Fig. 5. When the conventional CR scheme is utilized, the BER of the system is relatively high. The BER of the system is still higher than 1 × 10−2, even when the sampling rate is lower than 25 KHz. In contrast, significant BER performance improvement can be achieved by using the proposed SR scheme. As marked in Fig. 5, when the sampling rate is lower than 29.3 KHz, a BER of lower than 3.8 × 10−3 (the HD-FEC limit) can be realized for the proposed WDM CVLC system. Meanwhile, it is seen that the system can achieve a data rate up to 2.38 Kbits/frame when the sampling rate is 29.3 KHz. As the smartphone’s camera used in this work is based on Sony IMX214, which is able to output 13M-pixel HDR at the maximum of 30 frame/s, if continuous shooting or video recording based on real-time HDR mode is used to capture multiple photos continuously, a theoretical data rate of 71.4 Kbits/s can be achieved for the WDM CVLC system using the proposed SR scheme.
In this paper, we have experimentally demonstrated a WDM transmission over a CVLC system exploiting RSE. In addition, a sampling reconstruction scheme is proposed for SFO mitigation. It is showed that the proposed sampling reconstruction scheme exhibits superior BER performance than the conventional clock recovery scheme. Experimental results show that the proposed WDM CVLC system using the sampling reconstruction scheme can achieve a theoretical speed up to 2.38 Kbits/frame, while the BER is below the HD-FEC limit.
Hunan Provincial Innovation Foundation for Postgraduate (CX2017B100); National Natural Science Foundation of China (61377079); National Natural Science Foundation of China (61775054); Science and Technology Project of Hunan Province (2016GK2011).
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