Abstract

We propose a procedure for characterizing fabrication deviations within a chip and among different chips in a wafer in silicon photonics technology. In particular, independent measurements of SOI thickness and waveguide width deviations can be mapped through the wafer, allowing a precise and non-destructive characterization of how these variations are distributed along the surface of the wafer. These deviations are critical for most wavelength-dependent integrated devices, like microring resonators, filters, etc. We also show that the technique allows for the characterization of proximity effects.

© 2016 Optical Society of America

1. Introduction

Silicon photonics is gradually penetrating in the telecom and datacom market, mainly due to its compatibility with CMOS process lines and its scalability. In particular, using silicon-on-insulator technology with thin silicon layers (most typical between 220 and 350 nm thickness), provides very small-size waveguides allowing many devices per mm2 of footprint. However, the sub-micron waveguides associated with this technology have an effective refractive index which is very sensitive to few-nanometer variations in their height and width. This implies that any interferometry-based device, including microring resonators, Mach-Zehnder interferometers (MZIs), arrayed waveguide gratings (AWGs), etc, can have a very variable behavior along the wafer position [1]. For instance, it has been shown that the resonance position of ring resonators can vary more than 5nm along a single wafer [2]. The problem can be alleviated by different strategies, for example by thermally tuning the device [3], which is power-consuming, permanently trimming the device [4], which requires non-standard fabrication procedures, or fabrication-tolerant specific designs [5]. However, for complex interferometric devices, it may be unfeasible to control every single path to optimize performance. For these reasons, a careful characterization of how the fabrication deviations behave along the surface of the wafer is crucial for making a robust optical design.

The most typical techniques used for the estimation of the geometrical variations are critical-dimension scanning electron microscopy (CD-SEM) which can accurately evaluate the width of waveguides, and ellipsometry, which can determine the thickness of the silicon-on-insulator (SOI) layer with good precision [1]. The main drawback of these techniques is that they have to be implemented in the process line during fabrication. In particular ellipsometry measurements can only be performed on the unprocessed wafer, and SEM measurements require uncladded waveguides. In addition, these measurements can only be performed a limited number of times, because they are time-consuming. Once the wafer is processed, diced, and the chips are sent to the client, the user cannot measure these parameters in any specific chip without having to destroy the chip by cleaving it and removing the cladding. Refs [6,7]. show methods for estimating fabrication deviations using ring resonators, but these methods cannot distinguish between height and width errors, which typically have different statistics. Finally, in [8] the authors report a method of characterizing SOI thickness fluctuations by using long Bragg gratings, although the technique requires very specialized characterization tools.

In this paper, we show a simple procedure using two interferometers which can be implemented in the chip at any position, allowing the user to independently measure the waveguide height and width without having to damage the sample.

2. Principle

The main difficulty of waveguide metrology through optical means regards the distinction between height and width deviations, as both parameters have an impact in the effective refractive index. Figure 1 shows how the effective and group index varies with the waveguide width for a height of 220 nm. It is clear that the dependence becomes much weaker for wide waveguides. We have marked with dotted lines two distinct cases, a narrow waveguide which is a single-mode waveguide with 480 nm width, and a wide waveguide which is 1500 nm wide. The latter has an effective index dependence on width which is 30 times lower than the former, as shown in the labels of Fig. 1. This makes wide waveguides much more robust to width deviations than narrow waveguides. However, widths wider than 500 nm yield multimodal behavior. This means that bends can generate undesired higher-order modes (HOMs) [9]. For this reason, wide waveguides can only be implemented in straight sections. Therefore, in order to make an MZI only sensitive to height variations, one needs to replicate in both branches the narrow trajectories and tapers, and leaving the wide waveguides as the only asymmetry in the optical paths. This approach has been employed to make devices more robust to fabrication deviations in waveguide width, in particular for MZIs [10] and AWGs [11]. One example of this MZI is shown in Fig. 2(a).

 figure: Fig. 1

Fig. 1 Calculated effective (blue, solid) and group (red, dashed) index versus waveguide width for a 220nm-high silicon strip waveguide fully surrounded by silica. Green dotted lines mark the selected widths to represent the narrow (480 nm) and wide (1500 nm) waveguides, where slopes are also shown in nm−1 units.

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 figure: Fig. 2

Fig. 2 Sketch of the two elements proposed for the estimations of the fabrication deviations. (a) Widened MZI, sensitive only to height variations; (b) Narrow MZI, sensitive to both width and height. The grey areas are unetched regions which were present in some structures, and can be used as integrated silicon heaters. These were used for the study of proximity effects.

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We propose to use a widened MZI to characterize the waveguide height, as this device is very insensitive to width deviations. In order to estimate the waveguide height, one could extract the effective index from the fringe position of the MZI, although this can be risky, as it requires guessing the fringe order. Instead, we use a more reliable estimation based on the accurate characterization of the free-spectral-range (FSR) of the MZI, which is not subject to any hypothesis on the fringe order [9]. This measurement provides an accurate value of the group index ng of the widened waveguide through this equation:

ΔνFSR=cngΔL
where ΔL is the path difference in the MZI, c is the speed of light in vacuum, and ΔνFSR the FSR of the MZI in frequency units. Once the group index is determined, the SOI height can be estimated from the calculated curve ng(h, w = 1500 nm) through a simple 1D interpolation. Once the SOI thickness has been calculated, one can use a non-widened MZI to estimate the waveguide width. Equation (1) is applied again to extract the group index of the narrow waveguide, but now we know the SOI thickness from the widened MZI. As the local variability of the SOI thickness is low (∼1nm along 10 mm distance [1]), setting both wide and narrow MZIs at a close distance would yield a negligible SOI thickness variation. If we expand the dependence of the group index on the width and height to the first order, we can apply the following equation:
Δng=ngwΔw+nghΔh
where Δng, Δw, and Δh are respectively the variations of group index, waveguide width and waveguide height with respect to the nominal values. As now Δh is known from the wide waveguide, Δw can be easily calculated.

2. Fabrication and experiment

The structures were fabricated at CEA-LETI on 8-inch SOI wafers using CMOS fabrication lines [12]. The silicon structure is sandwiched between a thick SiO2 buried oxide (BOX) layer and a thinner SiO2 chemical vapor deposition (CVD) cladding. The silicon layer was patterned by a reactive-ion-etching (RIE) step after deep-UV 193 nm optical lithography printing. Many repetitions of the structures shown in Fig. 2 were introduced for different values of ΔL (most cases 172μm, with some instances with 86 and 344 μm), heater gap distances (no heater and heater gap distance of 0.5, 0.75 and 1 μm). The input and output ports were connected to grating couplers for coupling to single-mode fibers. 2 × 2 multimode interferometer (MMI) couplers were used in all the MZIs. In this kind of MZIs, the cross port is more insensitive to MMI imperfections than the bar port, therefore the cross port was used for the fringe measurements.

The fringe pattern of the MZI was measured with a tunable laser between 1530 and 1590 nm with 20 pm resolution. In order to reduce the noise in the FSR calculation, the curves were smoothed with a 20-point averaging window. The FSR was extracted by calculating the distance between consecutive crossing points with the 10% transmission point, between 1535 and 1565 nm. These measurements were performed in 10 different chips along the surface of the wafer.

3. Results and discussion

Figure 3(a) shows the cross-port transmission spectrum of a widened MZI, while Fig. 3(b) shows the extracted group indices of all the samples measured (wide and narrow) for 10 different chips. Values around 3.76 correspond to widened MZIs, while values around 4.28 correspond to narrow MZIs. However, it is clear that the variations within a die and from die-to-die are very different. Wide MZIs show very small variability, while narrow MZIs show larger intra and inter-die variations. This means that the impact of width variations is dominant with respect to height variations in SOI thickness.

 figure: Fig. 3

Fig. 3 (a) Example of MZI measured spectrum of a wide MZI. (b) Group index extracted from the measured FSR for different dice. Values around 3.76 correspond to wide MZIs [Fig. 2(a)], and values around 4.28, to narrow MZIs [Fig. 2(b)]. (c) Wafer map identifying the chips along the wafer surface. From (b) it is clear that widened MZIs are much more stable than narrow MZIs. Apart from a higher die-to-die variation, there are also intra-die patterns due to proximity effects.

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Following the procedure described previously, we first extracted the SOI thickness from the widened-MZI data. The results are shown in detail in Fig. 4. As the actual SOI thickness estimation strongly depends on the silicon model used, the estimation requires a calibration. Our initial silicon model yielded SOI thicknesses with an offset of 3.5 nm with respect to the ellipsometry estimations. To calibrate our metrology, an offset of 0.0045 in the refractive index of silicon was introduced to fit the SOI thickness with the ellipsometry values (shown as dashed lines in Fig. 4(a)). The final values for the refractive index of bulk silicon at 1552 nm were 3.4835 for the effective index and 3.6155 for the group index. With these values, all three ellipsometry measurements fit with the estimations from MZIs.

 figure: Fig. 4

Fig. 4 (a) SOI thickness extracted from group index of wide MZIs. Dashed lines show ellipsometry measurements in three of the chips. (b) Map of SOI thickness along the wafer extracted from the chips, averaging the values within each chip.

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Averaging the SOI thickness for each chip, we have mapped how this number varies along the surface of the wafer, which is shown in Fig. 4(b). A radial pattern is clearly appreciated, which confirms that the ng estimations are showing a real physical effect, and are not the result of noise. If one looks at the variability within a chip, we see no clear patterns, meaning that the variability of the SOI thickness within a single chip is too small to be measured with this system. σ values in every chip were smaller than 1 nm, which yields an approximate uncertainty of ± 1 nm in the SOI thickness estimation.

Taking the SOI results from the widened MZIs, we have estimated the widths of the waveguides using the narrow MZIs shown in Fig. 2(b) and Eq. (2). The result is shown in Fig. 5. In this case, not only is there a strong die-to-die variation, but there is also a clear pattern in the data. Each die has 4 narrow MZI samples. The first one is an isolated waveguide, i.e. with no heater (shown as dots in Fig. 5(a)); the other three points represent MZIs with heaters with decreasing gap distance, with values 1, 0.75 and 0.5 μm (shown as triangles). Mapping the isolated waveguide width along the wafer also shows a strong radial pattern, as shown in Fig. 5(b). On the other hand, Fig. 5(c) shows the results of SEM metrology of the waveguide width on 400 nm-wide waveguides (deviations with respect to 400 nm). Although the SEM metrology was not performed on the same chips as the optical metrology, we can compare the trends along the wafer, and it is clear that both techniques show width deviations of −30 nm in the central part of the wafer, which decrease towards the edges of the wafer down to ∼-15 nm. This agreement between both techniques demonstrates the validity of the procedure.

 figure: Fig. 5

Fig. 5 (a) Waveguide widths estimated from narrow MZIs and the SOI values shown in Fig. 4. The four samples shown for each die correspond, in this order, to the isolated waveguide (dots), and waveguide with heaters at distances of 1, 0.75 and 0.5μm (triangles). (b) Mapping of the isolated waveguide width along the surface of the wafer. (c) CD-SEM metrology results provided by the fabrication foundry.

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This procedure also allows us to accurately measure proximity effects due to heaters at both sides of the waveguide. The pattern shown in Fig. 5(a) clearly shows that waveguides with heaters are narrower than waveguides without. However, it is worth noting that, as shown in Fig. 2(b), MZIs with heaters only have them along half of their trajectory; but Eq. (1) considers an homogeneous path difference. This means that the group index extracted with Eq. (1) estimates an arithmetic mean midway between with and without heater. Therefore, in order to extract the width of the segment with heater, we have to multiply by two the variation with respect to the isolated waveguides. That is what we did to generate Fig. 6(a) from Fig. 5(a) for every measured chip. These results show that most of the chips undergo a narrowing between 8 and 10 nm when heaters are situated at 500 nm at both sides. Figure 6(b) shows an SEM micrograph showing a waveguide with and without heater, where a narrowing effect of ∼9nm is observed, which agrees with the metrology from MZIs. A narrowing of waveguides due to proximity is in agreement with previous observations too [13].

 figure: Fig. 6

Fig. 6 Proximity effects. (a) Width variation of waveguide with heater vs. isolated, for different proximity gaps. Different curves represent 10 different chips, corresponding to the ones shown in Fig. 5(a) with the same colors. (b) SEM micrograph showing a 9-nm variation in width for a nominal proximity gap of 500 nm.

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4. Conclusion

We propose a technique for measuring fabrication deviations in waveguide width and height by using two types of Mach-Zehnder interferometers with different widths. The technique can distinguish between both sources of fabrication deviations, and in addition, can also be used to quantify proximity effects in the waveguide width when adjacent heaters are present. This allows the user to be able to non-destructively measure these quantities in any chip without needing a prior specific characterization along the process line.

Acknowledgments

The authors acknowledge financial support from the European Union’s Seventh Framework Programme (FP7/2007-2013) under grant agreement number 619194 (project IRIS).

References and links

1. S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010). [CrossRef]  

2. C. Chauveau, P. Labeye, J. M. Fedeli, S. Blaize, and G. Lerondel, “Study of the uniformity of 300mm wafer through ring-resonator analysis,” IEEE International Conference on Photonics in Switching (PS), 1–3, (2012).

3. P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010). [CrossRef]   [PubMed]  

4. A. Canciamilla, S. Grillanda, F. Morichetti, C. Ferrari, J. Hu, J. D. Musgraves, K. Richardson, A. Agarwal, L. C. Kimerling, and A. Melloni, “Photo-induced trimming of coupled ring-resonator filters and delay lines in As2S3 chalcogenide glass,” Opt. Lett. 36(20), 4002–4004 (2011). [CrossRef]   [PubMed]  

5. S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photonics Technol. Lett. 27(8), 871–874 (2015). [CrossRef]  

6. M. Mancinelli, M. Borghi, P. Bettotti, J. M. Fedeli, and L. Pavesi, “An all optical method for fabrication error measurements in integrated photonic circuits,” J. Lightwave Technol. 31(14), 2340–2346 (2013). [CrossRef]  

7. L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in 2014 Optical Fiber Communication Conference (OSA, 2014), paper Th2A–37.

8. N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SoI wafer metrology,” IEEE Photonics Technol. Lett. 27(7), 755–758 (2015). [CrossRef]  

9. E. Dulkeith, F. Xia, L. Schares, W. M. J. Green, and Y. A. Vlasov, “Group index and group velocity dispersion in silicon-on-insulator photonic wires,” Opt. Express 14(9), 3853–3863 (2006). [CrossRef]   [PubMed]  

10. F. Horst, W. M. J. Green, S. Assefa, S. M. Shank, Y. A. Vlasov, and B. J. Offrein, “Cascaded Mach-Zehnder wavelength filters in silicon photonics for low loss and flat pass-band WDM (de-)multiplexing,” Opt. Express 21(10), 11652–11658 (2013). [CrossRef]   [PubMed]  

11. W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006). [CrossRef]  

12. J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proc. SPIE 6125, 61250H (2006). [CrossRef]  

13. P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004). [CrossRef]  

References

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  1. S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
    [Crossref]
  2. C. Chauveau, P. Labeye, J. M. Fedeli, S. Blaize, and G. Lerondel, “Study of the uniformity of 300mm wafer through ring-resonator analysis,” IEEE International Conference on Photonics in Switching (PS), 1–3, (2012).
  3. P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010).
    [Crossref] [PubMed]
  4. A. Canciamilla, S. Grillanda, F. Morichetti, C. Ferrari, J. Hu, J. D. Musgraves, K. Richardson, A. Agarwal, L. C. Kimerling, and A. Melloni, “Photo-induced trimming of coupled ring-resonator filters and delay lines in As2S3 chalcogenide glass,” Opt. Lett. 36(20), 4002–4004 (2011).
    [Crossref] [PubMed]
  5. S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photonics Technol. Lett. 27(8), 871–874 (2015).
    [Crossref]
  6. M. Mancinelli, M. Borghi, P. Bettotti, J. M. Fedeli, and L. Pavesi, “An all optical method for fabrication error measurements in integrated photonic circuits,” J. Lightwave Technol. 31(14), 2340–2346 (2013).
    [Crossref]
  7. L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in 2014 Optical Fiber Communication Conference (OSA, 2014), paper Th2A–37.
  8. N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SoI wafer metrology,” IEEE Photonics Technol. Lett. 27(7), 755–758 (2015).
    [Crossref]
  9. E. Dulkeith, F. Xia, L. Schares, W. M. J. Green, and Y. A. Vlasov, “Group index and group velocity dispersion in silicon-on-insulator photonic wires,” Opt. Express 14(9), 3853–3863 (2006).
    [Crossref] [PubMed]
  10. F. Horst, W. M. J. Green, S. Assefa, S. M. Shank, Y. A. Vlasov, and B. J. Offrein, “Cascaded Mach-Zehnder wavelength filters in silicon photonics for low loss and flat pass-band WDM (de-)multiplexing,” Opt. Express 21(10), 11652–11658 (2013).
    [Crossref] [PubMed]
  11. W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
    [Crossref]
  12. J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proc. SPIE 6125, 61250H (2006).
    [Crossref]
  13. P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
    [Crossref]

2015 (2)

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photonics Technol. Lett. 27(8), 871–874 (2015).
[Crossref]

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SoI wafer metrology,” IEEE Photonics Technol. Lett. 27(7), 755–758 (2015).
[Crossref]

2013 (2)

2011 (1)

2010 (2)

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010).
[Crossref] [PubMed]

2006 (3)

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proc. SPIE 6125, 61250H (2006).
[Crossref]

E. Dulkeith, F. Xia, L. Schares, W. M. J. Green, and Y. A. Vlasov, “Group index and group velocity dispersion in silicon-on-insulator photonic wires,” Opt. Express 14(9), 3853–3863 (2006).
[Crossref] [PubMed]

2004 (1)

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Agarwal, A.

Asghari, M.

Assefa, S.

Ayotte, N.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SoI wafer metrology,” IEEE Photonics Technol. Lett. 27(7), 755–758 (2015).
[Crossref]

Baets, R.

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Baets, R. G.

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

Beckx, S.

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Bettotti, P.

Bientsman, P.

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Blaize, S.

C. Chauveau, P. Labeye, J. M. Fedeli, S. Blaize, and G. Lerondel, “Study of the uniformity of 300mm wafer through ring-resonator analysis,” IEEE International Conference on Photonics in Switching (PS), 1–3, (2012).

Bogaerts, W.

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photonics Technol. Lett. 27(8), 871–874 (2015).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Borghi, M.

Canciamilla, A.

Chauveau, C.

C. Chauveau, P. Labeye, J. M. Fedeli, S. Blaize, and G. Lerondel, “Study of the uniformity of 300mm wafer through ring-resonator analysis,” IEEE International Conference on Photonics in Switching (PS), 1–3, (2012).

Cunningham, J. E.

D’heer, H.

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photonics Technol. Lett. 27(8), 871–874 (2015).
[Crossref]

Dong, P.

Dulkeith, E.

Dumon, P.

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Dwivedi, S.

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photonics Technol. Lett. 27(8), 871–874 (2015).
[Crossref]

Fedeli, J. M.

M. Mancinelli, M. Borghi, P. Bettotti, J. M. Fedeli, and L. Pavesi, “An all optical method for fabrication error measurements in integrated photonic circuits,” J. Lightwave Technol. 31(14), 2340–2346 (2013).
[Crossref]

J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proc. SPIE 6125, 61250H (2006).
[Crossref]

C. Chauveau, P. Labeye, J. M. Fedeli, S. Blaize, and G. Lerondel, “Study of the uniformity of 300mm wafer through ring-resonator analysis,” IEEE International Conference on Photonics in Switching (PS), 1–3, (2012).

Feng, D.

Ferrari, C.

Green, W. M. J.

Grillanda, S.

Horst, F.

Hu, J.

Jaenen, P.

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

Kimerling, L. C.

Krishnamoorthy, A. V.

Labeye, P.

C. Chauveau, P. Labeye, J. M. Fedeli, S. Blaize, and G. Lerondel, “Study of the uniformity of 300mm wafer through ring-resonator analysis,” IEEE International Conference on Photonics in Switching (PS), 1–3, (2012).

LaRochelle, S.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SoI wafer metrology,” IEEE Photonics Technol. Lett. 27(7), 755–758 (2015).
[Crossref]

Lerondel, G.

C. Chauveau, P. Labeye, J. M. Fedeli, S. Blaize, and G. Lerondel, “Study of the uniformity of 300mm wafer through ring-resonator analysis,” IEEE International Conference on Photonics in Switching (PS), 1–3, (2012).

Li, G.

Liang, H.

Luyssaert, B.

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Mancinelli, M.

Melloni, A.

Morichetti, F.

Musgraves, J. D.

Offrein, B. J.

Orobtchouk, R.

J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proc. SPIE 6125, 61250H (2006).
[Crossref]

Pavesi, L.

Qian, W.

Richardson, K.

Schares, L.

Seassal, C.

J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proc. SPIE 6125, 61250H (2006).
[Crossref]

Selvaraja, S. K.

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

Shafiiha, R.

Shank, S. M.

Simard, A. D.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SoI wafer metrology,” IEEE Photonics Technol. Lett. 27(7), 755–758 (2015).
[Crossref]

Taillaert, D.

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Thourhout, D. V.

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

Van Campenhout, J.

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Van Thourhout, D.

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Vivien, L.

J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proc. SPIE 6125, 61250H (2006).
[Crossref]

Vlasov, Y. A.

Wiaux, V.

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Wouters, J.

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

Xia, F.

IEEE J. Sel. Top. Quantum Electron. (2)

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

W. Bogaerts, P. Dumon, D. V. Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. G. Baets, “Compact wavelength-selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006).
[Crossref]

IEEE Photonics Technol. Lett. (3)

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bientsman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photonics Technol. Lett. 16(5), 1328–1330 (2004).
[Crossref]

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photonics Technol. Lett. 27(8), 871–874 (2015).
[Crossref]

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SoI wafer metrology,” IEEE Photonics Technol. Lett. 27(7), 755–758 (2015).
[Crossref]

J. Lightwave Technol. (1)

Opt. Express (3)

Opt. Lett. (1)

Proc. SPIE (1)

J. M. Fedeli, R. Orobtchouk, C. Seassal, and L. Vivien, “Integration issues of a photonic layer on top of a CMOS circuit,” Proc. SPIE 6125, 61250H (2006).
[Crossref]

Other (2)

C. Chauveau, P. Labeye, J. M. Fedeli, S. Blaize, and G. Lerondel, “Study of the uniformity of 300mm wafer through ring-resonator analysis,” IEEE International Conference on Photonics in Switching (PS), 1–3, (2012).

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in 2014 Optical Fiber Communication Conference (OSA, 2014), paper Th2A–37.

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Figures (6)

Fig. 1
Fig. 1 Calculated effective (blue, solid) and group (red, dashed) index versus waveguide width for a 220nm-high silicon strip waveguide fully surrounded by silica. Green dotted lines mark the selected widths to represent the narrow (480 nm) and wide (1500 nm) waveguides, where slopes are also shown in nm−1 units.
Fig. 2
Fig. 2 Sketch of the two elements proposed for the estimations of the fabrication deviations. (a) Widened MZI, sensitive only to height variations; (b) Narrow MZI, sensitive to both width and height. The grey areas are unetched regions which were present in some structures, and can be used as integrated silicon heaters. These were used for the study of proximity effects.
Fig. 3
Fig. 3 (a) Example of MZI measured spectrum of a wide MZI. (b) Group index extracted from the measured FSR for different dice. Values around 3.76 correspond to wide MZIs [Fig. 2(a)], and values around 4.28, to narrow MZIs [Fig. 2(b)]. (c) Wafer map identifying the chips along the wafer surface. From (b) it is clear that widened MZIs are much more stable than narrow MZIs. Apart from a higher die-to-die variation, there are also intra-die patterns due to proximity effects.
Fig. 4
Fig. 4 (a) SOI thickness extracted from group index of wide MZIs. Dashed lines show ellipsometry measurements in three of the chips. (b) Map of SOI thickness along the wafer extracted from the chips, averaging the values within each chip.
Fig. 5
Fig. 5 (a) Waveguide widths estimated from narrow MZIs and the SOI values shown in Fig. 4. The four samples shown for each die correspond, in this order, to the isolated waveguide (dots), and waveguide with heaters at distances of 1, 0.75 and 0.5μm (triangles). (b) Mapping of the isolated waveguide width along the surface of the wafer. (c) CD-SEM metrology results provided by the fabrication foundry.
Fig. 6
Fig. 6 Proximity effects. (a) Width variation of waveguide with heater vs. isolated, for different proximity gaps. Different curves represent 10 different chips, corresponding to the ones shown in Fig. 5(a) with the same colors. (b) SEM micrograph showing a 9-nm variation in width for a nominal proximity gap of 500 nm.

Equations (2)

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Δ ν FSR = c n g ΔL
Δ n g = n g w Δw+ n g h Δh

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