The switching and routing is essential for an advanced and reconfigurable optical network, and great efforts have been done for traditional single-mode system. We propose and demonstrate an on-chip switch compatible with mode-division multiplexing system. By controlling the induced phase difference, the functionalities of dynamically routing data channels can be achieved. The proposed switch is experimentally demonstrated with low insertion loss of ~1 dB and high extinction ratio of ~20 dB over the C-band for OFF-ON switchover. For further demonstration, the non-return-to-zero on-off keying signals at 10 Gb/s carried on the two spatial modes are successfully processed. Open and clear eye diagrams can be observed and the bit error rate measurements indicate a good data routing performance.
© 2016 Optical Society of America
To satisfy the rapidly increasing demands on high-speed data transfer for cloud computing and data-intensive applications, silicon photonic interconnects have attracted wide attentions as a promising candidate for the next-generation platform alleviating the communication bottleneck and unfavorable power scaling [1–3]. Great strides have been made in photonic interconnects for single-mode optical networks, based on a wide range of technologies. Recently, the mode-division multiplexing (MDM) transmission, where multiple spatial modes can be simultaneously used to increase the capacity of a single wavelength link, has been exclusively investigated. On top of the basic mode multiplexer/demultiplexer (MUX/DEMUX), some other components widely used in single-mode optical networks such as power splitter, filter and bend waveguide had been proposed and redesigned to accommodate high-order modes [4–6]. To realize a complete and flexible MDM optical network, the switching and routing for different data channels are indispensable functionalities. It is promising to enable data routing between processor and memory for future on-chip multiprocessors systems [7–13]. Up to now, only a few switching schemes have been proposed for MDM networks. In , several mode DEMUXs are utilized and each mode is demultiplexed to fundamental mode first, and then processed separately, making the whole switch complicated and power consumption increased.
In this paper, an on-chip switch suitable for MDM optical network based on the silicon-on insulator (SOI) platform is proposed and experimentally demonstrated. The two-mode multiplexed signals can be processed simultaneously, and the output signals are both on fundamental mode, which is easy for detection and subsequent processing. The proposed device consists of a symmetric Y-junction, a phase shifter and an adiabatic splitter. By controlling the phase difference induced by the phase shifter, the data information carried on two input modes can be optionally routed to different outputs. The measured eye diagrams validate the successful routing of the proposed device. Quantitative characterization by bit error rate (BER) measurement is also carried out with a reasonable power penalty of < 1.5 dB.
2. Operation principle and simulation
The proposed switch is schematically presented in Fig. 1(a). The symmetric Y-junction, which is widely used in various photonics integrated circuits due to compact size and wavelength-independence [15, 16], serves as a 3 dB power splitter. The adiabatic splitter serves as a 2 × 2 power splitter . Two waveguides and a phase shifter are adopted to connect the Y-junction and the adiabatic splitter, forming a Mach-Zehnder interferometer (MZI) structure. The micro ring resonator (MRR) based mode MUX  is utilized to generate the multiplexed signals. The signals can be optionally routed to the branches of the adiabatic splitter when switching to “OFF” or “ON” state, as shown in Fig. 1(b).
Figure 2(a) exhibits the top view of the symmetric Y-junction, the branch of which supports only single mode and the stem supports both even (fundamental transverse electric, TE0) and odd (first-order transverse electric, TE1) modes. The two branches are placed close to each other, forming a system supporting supermodes (the eigenmode of structure consisting of serval separate waveguides with a large amount of power in the multiple waveguides) defined as S0 and S1. The supermode will be split into serval conventional modes when the gap is big enough. The working mechanism is shown in Fig. 2(b). The input TE0 mode in the stem of Y-junction evolves first into the S0 mode and then split equally into two in-phase TE0 modes with the increasing gap between two branches . Similarly, the TE1 mode first evolves into S1 mode, and then splits equally into two antiphase parts, both on TE0 modes. The simulated electric distributions using bidirectional eigenmode expansion method are shown in Fig. 2(c). The inserts exhibit the mode profiles at different sections calculated by the finite difference algorithm. Figure 2(d) exhibits the schematic drawing of the adiabatic splitter, which consists of two separate waveguides placed close to each other in the same plane. For simulation convenience, its input and output ports are exchanged here, compared with the schematic in Fig. 1. The two waveguides are firstly designed with different widths and large gap to avoid unwanted interference. Then, they are tapered to the same width with the gap decreasing gradually to form a strong coupling zone. The adiabatically tapering is expected to ensure that the supermode can be only selectively excited by a TE0 mode. Finally, the two waveguides are pulled away to achieve decoupling, and the widths keep unchanged to make the power evenly split into the two waveguides. The effective indices of two guided modes of the coupling system are calculated as a function of the propagation position in adiabatic couplers, as shown in Fig. 2(e). The TE0 mode in the wide (narrow) waveguide adiabatically evolves into the S0 (S1) mode due to the closely matched effective index.
The proposed device is designed on SOI platform with 220 nm top silicon. For the Y-junction, the widths of the branch and stem parts are 0.4 and 0.8 μm, while the branch length is 5 μm. Note that the waveguides with 130 nm ridge height are adopted to reduce the reflection at the junction of the two branches. For the adiabatic splitters, the two waveguides are linearly tapered from 0.5 and 0.3 μm to 0.4 μm, respectively. The gap between the two waveguides decreases from 1 μm to G along the coupling length L. It increases back to 1 μm within a length of 10 μm. The crosstalk for the TE0 to S0 mode as a function of the coupling length L are calculated and shown in Fig. 3(a), under three different gaps (G = 150, 200, 250 nm) at 1550 nm. Here the crosstalk is defined as the power ratio of the output S0 to the TE0 mode injected from the narrow input waveguide. It can be seen that the crosstalk decreases with the reduction of gap G, for a fixed length. On the other hand, the crosstalk can be very low when L is designed to be larger than 150 μm. Same results can be also attained for the case of light launching from the wide waveguide. In our design, G = 200 nm and L = 180 μm are utilized, making a tradeoff between crosstalk performance and footprint. The simulated electric field distributions using these preferences are presented in Fig. 3(b). At the “OFF” state, the input TE0 and TE1 modes are converted to S0 and S1 modes with mode symmetry unchanged. The S0 and S1 modes are then transferred to wide and narrow output waveguides, respectively. At the “ON” state, a π phase shifting is induced by the phase shifter. Thus, the input TE0 is first split into two parts with same phase, which are then combined into the S1 mode after the phase shifter and routed to narrow waveguide. By contrast, the two parts from input TE1 mode have the same phase after the phase shifter, and they are combined and transferred to the wide waveguide. Thus, the data carried on the two modes can be routed to different outputs dynamically. To be noted, the output signals can be resorted to higher mode if necessary, as demonstrated in . Spectral responses of the proposed switch for both “OFF” and “ON” states are calculated over the C-band (1530-1565 nm), as shown in Fig. 3(c). The insertion loss less than 0.5 dB can be obtained and the crosstalk is as low as −28 dB for both “OFF” and “ON” states. As a result, the extinction ratio (ER) is as high as ~28 dB, guaranteeing a good routing performance of the proposed device.
3. Device fabrication and experimental results
The proposed switch was fabricated by the 248 nm deep ultraviolet lithography and inductively coupled plasma (ICP) etching. The microscope image of the fabricated device is shown in Fig. 4(a). Figures 4(b)-4(d) exhibit the zoom-in views of MRR-based mode MUX and switch. An integrated TiN heater is deposited on the top of one arm of the MZI to induce the phase difference. The SiO2 cladding is utilized to cover the entire device, forming a buffer layer between the metal heater and the waveguide.
The measured transmission spectra of the fabricated device are illustrated in Figs. 5(a)-5(d). The spectra have been normalized by deducting the loss caused by the couplers. We define 1-3/2-4 paths as the bar-paths, and 2-3/1-4 as the cross-paths for representation convenience. The legend indicates the input and output ports under switching setting, e.g., “1-3 (OFF)” refers to the transmission from port 1 to 3 at the “OFF” state. For the bar-paths, the insertion loss for the whole device (including MUX and switch) is ~2 dB over C-band at the “OFF” state, while it decreases to ~-22 dB at the “ON” state. Similarly, for the cross-paths, a low insertion loss of ~1 dB for the cross-paths is obtained at the “ON” state, while it decreases to ~-21 dB when switching to the “OFF” state. As a result, the ER is as high as 20 dB, indicating the switching functionalities work with a low crosstalk. Compared with the calculated spectral responses in Fig. 3(c), the ER degradation mainly results from the imperfect fabrication of the Y-junction. Note the nonlinear crosstalk can be ignored even if simultaneous two modes operation were performed, thanks to the moderate input power (< 10 dBm) and coupling length (< 300 μm). In order to accurately evaluate the proposed switch, a reference structure comprising only mode MUX and DEMUX with same parameters is fabricated and characterized on the same chip. The ER of mode MUX is measured to be ~28 dB over the C-band, which is higher than that of the whole device, ensuring the actual ER of the proposed switch will not be limited by the MUX. The proposed switch possesses very low insertion loss (< 1 dB) for both TE0 and TE1 inputs, subtracting the loss induced by the MUX. The heating power is zero in the “OFF” state, and no obvious phase errors between two branches are found since the upper and lower arms are symmetrical. The heating power is 40.5 mW when switching to the “ON” state. The measured switching time is ~50 µs.
The modulated signal at 10 Gb/s is used to further test the proposed device, and the experimental setup is shown in Fig. 6(a). A CW light at 1550.85 nm is launched into the Mach-Zehnder modulator (MZM) driven by the non-return-to-zero signal (231-1 pseudo-random binary sequences) from the bit pattern generator (BPG). The polarization state of input signal is optimized by the polarization controller (PC) to achieve a maximum coupling efficiency through the grating coupler. After coupling out of the chip, the processed signal is amplified by the erbium-doped fiber amplifier (EDFA) and attenuated by the attenuator (ATT). A band pass filter (BPF) is utilized for reducing the ASE noise, and a communication signal analyzer (CSA) as well as an error analyzer (EA) are used to monitor the output signals. The eye diagrams from ports 3 and 4 for both “OFF” and “ON” states are measured and shown in Fig. 6(b), with only one input port injected at a time. This is reasonable thanks to the large ER. For the bar-paths, clear and open eye diagrams at the “OFF” state can be observed, while signals can be barely detected when switching to the “ON” state. Similarly, clear and open eye diagrams can be obtained for the cross-paths at the “ON” state, while signals can be barely detected when switching to the “OFF” state. These results indicate a good routing performance of the proposed device. The different rising and falling time of the eye diagrams mainly results from the limited bandwidth (the FWHM ~9.5 GHz) of the MRR. Part of spectral side lobes is filtered out by the MRR. Finally, the BER measurements are performed, and the results are plotted in Fig. 6(c), showing ~1.5 dB power penalty for the paths of inputting from port 1, and ~0.5 dB for the paths of inputting from port 2. Higher penalty for the paths of inputting from port 2 can be attributed to the higher insertion loss induced by the MRR, which leads to a larger optical signal to noise ratio (OSNR) degradation while amplifying by the post-chip EDFA. The power penalties are referenced to a back-to-back (B2B) case, which is measured by replacing the chip with a tunable ATT.
In summary, we have proposed and fabricated a dynamical switch for reconfigurable mode-multiplexing optical network based on SOI platform. The input signal can be dynamically routed to the different outputs by tuning the phase shifter in a MZI structure. The measured insertion loss and ER are ~1 dB and ~20 dB over C-band for OFF-ON switchover, respectively. Open and clear eye diagrams can be observed and the BER results show ~1.5 dB power penalty for the paths of inputting from port 1, and ~0.5 dB for the paths of inputting from port 2. The proposed switch can be applied for on-chip interconnection, for instance at the receiver side where several users/detectors are expecting data from different modes.
This work was supported by the National Natural Science Foundation of China (Grant No. 61475050 and 61275072), the New Century Excellent Talent Project in Ministry of Education of China (NCET-13-0240), and the Foundation for Innovative Research Groups of the Natural Science Foundation of Hubei Province (2014CFA004).
References and Links
1. A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008). [CrossRef]
2. D. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]
3. R. Ho, K. W. Mai, and M. A. Horowitz, “The future of wires,” Proc. IEEE 89(4), 490–504 (2001). [CrossRef]
5. X. Guan, Y. Ding, and L. H. Frandsen, “Ultra-compact broadband higher order-mode pass filter fabricated in a silicon waveguide for multimode photonics,” Opt. Lett. 40(16), 3893–3896 (2015). [CrossRef] [PubMed]
7. A. W. Poon, X. S. Luo, F. Xu, and H. Chen, “Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection,” Proc. IEEE 97(7), 1216–1238 (2009). [CrossRef]
8. Q. Li, D. Nikolova, D. Calhoun, Y. Liu, R. Ding, T. Baehr-Jones, and K. Bergman, “Single Microring-Based Silicon Photonic Crossbar Switches,” IEEE Photonics Technol. Lett. 27(18), 1981–1984 (2015). [CrossRef]
10. K. Suzuki, K. Tanizawa, T. Matsukawa, G. Cong, S.-H. Kim, S. Suda, M. Ohno, T. Chiba, H. Tadokoro, M. Yanagihara, Y. Igarashi, M. Masahara, S. Namiki, and H. Kawashima, “Ultra-compact 8 × 8 strictly-non-blocking Si-wire PILOSS switch,” Opt. Express 22(4), 3887–3894 (2014). [CrossRef] [PubMed]
11. K. Tanizawa, K. Suzuki, M. Toyama, M. Ohtsuka, N. Yokoyama, K. Matsumaro, M. Seki, K. Koshino, T. Sugaya, S. Suda, G. Cong, T. Kimura, K. Ikeda, S. Namiki, and H. Kawashima, “Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer,” Opt. Express 23(13), 17599–17606 (2015). [CrossRef] [PubMed]
12. L. Lu, S. Zhao, L. Zhou, D. Li, Z. Li, M. Wang, X. Li, and J. Chen, “16 × 16 non-blocking silicon optical switch based on electro-optic Mach-Zehnder interferometers,” Opt. Express 24(9), 9295–9307 (2016). [CrossRef] [PubMed]
13. Z. Li, L. Zhou, L. Lu, S. Zhao, D. Li, and J. Chen, “4× 4 nonblocking optical switch fabric based on cascaded multimode interferometers,” Photonics Res. 4(1), 21–26 (2016). [CrossRef]
14. B. Stern, X. Zhu, C. Chen, L. Tzuang, J. Cardenas, K. Bergman, and M. Lipson, “On-chip mode-division multiplexing switch,” Optica 2(6), 530–535 (2015). [CrossRef]
15. W. Hung, H. Chan, and P. Chung, “Novel design of wide-angle single-mode symmetric Y-junctions,” Electron. Lett. 24(18), 1184–1185 (1988). [CrossRef]
16. J. Love and N. Riesen, “Single-, Few-, and Multimode Y-Junctions,” J. Lightwave Technol. 30(3), 304–309 (2012). [CrossRef]
17. J. Xing, K. Xiong, H. Xu, Z. Li, X. Xiao, J. Yu, and Y. Yu, “Silicon-on-insulator-based adiabatic splitter with simultaneous tapering of velocity and coupling,” Opt. Lett. 38(13), 2221–2223 (2013). [CrossRef] [PubMed]
18. M. Ye, Y. Yu, G. Chen, Y. Luo, and X. Zhang, “On-chip WDM mode-division multiplexing interconnection with optional demodulation function,” Opt. Express 23(25), 32130–32138 (2015). [CrossRef] [PubMed]