Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.
© 2015 Optical Society of America
The requirements for package-to-package input-output (I/O) interfaces in future high performance computing systems scale up to multiple of Tb/s as defined by the International Technology Roadmap for Semiconductors (ITRS) and further detailed by D. Miller  and A. Krishnamoorthy . The traditional scaling of I/O’s using electrical links for data transmission faces many bottlenecks such as pin count and bandwidth-distance-power trade-off. In the past decades optical fibers have gradually replaced electrical wires from transoceanic cables to fiber-to-the-home and data centers rack-to-rack cables, exploiting the very wide bandwidth and low loss of optical fibers. Today’s technology developments focus on implementing “in-package” optical solution with a direct interface to CMOS chips by using arrays of directly modulated lasers and surface illuminated photo-detectors  or integrated silicon photonics compact modulators and waveguide photo-detectors .
In this paper we present our progress towards the realization of multi-Tb/s optical links using silicon photonics circuits. We will first propose a multiplexing architecture to realize very-high bandwidth density. The realization of the key building blocks in an integrated fabrication platform will then be described, followed by a study of the optical devices performance variability.
2. Multiplexing architecture using compact silicon photonics circuits
Various multiplexing approaches are pursued in optical communication to increase the number of bits per second transmitted per physical line without increasing the individual channel data rate: primarily pulse amplitude modulation (PAM), phase shift keying modulation (PSK) , wavelength division multiplexing (WDM) and space division multiplexing (SDM) using multicore fibers. Because of the expected electronics complexity required for PAM or PSK (forward error correction and digital signal processing) making them less favorable for direct interfacing with CMOS, we have selected a combination of WDM and SDM as a multiplexing strategy.
Following a similar approach as in , a possible optical architecture is proposed as depicted in Fig. 1. The transmitter is based on a dense WDM continuous wave (cw) laser source, feeding multiple arrays of micro-ring resonator (MRR) modulators . Each MRR modulator in one array modulates only one channel of the WDM laser source by tuning its operating wavelength with an integrated heater. Each transmitter array ends with a chip-to-fiber coupler, organized in a two dimensional hexagonal array to interface with a single multi-core fiber to combine WDM and SDM. An example of such compact chip-to-fiber assembly was demonstrated in  with a pitch reducing optical fiber array (PROFA) down to a pitch of 40μm.
The receiver couples the light from the multicore fiber onto the silicon photonics chip by the mean of an array of polarization splitting grating couplers . Each output waveguide of these couplers connects to an array of MRR wavelength filters where each pair of filters drops the same selected wavelength onto a common waveguide-based germanium photo-detectors (Ge WPD). Each filter is tuned with its own integrated heater but all heaters are controlled with a common feedback loop and common heater current.
Assuming eight wavelength channels, a PROFA fiber of sixty-one cores (two cores are used for active alignment and cannot be used for data transmission) and a link data rate of 28Gbps, such an architecture can achieve an aggregate bandwidth of 13.2Tb/s. Each core data eight-channel link transmit/receive unit occupies an area of less than 134,400μm2, when assuming a micro-bump pitch of 40μm. Hence the aggregate bandwidth of 13.2Tb/s is realized in an area of 7.93mm2 with an additional area of 0.32mm2 to support the PROFA fiber coupling. Thus this architecture realizes a transceiver area density of 1.6Tb/s/mm2 and an extremely large escape bandwidth areal density of 41.3Tb/s/mm2.
Moreover the use of extremely compact photonics devices with low capacitance such as MRR modulators (<20fF ) and Ge WPD (<2fF ) enables ~0.5pJ/bit power consumption , excluding the laser power. This relatively high energy per bit compared to the components intrinsic capacitance is due to the extra capacitance of the electrical interconnects between the optical devices and the CMOS circuits and to the amplification electronics required at the receiver.
3. Silicon photonics fabrication description
The silicon photonics technology used to fabricate the devices discussed hereafter is based on a 200mm 130nm CMOS fabrication platform . It is important to note that the 130nm CMOS node referred to here only relates to the CMOS fabrication technology for the photonics devices and not to the CMOS technology node required for the high-speed electronics (drivers and receivers) that interfaces with the optical components for 28Gb/s or more data rates.
The final cross-section schematic is shown in Fig. 2. The starting substrates are Silicon-On-Insulator (SOI) 200mm wafers made with a 2.0μm buried oxide (BOX) and a top silicon of 220nm. This layer is patterned with 193nm lithography into three levels to achieve high (220nm deep), medium (150nm deep) and low (70nm deep) optical waveguide confinement. The patterned silicon is then clad with high-density plasma (HDP) oxide that is capable of high-quality filling of narrow trenches without impacting the propagation loss. After planarization of the HDP oxide by chemo-mechanical polishing (CMP), a gate oxide and poly-Si layer is deposited and further patterned into two levels with 193nm lithography to realize high efficiency grating couplers and metal-oxide-semiconductor (MOS) modulators.
The p-n modulators are realized with six levels of dopant implantation, the poly-Si gate is doped with two levels of dopant implantation and all implants are activated with a 1075°C spike anneal. After a second HDP oxide deposition and CMP, the Ge WPD is then formed by selective epitaxy and CMP. The contacts to Ge are formed by ion implantation and thermal anneal at 550°C. The contacts to highly doped silicon and poly-Si regions are improved by a local silicidation process using nickel. The 1-μm deep tungsten (W) plugs contact both the NiSi and the top of the doped Ge regions. The W heaters are then formed before the Cu metal interconnect. A local undercut is made with an isotropic dry etch to remove part of the substrate under the BOX to provide a thermal isolation. Finally a passivation layer is deposited and AlCu bondpads are formed.
4. Silicon photonics device performance
In this section we will first discuss the SOI top silicon thickness uniformity and its impact on our silicon photonics technology. We will then describe the performance of the key building blocks enabling the propose architecture: gratings for vertical coupling to fibers, thermally tuned WDM MRR filters, thermally tuned MRR modulators and the Ge WPD’s.
1. SOI top silicon thickness control
The controllability of the performance characteristics of resonant devices such as MRR is highly dependent on the physical dimension variations. In , the authors identify the top silicon thickness of the SOI substrates to have the largest impact on the device performance variation. In  we have proposed a technique to significantly improve the top silicon thickness uniformity by using a location specific process leading to a within wafer 3-σ uniformity <2.0nm. In  we have reported on improved SOI 300mm substrates that have a 3-σ uniformity of 1.65nm. The characteristics of the 200mm SOI substrates used for the device studies of this paper have a within-wafer 3-σ variation of less than 2.0nm assuming a 1cm edge exclusion.
2. Gratings for vertical coupling to fibers
Gratings are commonly used to couple light from standard single mode fibers to silicon nanophotonic circuits . In recent years the performance of such couplers have been significantly improved with respect to insertion loss and optical bandwidth. For instance in  a 2-D grating coupler enabling polarization diversity exhibits less than 3dB insertion loss over a 26.5nm bandwidth, using a double SOI wafer to create a buried reflector. In  a 1-D grating coupler has less than 2.3dB insertion loss over a 80nm bandwidth combining SiN and Si gratings.
The gratings integrated in the technology described in this paper are based on a poly-Si overlay above the Si waveguides as described in . The performance of such single polarization (TE) grating couplers to a single mode fiber is summarized in Fig. 3. The minimum insertion loss is 2.8dB with a 1-σ of 0.2dB, the peak wavelength is 1552.8nm with a range across the wafer of only 10nm and the 1dB bandwidth is 25.4nm with a 1-σ of less than 8%. The values reported here have been obtained using an automatic wafer-scale prober at fixed fiber height from the wafer top surface and without index matching fluid between the fiber and the wafer. Improved performance characteristics are expected after height optimization and permanent attachment of fibers performed during packaging.
3. Thermally tuned 5-channel WDM Double-MRR filters
The high fidelity patterning achieved with our technology translates into an excellent within-device uniformity, enabling a simple collective control strategy for the heater current tuning with a common feedback loop. An example of such filter array for five channels with double-ring racetrack is shown in Fig. 4(a) and 4(b) . The 5-channel filter spectrum is shown in Fig. 4(c). The plot in Fig. 4(e) illustrates the thermal efficiency improvement of the heaters obtained using a local substrate undercut (Fig. 4 (d)) from 0.21nm/mW to 1.09nm/mW per channel . When assuming data rates of 28Gb/s, it requires 0.5pJ/bit to tune this filter over a range of more than 14nm.
The key characteristics of this component have been measured on all full dies (130) across a 200mm wafer and are shown in Fig. 5 . The first channel wavelength is controlled with a 1-σ of 2.6nm and the 1dB bandwidth 1-σ is less than 4%.
These filters can be used in WDM systems where the laser channel spacing is fixed and matches the filter channel spacing that is defined by design. Because of the high fabrication quality there is no need to adjust the channel spacing within one filter and the only tuning required is common to all filters to track the WDM laser comb relative shift to the filter comb.
4. All-pass MRR modulator
The MRR modulator fabricated in this study is shown in Fig. 6, defined in the 150nm deep etch level and with a radius of 7.5μm . The modulator formed with a lateral diode along the full circumference of the ring. W heaters and UCUT have been integrated with the MRR modulator for efficient thermal tuning of the operating wavelength.
The static performance of this depletion p-n MRR modulator is summarized in Fig. 7. The wavelength selected for characterization of the extinction ratio and insertion loss corresponds to the maximum extinction ratio for a 1V voltage swing applied to the modulator. The average extinction ratio is 5.6dB with a 1-σ of less than 10% and a corresponding insertion loss of 9.4dB (1-σ less than 7.5%). The average quality factor is 4812 and is controlled with a 1-σ of less than 4%. The average modulation efficiency is 35pm/V with a 1-σ of 2.8pm/V and the heater efficiency with UCUT is 259pm/mW with a 1-σ of 7pm/mW .
The dynamic performance of the MRR modulator is given in Fig. 8. With an R1 of 57ohm and a C1 of 36fF this device has an electro-optical bandwidth of 22GHz and is capable of operating at 28Gb/s (Fig. 8(d)) .
A well-known issue of these modulators is the very limited operating bandwidth and temperature that require an accurate thermal control. We have recently demonstrated that such control can be realized by taping a small fraction of the modulator optical power to monitor the optical modulation amplitude .
5. Germanium waveguide photodetector
For this study we have designed a 15μm-long vertical PIN Ge/Si diode with p-type contact in Ge and n-type contact in Si . The designs of the contact to the Ge have been varied on three types of devices to achieve different responsivity and opto-electrical bandwidth trade-offs: denser contacts closer to the Ge waveguide center enhance the bandwidth but degrades responsivity.
The yield of these devices on a 200mm wafer is 97%. The responsivities at 1555nm, −1V reverse bias, for Type I, Type II and Type III respectively are 0.58A/W, 0.85A/W and 0.97A/W with a standard deviation less than 0.05A/W. The dark current is well-behaved and typically between 10nA and 30nA for all designs (see Fig. 9). Type I and Type II are capable to operate at 28Gb/s .
Because of the heterogeneous nature of the Ge WPD on a Si waveguide, there is a genuine concern of the repeatability of the quality of such device. We have measured the leakage current of vertical Ge/Si diodes under 1V reverse bias with three different lengths (5.8μm, 10.4μm and 21.8μm) on at least nine dies per wafer across six wafer batches with at least five wafers per batch. It is important to also note that four different masksets were used during this study. The trend chart is shown in Fig. 10: nearly every data point is below 50nA. This demonstrates that the Ge WPD can be made reliably with low dark current.
We have presented a systematic study of the performance and its variability of various key building blocks required to realize compact, low power multiplexed optical interconnects operating at 28 Gbps using silicon photonics technology based on 130nm CMOS technology processing equipment (200mm substrate). Improved wafer-scale control is expected by exploiting more advanced CMOS processing equipment.
This work was supported by imec’s CORE partner program. The authors would like to thank imec p-line for the silicon photonics fabrication. Part of the research leading to these results has received funding from the European Community's Seventh Framework Programme(FP7/2007-2013) under grant agreement n° 318178-PLAT4M.
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