We present a five-channel wavelength division multiplexed modulator module that heterogeneously integrates a 200 GHz channel-spacing silicon arrayed-waveguide grating multiplexer and a 20 Gbps electro-absorption modulator array, showing the potential for 100 Gbps transmission capacity on a 1.5x0.5 mm2 footprint.
© 2015 Optical Society of America
Wavelength division multiplexing (WDM) modules are of key importance for realizing high aggregate bitrate optical networks and optical interconnects. WDM transmitters and receivers require low cost and high performance devices for maximal bandwidth usage and high energy-efficiency. For the key opto-electronic components in a WDM system, both silicon and III-V based devices are available. Potentially CMOS compatible, low-cost, monolithic silicon WDM modulator chips have been reported [1, 2 ]. However, an optically broadband silicon-based modulator usually has a large footprint and requires a relatively high driving voltage and hence high power consumption for sufficient extinction ratio . Alternatively, purely III-V WDM modulator chips have been demonstrated [4, 5 ]. Although they are more efficient than silicon modulators, the monolithic integration with passive wavelength division multiplexing devices, e.g. arrayed waveguide gratings (AWG) and etched diffractive gratings (EDG) requires involved techniques such as selected area growth (SAG), butt joint regrowth (BJR) or quantum well intermixing (QWI). In order to overcome these issues, a hybrid silicon platform that combines the advantages of III-V based materials and silicon is being studied. III-V/Si hybrid active devices with excellent performance, such as hybrid silicon narrow linewidth lasers , high-speed modulators , and high-speed detectors  have already been demonstrated. The highest speed modulators on silicon were achieved by transferring a III-V epitaxy stack onto a SOI wafer to realize a 67GHz bandwidth traveling-wave hybrid silicon electro-absorption modulator (EAM) . These hybrid devices can be integrated together to build up more complex on-chip photonic modules [9, 10 ] on silicon-based substrates, which shows its potential for high density, high performance WDM transmitters and receivers for optical communication networks and multi-CPU optical interconnects in the future.
In this paper, a silicon AWG and an array of five III-V EAMs are heterogeneously integrated using adhesive bonding technology . The (lumped) III-V EAMs show 17 GHz E/O bandwidth and can operate up to 28 Gb/s. A five-channel wavelength division multiplexed modulator module with an ultracompact size (1.5x0.5 mm2), a low driving voltage (~2.5 Vpp), and a large extinction ratio (4.9-6.9 dB) is obtained with 100Gbps capacity.
Figure 1 shows the schematic of the chip layout. On each channel of the AWG, a separate EAM is integrated. The AWG is formed by 220 nm height silicon waveguides and it has five channels with 200 GHz channel spacing. The III-V layer stack used for the EAM is shown in Table 1 . The InAlGaAs multiple-quantum-well (MQW) stack is sandwiched between two separate confinement heterostructure layers (SCHs). It’s composed of 10 compressively strained wells and 11 tensile strained barriers and has its photoluminescence (PL) peak at 1480 nm. Compared with InGaAsP quantum wells, the InAlGaAs quantum wells give a stronger quantum confined stark effect (QCSE) and hence a better modulation efficiency, due to its larger conduction band offset . The layer stack is designed for transverse electric (TE) polarization  in the C-band, compatible with conventional semiconductor diode lasers. In our design, the confinement factors in the MQW region and in Si are 0.41 and 0.03, respectively. The superlattice layer structure is incorporated to prevent the propagation of dislocations into the active region due to the bonding.
Figures 2(a) and 2(b) are the cross-sectional view and top view of the EAM, respectively. The length of the active modulator section is 100 µm and it is 2 µm wide. Benzocyclobutene (DVS-BCB) is adopted for adhesive bonding and is also used for passivation to decrease the parasitic capacitance. A lumped electrode structure is adopted, which means the RC time constant limits the high speed performance of the EAM. The passive silicon waveguide underneath is a rib waveguide with 1.5 µm width and is 160 nm shallowly etched into the 380 nm silicon layer. The optical coupling between the silicon device layer and the III-V epitaxial stack is realized using a bi-level taper consisting of two linearly tapered sections in the III-V structure. In the first taper section, the optical mode is converted from the silicon waveguide to the MQW (including SCH layers) waveguide without the thick p-cladding layer. Then, the second taper section adiabatically transforms the waveguide mode to that of the full III-V structure. The thickness of the Si at the hybrid modulator section is set to be 380 nm to achieve a better coupling between the Si and III-V waveguides. This is realized by depositing poly-silicon on the 220nm thick crystalline silicon SOI wafer. We analyze the performance of the tapers for different values of Lt1, Lt2 and the BCB bonding layer thickness hBCB, using a commercial software FIMMWAVE . Lt1 and Lt2 are the lengths of MQW taper and p-InP taper, respectively. Wtip1 and Wtip2 are the widths of the tips of the MQW taper and p-InP taper, respectively. The BCB thickness is labeled as hBCB. Figures 3(a) and 3(b) show the coupling efficiency as a function of the lengths Lt1, Lt2, when hBCB varies. Here we assume Wtip1 = Wtip2 = 0.2 µm, and while one taper is investigated, the other taper is set to be long enough for adiabatic conversion. From the figures we can find that the smaller hBCB, the better the coupling efficiency and the shorter the taper length. However, thinner BCB bonding layers reduce the yield of the bonding process and hence a trade-off needs to be made is selecting the bonding layer thickness.
In our design, we assume Lt1 = 30 µm, Lt2 = 15 µm and hBCB = 0.03 µm. The mode transformation under this condition is presented in Fig. 3(c). The coupling efficiency from the passive silicon waveguide to the III-V waveguide using this 45 µm long taper can be more than 95%.
Figure 4 shows a schematic diagram of the fabrication process. The silicon photonic components are defined on 200 mm silicon-on-insulator (SOI) wafers with a 380 nm thick poly-silicon / crystalline silicon layer using 193 nm deep UV lithography. The rib silicon waveguides are etched 160 nm deep using inductively-coupled-plasma (ICP) dry etching. The silicon waveguide circuits are then planarized through SiO2 PECVD deposition followed by chemical mechanical polishing down to the silicon device layer. The III-V layer stack is adhesively bonded to this silicon waveguide using a 30 nm thick DVS-BCB layer. The thickness of BCB at different bonding locations may vary by 10% (so 3nm). HCl is then used to remove the InP substrate.
The p-InP mesa with a width of 3.5 μm is defined by using the top p-metal (Ti/Au) as a hard mask. The 100 nm InGaAs layer and 1.5 µm InP p-doped layer are etched using selective wet chemical etching with 1H3PO4: 1H2O2: 20H2O and 1HCl:1H2O, respectively. The waveguide is oriented along the [0 1-1] direction of the III-V. The width of the p-InP at the bottom is reduced to 2 µm as the orientation of the EAM mesa with respect to the InP crystal planes introduces an inverted trapezoidal mesa. Afterwards, a 5 µm wide SiN mask is defined using UV lithography. 20CitricAcid: 1H2O2 is used for wet etching of the MQW layer and the MQW is underetched by 3 µm in order to reach 2 µm in width. The etching is selective to the n-InP beneath. The widths of the tips (Wtip1 = Wtip2 = 0.2 µm) are quite critical for a good coupling. In this work, such narrow taper tips are defined using UV lithography and carefully controlled by wet chemical etching, which demonstrates the manufacturability of these components in standard III-V processing lines. When the III-V mesa is defined, the n-type layer is etched using HCl. Then Ni/Ge/Au is deposited for the n-contacts. In the next step, the III-V structure is encapsulated with DVS-BCB for passivation to decrease parasitic capacitance. Reactive ion etching (RIE) is used to etch through the DVS-BCB layer to open the n-contacts and the p-contacts. Finally, ground-signal-ground (GSG) metal contact pads with 100 μm pitch are formed for the RF ports. The SEM pictures of the top view and cross section of the EAM are shown in Figs. 5(a) and 5(b) , respectively. The inset of Fig. 5(a) shows the narrow taper tip.
4. Experimental results
The normalized transmission spectra of the 5-channel multiplexer before and after the heterogeneous integration of EAMs are shown in Fig. 6 . The curves are normalized to a reference waveguide with grating couplers showing 12dB fiber-to-fiber insertion loss. By comparing the spectra shown in Fig. 6(a) and 6(b), one finds that the central wavelength of each AWG channel shifts a little after the hybrid integration, and the side lobes of the AWG are slightly broadened. This is attributed to the different top cladding of the AWG after the III-V processing. Therefore, the phase relation will be affected and finally the spectrum will change.The channel spacing of the AWG is 1.6 nm and the device has an insertion loss less than 3 dB. However, after EAM integration the insertion loss varies from between −9.3 dB to −3.4 dB (measured after passing through the EAMs). However, after EAM integration the insertion loss varies from between −9.3 dB to −3.4 dB (measured after passing through the EAMs and AWG), which is mainly attributed to non-uniform insertion losses of the fabricated EAMs, although each EAM is designed to be identical. The III-V processing is expected to have no influence on the passive silicon waveguide circuit, as the etching is selective and the silicon layer is well protected beneath the oxide layer. The minimum insertion loss of the EAM at 0V bias is measured to be 1.2 dB. Figure 7 illustrates the measured static extinction ratio of the 100µm-long EAMs under different reverse biases. More than 12 dB extinction ratio can be achieved when the bias is changed from 0 V to −2.5 V.
The small-signal modulation of the hybrid EAMs was measured using a vector network analyzer. Figure 8 shows the typical electro/optical (E/O) modulation response and the microwave reflection (S11) to the RF source for an EAM under a reverse bias of −2 V. The measurement indicates the E/O 3 dB bandwidth is 17 GHz. The red lines in the figures are the fitting results of the measured data according to an equivalent electrical circuit model  of the modulator [see the inset of Fig. 8(b)]. In the circuit diagram, Zs is the 50 Ω source impedance, Lm is the inductance, Ra is the device resistance, Ca is the junction capacitance, Rj is the device junction leakage resistance and Ce is the parasitic capacitance between the electrodes. Besides, we also consider the resistance and capacitance between the electrodes and the Si substrate Rsub and Csub. The junction capacitance Ca is fitted to be 0.145 pF. As the electrodes of the modulators are lumped electrodes, it suffers from strong microwave reflection.
For the large signal modulation measurements, a tunable continuous wave (CW) laser was aligned to each channel of the AWG. A SHF pattern generator followed by a driving amplifier and a bias tee produced a PRBS signal with 2.3 to 2.6 Vpp with a DC offset of −1.5 V to −2 V to drive the EAMs. The modulated light was boosted by an erbium-doped fiber amplifier (EDFA). A narrow optical filter was inserted to remove the amplified spontaneous emission (ASE) noise generated by the EDFA. Finally, eye diagrams were obtained with a Tektronix 8300A digital series analyzer. The 20 Gb/s and 28 Gb/s eye diagram of the EAM on channel 2 are displayed in Figs. 9(a) and 9(b) , respectively. Figures 10(a)-10(e) shows the eye diagrams after the AWG multiplexer at 20 Gbps for the five different channels. All EAMs exhibit clean and open eyes. The dynamic extinction ratios vary between 4.9 dB and 6.9 dB, limited by the large insertion loss of the chip in the experiment.
We report a five-channel WDM modulator module that heterogeneously integrates a 200 GHz channel-spacing arrayed waveguide grating multiplexer and a 20 Gbps electro-absorption modulator array reaching 100 Gbps capacity. The total size of the device is 1.5x0.5 mm2. The bandwidth of each modulator is around 17 GHz enabling 20 Gbps and 28Gbps modulation. The device modulation bandwidth can be further enhanced by reducing the device length (thereby decreasing the RC) or introducing a travelling wave design. The realization of the module on a hybrid silicon photonic platform allows in a next step to co-integrate the laser sources as well.
This work is partially supported by the National High Technology Research and Development Program (863) of China (2012AA012201), the National Nature Science Foundation of China (#61107020 and 91233208) and Guangdong Innovative Research Team Program (No. 201001D0104799318). Xin Fu acknowledges the China Scholarship Council (CSC) for a student grant.
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