We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than −20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.
© 2015 Optical Society of America
Dynamic optical path switching is a promising method to reduce the power consumption of optical telecom and datacom networks . The key device is a low-cost high-port-count strictly-non-blocking optical switch, and high-density photonic integration is a promising approach. Highly integrated switch fabrics based on silicon-on-insulator (SOI) [2–4], InP , and waveguide-based microelectromechanical system  platforms have been demonstrated. Among these, the SOI platform is very attractive because it allows mass production using a complementary metal-oxide-semiconductor (CMOS)-compatible fabrication process with large wafers. We have already reported a record-compact 8 × 8 strictly-non-blocking thermooptic optical switch based on Si-wire waveguides . The switch employs a path-independent-insertion-loss (PILOSS) topology , which ensures port-count scalability in terms of power consumption since only N element switches should be active in an N × N switch. Recently, we have demonstrated scalability of the PILOSS Si-wire switch up to a port count of 32 × 32 .
In this paper, we report an ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch packaged with a land grid array (LGA) interposer. The optical switch integrates 1024 thermooptic Mach-Zehnder (MZ) switches and 961 intersections on a very small, 11 × 25 mm2 die. The footprint of the switch chip is 46 times as small as that of a silica-based 32 × 32 optical switch . This paper addresses two technical challenges to achieving a port count of 32 × 32: high intra-die uniformity and high-density electronic packaging. Loss and crosstalk of the MZ element switch impose intrinsic limitations on the performance of the PILOSS switch. In addition, MZ switches have to be uniform within the die for a large port count. We observed crosstalk degradation caused by intra-die non-uniformity due to dimensional errors arising during the fabrication of the 8 × 8 Si-wire switch . Clearly, the requirements for uniformity become more severe in the 32 × 32 switch. To minimize the dimensional error in the fabricated switch, we utilize advanced facilities for prototyping 45-nm CMOS transistors on 300-mm wafers, featuring ArF immersion lithography. Electronic packaging is also important to scale the port count of the PILOSS switch. The 8 × 8 Si-wire switch employed wire bonding with a simple pad arrangement on the chip for connecting the 136 heater electrodes to the control electronics . However, assuming a similar pad arrangement in the 32 × 32 switch with more than 2000 heaters, the die would be very large. To keep a small footprint on the SOI platform, the dense two-dimensional pad arrangement on the chip is fanned out to a 0.5-mm-pitch LGA through a ceramic interposer that is flip-chip bonded to the chip. The transmission characteristics of the optical switch with the interposer are measured for sampled optical paths, and an on-chip loss of 15.8 ± 1.0 dB is achieved. We also demonstrate successful switching performance with 43-Gb/s QPSK signals. The crosstalk of the switch is then discussed. The worst crosstalk is estimated to be −20 dB at a bandwidth of 1.8 nm.
2. Design, fabrication, and packaging
The 32 × 32 optical switch employs one of the strictly-non-blocking switch configurations in which 2 × 2 element switches are arranged in a matrix with 32 rows and 32 columns and are connected by intersections. The topology enables PILOSS operation since the pass length becomes equal for all possible switching paths [4,7]. We fabricated the 32 × 32 switch on a 300-mm-diameter SOI wafer by using a CMOS-compatible mass-production process. ArF immersion lithography, which provides a 45-nm process rule for CMOS transistors, is used to improve the intra-die and inter-die uniformity . Figure 1 shows microscope photographs of the switch chip. The switch chip integrates 1024 2 × 2 MZ element switches and 961 intersections. As shown in Fig. 1(a), the die footprint is 11 × 25 mm2, including the electrode pads for flip-chip connections, which is 46 times as small as the 115 × 110 mm2 silica-based 32 × 32 PILOSS switch .
Figure 1(b) shows a magnified image of the MZ element switch and intersection. The MZ switch consists of two 3-dB directional couplers (DCs) for the transverse-magnetic (TM) mode and thermooptic phase shifters with a TiN heater on both arms. The operation in TM mode is chosen because of the larger tolerance for dimensional errors in the DC. For future polarization insensitivity, polarization diversity is a prospective approach. The Si-wire waveguides are 430-nm wide and 220-nm high, and buried by 1.5-μm-thick SiO2 cladding. The electrical wiring pattern is formed by the deposition and etching of Al. The MZ element switch is designed to be in the cross state without heating. The intersection is based on a 0-dB DC in which all the input power is transferred to the adjacent waveguide. The 0-dB DC is arranged with 90-degree rotation, resulting in low crosstalk in C-band [4,11]. We confirmed from finite-difference time-domain simulations that the loss and crosstalk are less than 0.1 dB and −45 dB, respectively.
For reliable electrical contacts between the switch chip and control electronics, the pad arrangement of the chip is fanned out with a ceramic LGA interposer. Figures 2(a) and 2(b) show a photograph and a schematic side view, respectively, of the optical switch after flip-chip bonding. The interposer converts the pad arrangement on the chip (minimum pitch: 0.18 mm) into a 0.5-mm-pitch LGA. An array pitch of 0.5 mm is common in the packaging of LSI circuits. Note here that electrical crosstalk between the LGA pads is negligible since the heaters with a response frequency of less than 100 kHz are driven by direct current. The switch chip is flip-chip bonded to the interposer by thermal compression with Au bumps andnonconductive paste. The footprint of the switch including the LGA interposer is 36 × 25 mm2. Figure 3 shows a histogram of the electrical resistances of the heaters after flip-chip bonding. The resistance is 281 ± 2 ohm. The small variance indicates that high uniformity is achieved in both the fabrication of the heaters and the flip-chip bonding. The optical switch with LGA interposer achieves contact with a printed circuit board (PCB) by using an LGA socket as shown in Fig. 2(c).
The performance of an MZ element switch fabricated on the same die of the 32 × 32 switch circuit was measured for TM input light. Figures 4(a) and 4(b) show the transmission spectra of intended output and power leakage to an unintended port in the bar and cross states, respectively. Crosstalk is defined as a ratio of the leakage to the intended output. In both switching states, the minimum crosstalk is less than −40 dB at approximately 1545 nm. The bandwidths in which the crosstalk is below −35 dB are 4.3 nm and 2.3 nm for the bar and cross states, respectively. The leakage at the cross state, which fluctuates in the low power range, is affected by residual TE-like component due to the limited polarization extinction ratio of the measurement setup. When the TE-like component is launched into the MZ element switch, the light straightly passes through the waveguide without coupling to the adjacent waveguide at the DCs designed for TM mode, regardless of the switching state. In the cross state, this residual component being out from port 1 in Fig. 4(b) is observed as the background of the leakage for the TM input. Thus, the measured crosstalk is limited here. On the other hand, the residual component becomes the background of the intended TM output in the bar state, and the effect is not clearly observed in the high power range. In the PILOSS switch circuit, the residual TE-like component is attenuated at the intersections that function as a polarization cleaner for TM mode, as shown in our previous work . Therefore, the bandwidth is defined here with the envelope. Using the bandwidth of 2.3 nm, we discuss the total crosstalk of the 32 × 32 switch in the next section. Figure 5 shows the response time of the test element switch.
A response time of less than 30 μs is achieved, which is fast enough for dynamic optical path allocation.
The transmission characteristics of the 32 × 32 switch with LGA interposer were measured. Any path contains 32 MZ element switches and 31 intersections in the PILOSS topology. In order to set a path, a switching current is applied to one of the MZ element switches along the path to set it to the bar state, and small trimming currents are applied to the other 31 cross-state MZ element switches. The trimming current that compensates phase offset of the MZ element switch is required to make the exact cross state, minimizing the loss and crosstalk. Owing to the limited channel number of the control electronics on the PCB, the six paths 1-12, 1-20, 1-32, 32-1, 32-13, and 32-19 are selected to show typical performances, in which 96 MZ element switches operate in total. The selected paths on the 32 × 32 PILOSS switch matrix are shown in Fig. 6(a). The numbers in brackets denote the row and column of the activated or bar-state MZ element switch. Figure 6(b) shows the on-chip loss of the paths at 1545 nm. The on-chip loss excluding the loss of the fiber-to-chip coupling is 15.8 ± 1.0 dB, and it can be broken down as follows: the propagation loss of the access waveguides for the input and output is 2.1 dB, and the loss of the switch part is 13.7 dB. Loss of 32 MZ element switches and 31 intersections comprises the loss of the switch part, and hence the combined loss of one MZ element switch and one intersection is 13.7/31.5 = 0.44 dB. Since the propagation loss of the switch part is estimated to be 5.5 dB from the propagation loss of the Si-wire waveguide, the combined excess loss is (13.7-5.5)/31.5 = 0.26 dB. Accumulations of small bending losses and backward light leakage of the intersection are considered to be the main causes. Note here that two switch samples are used for the measurement because of contact failures in the socket; one sample is for the measurement with the input port 1, and the other is for the measurement with the input port 32. This contact problem will be fixed by improving the interposer for better accuracy in the absolute position of the LGA pads. The typical electrical powers to set the MZ element switch to the bar and cross states are 45 mW and 1.5 mW,respectively. The smaller power is the trimming power for the exact cross state. Since the 32 × 32 optical switch operates with 32 bar-state and 992 cross-state MZ element switches for the full connections, the total power consumption is estimated to be 2.93 W.
The 32 × 32 switch is next demonstrated with a 43-Gb/s digital-coherent QPSK signal. The signal at 1544.93 nm is generated by a tunable laser diode, an IQ modulator, and a pulse pattern generator with a pseudo-random bit sequence of 231-1. The signal is launched into the switch, and the output is received with digital-coherent detection after adjustment of the optical signal-to-noise ratio (OSNR). The OSNR was set at 16.7 dB by using a variable optical attenuator and an Er-doped fiber pre-amplifier. The receiver consists of a 90-degree hybrid optical circuit, a tunable laser diode as a local oscillator, and balanced photo detectors. A high-speed oscilloscope with an analog bandwidth of 33 GHz was used for analog-to-digital conversion, and only a phase tracking algorithm was employed for the demodulation of the signal. Figures 7(a) and 7(b) show the error vector magnitude (EVM) and constellation diagrams, respectively, at an OSNR of 16.7 dB for sampled optical paths of 1-10, 1-19, 1-29, 32-1, 32-13, and 32-27. The received QPSK signals have the same signal quality as those under back-to-back conditions. These results indicate that the OSNR penalty due to the switching with the heaters is negligibly small.
In the present study, we did not evaluate the crosstalk characteristics when all the inputs and outputs were fully connected because the channel number of the control electronics is limited. Here, let us predict the total crosstalk from the measurement results of the test element switch shown in Fig. 4. Note that the multi-path interference or the coherent crosstalk is not taken into account here. In the PILOSS switch topology, an input signal passes through 32 MZ element switches and 31 intersections. The 32 signal paths can cross each other at the MZ element switches and at the intersections, and these crossings lead to crosstalk. The crossing at the MZ element switch gives more crosstalk than the intersection in our switch since the crosstalk of the intersection is an order of magnitude smaller. Hence, the worst crosstalk is approximated by a situation in which 30 crossings occur at the MZ element switches. Note that no two paths cross at the first or last MZ element switch in the PILOSS topology. Then, the worst total crosstalk is estimated to be −35 dB + 14.8 dB (30 times) = −20.2 dB at a bandwidth of 2.3 nm if the center wavelengths of the MZ element switches are identical. In practice, the center wavelengths vary slightly, resulting in narrowing of the bandwidth.
Then, we take the narrowing effect into account and estimate the bandwidth in which the total crosstalk is below −20 dB. The crosstalk of −20 dB is, in general, a minimum requirement for error-free signal reception at beyond 10 Gbaud. The variation in the center wavelength is caused mainly by dimensional errors in the fabrication of the DCs of the MZ element switch. Figure 8(a) shows a cross section of the DC. The width of the waveguides is 430 nm, and thegap between them is 430 nm. The dimensional errors in the waveguide width were determined by using a critical dimension scanning electron microscope. The standard deviation of the 430-nm pitch line and space patterns was 0.9 nm across the wafer under on-resist conditions. We assume here that there is little change in the standard deviation after etching of the waveguide in a small die and discuss the variation in the center wavelength with the value. Assuming that the change in waveguide width at the DC is only the cause of the variation, we estimate the effect as follows. Note that the variation in SOI thickness is less than 1 nm across the 300-mm wafers we used and is negligibly small in the die.
First, the effective refractive indices of the 0th and 1st TM-like modes of the directional coupling section, neff-TM0 and neff-TM1, are calculated for various waveguide widths W around 430 nm by the finite element method. The gap between the waveguides varies with W. The relationship between the differences in effective refractive indices Δ neff-TM = neff-TM0 - neff-TM1, W, and the wavelength λ is obtained in terms of Δ neff-TM(W, λ). Assuming simply that two DCs of an MZ element switch located close to each other on the die have the same waveguide width, the center wavelength of the MZ switch, λc, is calculated from the mode coupling theory via:Figure 8(b) shows the results. The standard deviation of the center wavelength is 0.083 nm for a standard deviation of the waveguide width of 0.9 nm. If we consider three standard deviations, the narrowing of the bandwidth is calculated to be 3 × 0.083 nm × 2 (plus and minus from the center) = 0.5 nm. This is 1/10th the value obtained for the Si-wire 8 × 8 PILOSS switch that we fabricated using electron beam lithography , even though the die size is 16 times as large as that of the 8 × 8 switch, which is attributable to the advanced fabrication process involving ArF immersion lithography. The bandwidth with the total crosstalk below −20 dB is estimated to be 2.3 nm – 0.5 nm = 1.8 nm at around 1545 nm. Future challenges include obtaining a lower crosstalk and broader bandwidth. Prospective approaches employ the double-gate MZ configuration  and wavelength-insensitive couplers .
We have demonstrated the port-count scalability of the PILOSS Si-wire optical switch up to 32 × 32 with the advanced CMOS process on 300-mm SOI and packaging technology using a 0.5-mm-pitch LGA interposer. A small chip footprint of 11 × 25 mm2 was achieved. The on-chip loss was 15.8 ± 1.0 dB, and the worst crosstalk was estimated to be −20 dB in a bandwidth of 1.8 nm around 1545 nm. The optical switch was successfully demonstrated with 43-Gb/s QPSK signals. Our future work includes demonstrations of the full functionality of the 32 × 32 switch with the LGA interposer by developing a PCB that is capable of controlling all the 2048 heaters. Broadening the bandwidth, improving the efficiency of optical coupling, and avoiding the input polarization sensitivity are among challenges that need to be overcome to enable the practical use of the optical switch.
This work was supported in part by Project for Developing Innovation Systems of the Ministry of Education, Culture, Sports, Science and Technology of Japan.
References and links
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