We present a theoretical optimisation of 1D apodized grating couplers in a “pure” Silicon-On-Insulator (SOI) architecture, i.e. without any bottom reflector element, by means of a general mutative method. We perform a comprehensive 2D Finite Difference Time Domain study of chirped and apodized grating couplers in 220 nm SOI, and demonstrate that the global maximum coupling efficiency in that platform is capped to 65% (−1.9 dB). Moving to designs with thicker Si-layers, we identify a new record design in 340 nm SOI, with a simulated coupling efficiency of 89% (−0.5 dB). Going to thicker Si layers does not further improve the efficiency, implying that −0.5 dB may be a global maximum for a grating coupler in SOI without a bottom-reflector. Even after allowing for 193 nm UV-lithographic fabrication constraints, the 340 nm design still offers −0.7 dB efficiency. These new apodized designs are the first pure SOI couplers compatible with deep-UV lithography to offer better than −1 dB insertion losses. With only very minor changes to existing deposition and lithography recipes, they are compatible with the multi-project wafer runs already offered by Si-Photonics foundries.
© 2015 Optical Society of America
One of the most interesting platforms for the next-generation of silicon optical circuits is the Silicon-On-Insulator (SOI) architecture. This is based on a thin crystalline silicon (c-Si) membrane lying on the top of a few microns thick silicon dioxide (SiO2) layer. The SOI system provides light guiding in the silicon, and can be nanostructured for light manipulation at the wavelength scale. In the “pure” Complementary-Metal-Oxide-Semiconductor (CMOS) compatible SOI architecture, the silicon waveguide and the oxide are grown on a c-Si wafer, and the structure does not contain any metallic element. Currently, the SOI platform is the best candidate to integrate Photonics and Micro-electronics in a single device. It has also potential for low-cost and large-throughput: Thousands of optical circuits can be manufactured in parallel on a 200 mm / 300 mm SOI wafer using optical lithography and automated production lines.
The SOI approach offers a high refractive index contrast Δn between c-Si and SiO2. The high Δn allows for a tight light confinement on the chip, and opens the way for an unprecedented miniaturization of electro-optical devices. The 220 nm SOI architecture has become a “de facto” standard for Si-Photonics, as it is widely available, offered by the Si-foundries for multi-project wafers, and it gives single mode wave-guiding for light in the telecom C-band around 1550 nm. However, the tight optical confinement poses a significant problem when light has to be injected from an optical fibre to the silicon chip and vice versa, because the single-mode fibre has a relatively large core diameter of ≈ 10 microns, and the index contrast with the cladding is much lower than in the SOI waveguide (Δn ≤ 0.1). This generates a large modal mismatch between the fibre and the SOI waveguide, and, consequently, large insertion losses.
The grating coupler (GC) is a promising approach for this coupling problem. GCs can be fabricated and integrated directly in the SOI circuit, they have a small footprint around 15×15 μm2, and they show relaxed spatial alignment tolerances thanks to the vertical coupling scheme. The 1 dB alignment tolerance is around ± 2 μm, compared to edge-coupling methods with 1 dB tolerances of just ± 500 nm . Although the fibre-to-waveguide coupling efficiency (CE) has been improved during the last years in 1D GCs [2–14] and in 2D polarisation-diversity couplers [16–21], the insertion losses are still the main bottleneck of such an approach. Efficiencies better than −1 dB (80%) have been demonstrated at a laboratory level, however the vast majority of grating couplers being fabricated in standard 220 nm SOI offer only −3.5 / −6 dB efficiency [22–24].
For the 1D GCs, a higher coupling efficiency can be achieved with an apodized design: The position and width of each lattice element are engineered to maximise the coupling probability. In addition, also the etching depth can be varied along the grating, taking advantage of the lag effect in the dry-etching process  to improve the grating-to-waveguide impedance matching. In Fig. 1 we illustrate a summary of the state of the art for the CE of 1D apodized GCs, and we compare with the best theoretical result of this work. The designs are divided into two categories: with and without back reflector (i.e. in the latter case the grating is placed on a Silicon substrate).
Apodized GCs without a back reflector (left part of Fig. 1) do not require any post or preprocessing steps beyond those within standard CMOS fabrication, and are much easier to fabricate than those with a back reflector (right part of Fig. 1). For the latter, a highly specialized step is required for the mirror bonding [11,12] or for the back-surface metallisation [13,14]. Up to now, no foundry has either introduced nor standardized such processes. On the other hand, the drawback of using a standard Si substrate is the low reflectance of the bottom Si-SiO2 interface, which allows for significant losses in the Si substrate. In a 220 nm thick SOI architecture, the maximum theoretical CE found so far  is 61% (−2.15 dB). To improve this result, it is necessary to use thicker grating structures which operate in a double TE-mode regime: they can be obtained e.g. by adding a patch of a-Si or poly-Si to 220 nm SOI, which is becoming a common procedure for Si-photonics foundries [8, 9]. Chen and coworkers  adopted a pure 340 nm thick SOI platform, and reported the highest theoretical and experimental CE of 84% (−0.76 dB) and 74% (−1.31 dB), respectively. Furthermore, hybrid SOI approaches were proposed. For example, Roelkens and colleagues  calculated a maximum CE of 78% (−1.08 dB) for a 220 nm SOI grating with a poly-Silicon overlay, and Vermeulen and coworkers  reported an experimental CE of 69% (−1.6 dB) in a similar device fabricated in a 200 mm CMOS factory line. More recently, Yang and collaborators  proposed a Germanium overlay and reported a theoretical CE of 76% (−1.19 dB).
On the other hand, 1D apodized GCs with a distributed Bragg reflector  or a metallic back reflector [11–15] have also been proposed at the lab-level (right part of Fig. 1). The absolute theoretical and experimental record efficiencies of 94% (−0.26 dB)  and 87% (−0.58 dB)  are obtained with a SOI thickness of 250 nm and a bottom Al mirror.
In this work we focus on 1D apodized grating couplers in the pure SOI platform with a Silicon substrate. We prove that they have the potential to reach ultra-high efficiencies comparable with more complicated designs including bottom-reflector elements. A sketch of the structure under investigation is shown in Fig. 2(a). The SOI waveguide thickness is denoted with S, the etching depth with E, the x-position of the centre of the ith SiO2 trench with pi, and the respective width with wi. The bottom oxide (BOX) thickness is denoted with B, and the top oxide (TOX) layer is infinitely extended. This simulates the situation in which the fibre is perfectly impedance-matched to the TOX. We assume constant refractive indices for Si and SiO2, equal to 3.47 and 1.44, respectively [25,26]. TE-polarised light (the electric field is along the z-direction) from a single-mode fibre is incident from the top at an angle of 10 degrees with a given fibre offset. We find designs with an ultra-high coupling efficiency of 89% (−0.5 dB) in a 340 nm thick SOI platform without any back reflector. This result is reported in Fig. 1 with a large yellow triangle. The CE spectrum is reported in Fig. 2(b) with a red line and compared with the spectrum of the best apodized grating in standard 220 nm SOI. The CE values for the best uniform designs in 220 and 340 nm SOI are also reported with horizontal dashed lines for comparison. An absolute +24% efficiency gain is achieved by simply increasing the thickness of the grating region. Thanks to the mutative optimisation of the apodized design, our best CE is 5% higher than in the previous record-efficiency configuration , and the gap with respect to the absolute record-efficiency GC with an Al back reflector  is reduced to less than 5%. Special attention is paid to the FDTD mesh and convergence to ensure a high fidelity for our numerical results.
The rest of the paper is structured as follows. In Section 2 we present the optimisation method and its application to the case of a standard 220 nm thick SOI architecture. The target is to determine the highest efficiency achievable in this platform. In Section 3 we explore larger SOI thicknesses and we present our best results. Special attention is paid to the constraints imposed to the design by deep-UV lithography, and to the visual analysis of the physical mechanisms behind the improved coupling efficiency. The Conclusions are presented in Section 4. The computational details of our method and the convergence study for 2D-FDTD simulations are given in the Appendix.
2. Optimisation of apodized grating couplers for a 220 nm thick SOI architecture
In this section we apply our optimisation method to the standard SOI thickness of 220 nm. This architecture is single TE-mode at the telecom wavelength of 1550 nm, and thus is the ideal platform for Si-Photonics. Grating couplers with a shallow etching (∼ 70 nm) are routinely produced in 220 nm SOI, but they offer a coupling efficiency below 45% (−3.5 dB) dB when they are fabricated at the industrial level [22–24]. The target is to determine the ultimate coupling efficiency of an apodized design in 220 nm SOI. Since we are also interested in the ultimate deliverable coupling efficiency, we consider design constraints compatible with deep-UV lithography. In this case, the minimum feature size is set to 100 nm.
The main idea behind our method is to start from a uniform grating structure, and then modify it to find the best apodized design. The lateral footprint of the devices under investigation is around 16–18 μm, and it is enough to place around 25–30 Si / SiO2 units in the grating region (Fig. 2(a)). One can easily see that a non-uniform design needs more than 50 independent parameters to be properly described: the position and width of each SiO2 element, the etching depth, the BOX thickness, and the fibre position. A brute-force optimisation of such a structure would be prohibitive, and lacking physical insight. Instead, we split the task into three steps:
- the systematic optimisation of the uniform design;
- the optimisation of the linearly chirped design;
- a mutative refinement, which brings to the final apodized configuration.
A key feature of our approach is to take the etch depth as a free parameter, and to re-optimise it at steps 1 and 2 of the calculation. We adopt the commercial software Lumerical FDTD Solutions to perform 2D-FDTD simulations of the grating structures. More details on the numerical approach and on the convergence of these calculations are reported in the Appendix.
Referring to the notation of Fig. 2(a), in the first step we optimise a periodic structure characterized by a unique period p0 and SiO2 bars width w0. Four parameters enter in the optimisation sweep: the etching depth, the BOX thickness, the fibre position, and the duty cycle DC=w0/p0. The hierarchy of the sweep is E-B-fibre position-duty cycle. The grating period p0 is a variable parameter, which is tuned to bring the maximum of the CE spectrum at the target wavelength of 1550 nm (keeping the DC fixed).
The best CE of the uniform configurations is reported in Fig. 3(a) with a solid black line and symbols. In agreement with previous results [7, 21], the highest CE of 53.7% (−2.7 dB) is obtained for E=80 nm, B=2000 nm, p0=643.49 nm, DC=0.5, and a fibre offset of 4.1 microns. The fibre offset is indicated with respect to the centre of the first SiO2, which is placed at x=0.
In the second step of the optimisation we deal with a linearly chirped design. In this case, the inter-bar distance p0 is constant, but the SiO2 widths wi vary linearly along x to provide a better impedance matching at the junction between the grating and the un-patterned SOI waveguide. The minimum and maximum trench widths are denoted with wmin and wmax, respectively. The innermost part of the grating is uniform. For the UV-lithographic constraints, we impose wmin=100 nm. The best CE of the chirped designs are reported in Fig. 3(a) with dashed lines and symbols. The red one with open triangles refers to the un-constrained case, while the blue one with open squares refers to the constrained design. For the first case, the highest CE of 61.6% (−2.1 dB) is obtained with E=100 nm, B=2000 nm, p0=635.6 nm nm, wmax=190.68 nm nm, and a fibre offset of 6.95 μm. The constrained design has a slightly lower CE of 59.4% (−2.26 dB) with E=80 nm, B=2000 nm, p0=632.1 nm nm, wmax=252.85 nm, and a fibre offset of 4.6 μm.
To further increase the CE, in the last step the positions and centres of the oxide trenches are finely adjusted with a mutative refinement. The widths wi and positions pi are randomly varied around the starting values of the best linear chirp:Appendix. At each etching depth, 3000 mutation steps are applied to the best chirped structures of Fig. 3. The final results are reported in Fig. 3(a) with solid lines and closed symbols. The red line with closed triangles refers to the un-constrained design, while the blue one with closed squares refers to the design with lithographic constraints. For the un-constrained case, the best apodized GC has a CE of 64.65% (−1.9 dB) with E=100 nm. For the constrained case, the CE decreases to 61.9% (−2.08 dB), and it is achieved with E=220 nm (fully etched), B=2200 nm, and a fibre offset of 4.2 μm. These optimal configurations are marked with large black circles in Fig. 3(a). The bars widths wi and the inter-bars distances pi+1 − pi for these designs are reported in the panels (b) and (c) of Fig. 3. The pi and wi sequences for these configurations are also reported in Table 1. The positions of the centre of the fibre mode are indicated in Fig. 3(b) by vertical dashed lines with the corresponding color. A pink shadow represents the optical power associated to the Gaussian mode for the un-constrained design. In this case, we see that the SiO2 elements play different roles. The first trenches do not interact strongly with the incident light, and just provide impedance matching between the grating region and the un-patterned waveguide. The central elements, instead, interacts strongly with light, and are responsible for diffraction. The remaining grooves play a very minor role. From Fig. 3(a) we see that the maximum decrease in the CE due to the lithographic constraints is around 3.5% (−0.25 dB) only.
After this comprehensive investigation, we extract the following guidelines to optimise an apodized grating design starting from the information on the optimal uniform gratings already available in the literature :
- the etching depth has to be slightly increased (of the order of 20–30 nm) compared to the optimal value for the uniform grating;
- the BOX thickness is almost unchanged, only minor refinements are needed if the etching depth is increased;
- the fibre offset is in the range 4–7 μm, and it depends on the minimum trench width: For the uniform and constrained gratings, the fibre is closer to the edge of the grating.
Our mutative method improves the current record CE in 220 nm SOI by 4% absolute . However, the insertion losses are still far from the −1 dB goal, which is the benchmark for the market application of grating couplers . To be sure that we found the unique best apodized design in 220 nm SOI, we checked to confirm that the same optimal structure is reached starting from different linear chirps. This result is illustrated in Fig. 4, where we report the evolution of the CE starting from three different chirped configurations. The resulting sequence of the bars width after 3000 mutations is illustrated in the inset. From these results, it is evident that the final CE is capped to 65% (−1.9 dB), which is the global limit for 220 nm SOI. The final wi sequences are very similar, proving the robustness of the final design obtained with our method.
This final result, together with the growth of the CE observed in Fig. 3 for deeply-etched structures, dictates a clear strategy: Increase the SOI thickness and the maximum achievable etching depth to reach a higher efficiency.
3. Thicker SOI architectures for higher coupling efficiency
We now apply the same optimisation to the GC architectures in SOI with different Si thicknesses. The coupling efficiency at 1550 nm for the optimized 1D uniform gratings with different thicknesses is reported in Fig. 5(a) with a solid black line and squares . The CE increases with the SOI thickness, and reaches the maximum of 73.1% (−1.36 dB) for S=420 nm. By applying the optimisation guidelines derived in the previous section, we quickly found an un-constrained (wmin=0 nm) linearly chirped configuration for each SOI thickness. These configurations are then apodized by applying 3000 mutative steps: The final results are illustrated in Fig. 5(a) with a red line and dots. The optimal configuration is characterized by a thickness S=340 nm, E=200 nm, B=1950 nm, a fibre offset of 6.4 μm, and it reaches a CE of 88.2% (−0.55 dB).
To double-check this result, we applied our method also to the best pure SOI structure reported in the literature . This grating is obtained with an analytic formula that tunes the widths and positions of the SiO2 elements to maximise the overlap between the grating and the fibre modes. At a thickness of 340 nm, this design reaches a theoretical CE of 84% (−0.76 dB). The sequence of wi and pi reported in Ref.  is adopted also for thicknesses different from 340 nm. In these cases, a fast sweep over the etching depth, BOX thickness, and fibre position is performed before starting the apodization loop. If necessary, the entire lattice structure is rescaled to tune its response at 1550 nm. Then we apply 3000 mutative steps to these configurations: The final CE is reported in Fig. 5(a) with a blue line and triangles. We see that independently of the starting configuration, the mutative refinement produces the same trend and very similar CE values. The best structure is characterized by S=340 nm, E=200 nm, B=1950 nm, a fibre offset of 5.9 μm, and shows the highest CE of 89.3% (−0.49 dB). This result is more than 5% better than the previous record-efficiency in pure SOI . Moreover, the gap with respect to the absolute record-efficiency design with a bottom Al mirror  is reduced to less than 5%.
We checked that the high-performance of the apodized design is preserved also when deep-UV lithographic constraints are included. Following the same procedure illustrated in the previous section, we identified an efficient and constrained (wmin=100 nm) linear chirp for the optimal thickness S=340 nm. We then apply 3000 mutative steps: The resulting CE value of 84.8% (−0.72 dB) is reported in Fig. 5(a) with an open green square. We see that even after allowing for 193 nm UV-lithographic constraints, the apodized design in pure SOI still offers better than −0.75 dB coupling efficiency. The sequences of the SiO2 bars widths and the inter-bar distances pi+1 − pi are reported in Figs. 5(b) and 5(c) for the three high-performance apodized configurations with S=340 nm. These data are also reported in Table 1.
Although the trends and the final CE values of the two curves for the un-constrained apodized designs of Fig. 5(a) are very similar, from Figs. 5(b) and 5(c) we see that the optimal gratings for S=340 nm are characterized by slightly different wi and pi sequences. This fact suggests that further improvements may be possible, or that there could be several multi-mode gratings offering similar CE with different lattice structures.
To give a visual representation of the physical mechanisms behind the improved efficiency of the apodized couplers, we calculate the maps of the electric field component Ez for the uniform and apodized designs with S=340 nm. The latter is obtained from the linear chirp, red curve of Fig. 5(a). A field monitor is used to record the Ez(x, y, t) values in space and time. In this way we generate movies of the interaction of the fibre mode with our structures. These movies represent the electric field amplitude and are shown in the multimedia files Visualization 1 and Visualization 2 for the uniform and un-constrained apodized designs in 340 nm SOI, respectively.
At the target wavelength of 1550 nm, we calculated the Fourier transform of the Ez(x, y, t) signal over the simulation box. The result is a plot of the Ez(x, y) profile under continuous wave excitation at λ =1550 nm, which is conceptually equivalent to those obtained with Eigenmode Expansion Methods [4, 7, 11, 12]. The Ez(x, y) plots are reported in Figs. 6(a) and 6(b) for the uniform and apodized configurations. Three main differences emerge from this comparison:
- the impedance matching at the junction between the grating and the un-patterned SOI waveguide is substantially improved, as it is evident from the reduced scattered field in the BOX and TOX for x <−3 μm;
- the grating-to-fibre injection is single-mode in the apodized design, while this is not the case for the uniform design;
- the transmission losses are greatly reduced thanks to the apodization, as it is evident by comparing the Ez amplitudes in the BOX region.
We checked the impact of fabrication imperfections on the un-constrained apodized design in 340 nm SOI. By means of 2D-FDTD simulations we found that a reduction (increase) of the etch depth determines a redshift (blueshift) of the CE spectrum. For a 10 nm reduction (E=190 nm), the redshift is 10 nm. When the etch depth is varied by ± 20 nm, the maximum decrease in the CE is 5% absolute (−0.22 dB). A similar trend is obtained by applying a global reduction / increase in the SiO2 bars widths. The CE spectrum undergoes a redshift (blueshift) of approximately 11 nm when a 10% reduction is applied. The maximum CE is substantially unaffected. By shifting the fibre position along the grating (x direction in Fig. 2(a)), we calculate a relaxed −1 dB spatial window of 4.5 μm.
The optimal SOI thickness of 340 nm allows for an ultra-high grating efficiency, but it is not single TE-mode. To integrate the coupler in a standard 220 nm photonic circuit, a taper for adiabatic mode conversion is required. This has been considered in the literature, for example using a linear V-shaped taper which yields a negligible insertion loss when the taper length is adequately chosen . By using this or similar approaches, our 340 nm grating design can be straightforwardly incorporated into the standard 220 nm SOI architecture.
The main results of this work are summarized in Fig. 7, where we compare the CE of the best uniform, linearly chirped and apodized gratings for the relevant SOI thicknesses of 220 and 340 nm. Using our general optimisation method, we have shown that the coupling efficiency of GCs without bottom-reflectors in the 220 nm SOI platform is capped to 65%. The spatial apodization provides an absolute +11% improvement compared to the best uniform design. The maximum CE value for the 220 nm thick SOI platform is below the goal of −1 dB (80%) for the market application of grating couplers. To surpass this value, it is necessary to increase the thickness of the grating region.
The best performing GC designs are identified in 340 nm SOI, where our apodization scheme generates un-constrained designs with coupling efficiencies of 89% (−0.5 dB). An efficiency of 85% is reached even after accounting for lithographic fabrication constraints (minimum feature size of 100 nm). This result clearly point out that a high coupling efficiency can be achieved in a pure SOI platform without any bottom reflector element. The 340 nm SOI design could be transferred to existing multi-project wafers foundry runs, with only very minor changes to current deposition and etching recipes. This creates the potential for researchers and SMEs working in the field of Si-Photonics to access low-cost, high-performance, fully CMOS-compatible couplers with less than −1 dB insertion loss.
Appendix: Computational details
In this section we illustrate two computational aspects of our investigation: (i) the numerical convergence of 2D-FDTD simulations of apodized gratings, and (ii) the optimal mutation parameters that ensure the fastest convergence of the method to the apodized structure with the highest efficiency.
We adopted the commercial software Lumerical FDTD Solutions to calculate the fraction of power that is coupled to the TE modes of the un-patterned SOI waveguide (Fig. 2(a)). Since apodized structures do not have a definite spatial periodicity, we adopted a 2D adaptive mesh along x. The cells are more dense in the high-index silicon regions and at the interfaces between Si and SiO2. The mesh accuracy is described by a single parameter, the mesh level, which varies between a minimum of 1 (low accuracy) and a maximum of 8 (high accuracy). Even with the highest resolution, the calculation of a CE spectrum over 200 energy points takes around 20 seconds on a standard workstation equipped with 8 cores at 2.8 GHz and 64 Gb of RAM memory. Along the y-direction the mesh has to be properly snapped to the horizontal interfaces. To do this, we adopted two mesh override regions. The first one encloses the SOI region, while the second one lies across the Si / SiO2 interface between the BOX and the substrate. In these regions, a uniform mesh overwrites the adaptive one along y. The vertical mesh step Δy is 10 nm, so S and E must be integer multiples of this value.
The convergence of our 2D-FDTD simulations is illustrated in Fig. 8. We report the wavelength of the maximum CE (left axis) and the maximum CE (right axis) calculated with different mesh levels for the apodized design in 340 nm SOI that we present in Fig. 5 with a red line and symbols. A low mesh level leads to inaccurate results, especially for what concerns the tuning of the response at 1550 nm. The situation improves by moving to more accurate settings: When the mesh level is in the high-accuracy range (level 7 and 8), the system is correctly tuned at 1550 nm, and the CE shows just small variations of the order of 0.1%. In the rest of the paper, we adopted the mesh level 8, which is the maximum supported by the software.
Genetic methods have already been applied for the optimisation of apodized 1D GCs . However, the optimal parameters of the method and the ultimate CE efficiency for a given SOI thickness were not discussed. To investigate these aspects, we applied the mutative refinement to the unconstrained linearly chirped structure with S=220 nm and E=100 nm using five different assignments for Δp and Δw. The results are reported in Figs. 9(a–e) for the cases Δp=Δw=1, 2, 5, 10, and 20 nm, respectively. We report the CE of the current design with a black line and symbols, and the the best CE with a red line and symbols. The maximum CE achieved after 3000 mutations is reported in Fig. 9(f). When the mutation amplitude is very small (1 nm, panel (a)), each mutated configuration is close to the previous one. The curve for the current CE shows just tiny ripples, and the best CE undergoes a steady but slow growth. For large mutation amplitudes (Δp=Δw=10 and 20 nm), instead, the current CE is very scattered, and the best CE shows abrupt jumps followed by long plateaus. As a results, also in this case the convergence is slow because the search is too random. The plot in Fig. 9(f) gives a visual representation of this trade-off, which determines the optimal mutation rate Δp=Δw=2 nm. This value gives the fastest convergence to the configuration with the highest efficiency, and it is used also in the rest of the work.
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