We report on a path-independent insertion-loss (PILOSS) 8 × 8 matrix switch based on Si-wire waveguides, which has a record-small footprint of 3.5 × 2.4 mm2. The PILOSS switch consists of 64 thermooptic Mach-Zehnder (MZ) switches and 49 low-crosstalk intersections. Each of the MZ switches and intersections employs directional couplers, which enable the composition of a low loss PILOSS switch. We demonstrate successful switching of digital-coherent 43-Gbps QPSK signal.
© 2014 Optical Society of America
Continuous increase of the network traffic is expected for the future due to the spread of ultrahigh-definition video format (e.g., 4-K, 8-K) and mobile data traffic increases . Since the present network technology suffers from the increase of electric power consumption of network equipment accompanied by the traffic increase, future network technology should resolve such an energy bottleneck in order to be scalable and sustainable. In other words, it should be capable of handling several orders of magnitude larger network traffic with lower power consumption than that of the present. One plausible approach is the dynamic optical path network (DOPN) [2, 3]. The DOPN is based on the fast optical circuit switching, in which high-port-count N × N optical switches play an essential role. However, the realization of high-port-count optical switches with admissible cost has been a challenge over the past decades. Silicon photonics is a promising technology to achieve such optical switches as it offers a platform to realize efficient, mass-producible and hence low-cost, highly integrated, and small-footprint optical devices.
A waveguide-based integrated N × N optical switch can be formed by using a certain number of 2 × 2 element switches. Each of the element switches in an N × N switch is set to either OFF or ON state by changing the applied electric power. Proper design can make the element switch ‘normally’ OFF (the switch with no electric power applied is in OFF state). Therefore, the total power consumption of an N × N switch is determined by the number of the element switches in ON state. One standard N × N switch topology is called a path-independent insertion-loss (PILOSS) topology [4, 5], in which the switch consists of the matrix of 2 × 2 element switches. In the PILOSS topology, light always passes through N element switches and N−1 intersections, thus experiences the equal attenuation for all the N 2-ways of paths. The number of ON state element switches is N in the PILOSS topology. Another standard N × N switch topology is a “switch-and-select” topology, in which the switch is built by connecting the arrays of 1 × N switch units. Recently, switches of this topology have been demonstrated on silicon-on-insulator (SOI) [6, 7] and InP  platforms. The number of ON state element switches varies depending on a path setting, and the average number of ON state element switches is proportional to (log2N) N. Due to less ON state element switches, the PILOSS topology is more energy-efficient. For this reason, the PILOSS topology is believed to be most promising towards larger N.
In SOI platforms, a Si 8 × 8 PILOSS switch has been demonstrated with thick (1.5 μm) Si rib-waveguides . A smaller switch can be fabricated with Si-wire waveguides on thin (200 – 300 nm) SOI. The thin SOI is also an important platform for monolithic integration of electronic devices and circuit [9–12], and a blocking 8 × 8 switch integrated with driver electronics has been reported recently .
In this paper, we report on the first demonstration of an 8 × 8 strictly-non-blocking PILOSS switch using Si-wire waveguides, to the best of our knowledge. It has a record-small footprint of 2.4 × 3.5 mm2, which is 1/4 compared with the PILOSS switch based on the thick Si-rib waveguides . On-chip loss is 6.5 dB, and crosstalk is as low as −23.1 dB. To demonstrate its performance for circuit switch applications, we evaluate switching of digital-coherent 43-Gbps QPSK signals.
2. Fabricated matrix switch
The 8 × 8 PILOSS switch chip was fabricated by using e-beam lithography and CMOS-compatible process. Figure 1(a) is a microscope image of the fabricated PILOSS switch chip including 64 Mach-Zehnder (MZ) switches and 49 intersections. The Si-wire waveguide is 430-nm wide and 220-nm high, buried by SiO2 cladding. The 3-dB splitter/combiner of the MZ switch is a directional coupler (DC), which is designed for the transverse-magnetic (TM) mode that provides a larger fabrication tolerance than the transverse-electric mode case. Each arm of the MZ switch has a thermooptic phase-shifter with a TiN heater. The footprint of the PILOSS switch is 3.5 × 2.4 mm2, which is 1/550 as small as that of the silica-PLC PILOSS switch , and 1/4 as small as that of the thick Si rib-waveguide based PILOSS switch .
The PILOSS switch chip was die-bonded on a ceramic mount as shown in Fig. 1(b), then electrode pads on the chip were wire-bonded to the fan-out electrical interconnects on the mount. The heaters were controlled through an external heater driver. Optical fiber arrays were butt-coupled to the waveguide chip through the spot-size converters (SSCs) fabricated at the edges of the chip. The coupling loss between the SSC and fiber was estimated to be 3.6 dB/facet from fiber-to-fiber insertion loss (10.4 dB) and propagation loss (3.2 dB/cm × 1.0 cm = 3.2 dB) of a reference Si-wire waveguide on the same chip.
3. Results and discussion
3.1 Mach-Zehnder switch and intersection elements
Figure 2(a) shows a test MZ switch, which has an identical structure to those composing the PILOSS switch and is placed adjacent to the PILOSS switch on the same chip. The MZ switch has thermooptic phase shifters with TiN heaters, and the 3-dB splitter/combiner of the MZ switch is a DC. Figures 2(b) and 2(c) show the transmission spectra in the cross state and the bar state, exhibiting −45 dB and −42 dB crosstalk at a wavelength of 1.55 μm, respectively. These performances are much higher than those of a thick Si-rib switch reported as −25 dB . A test intersection was also fabricated on the same chip as shown in Fig. 3(a). The intersection is a standard DC that is used in an upright orientation . The bar and the cross port transmission spectra shown in Fig. 3(b) exhibit −38 dB crosstalk at a wavelength of 1.55 μm.
3.2 Loss and its breakdown
The losses of all 64 paths were evaluated at a wavelength of 1.55 μm. Figure 4 illustrates the measurement setup. Light is launched to one input port, and then a path that starts from the input port was formed by properly choosing one element switch and turning it on. Powers from all the output ports were measured with eight photodiodes. The output power at one particular port that terminates the path yields the insertion loss of the path, whereas the other seven output powers yield optical leakages to the output ports that are off the path. By changing the ON-state switch, we scan the output port that is connected to the input port from one port to next, while recording the transmitted power and leaked powers. We repeat this cycle, while changing the input port, from one to next.
The measured losses are shown in Fig. 5. The average on-chip loss is 6.5 ± 1.0 dB, where the on-chip loss is defined as the loss without the coupling loss. This small loss variation clearly warrants the merit of the PILOSS topology. Relatively larger losses are measured for the paths with a specific input/output port. This suggests that the residual loss variation is mainly caused by the coupling efficiency variation.
The losses of the MZ switch and of the intersection can be estimated from the average on-chip loss. The chip includes 5.6-mm long lead part of the waveguide. Subtracting the propagation loss, 1.8 dB, we obtain 4.7 dB as the insertion loss of the PILOSS switch. Each path contains eight MZ switches and seven intersections such that the average on-chip loss is expressed as 8LMZ + 7Lint = 4.7, where LMZ and Lint are the on-chip losses of the MZ switch and the intersection, respectively. Assuming that the on-chip loss is proportional to the propagation length of the device, LMZ = 3Lint, where the propagation length of the MZ switch is three-times longer than that of the intersection in our design. From the two relations, LMZ and Lint are calculated to be 0.5 dB and 0.2 dB, respectively. These small losses are due to the use of the DCs as the 3-dB splitter/combiner of the MZ switch and the intersection.
For evaluating crosstalk performance, it is, in principle, necessary to couple light to all the eight input ports. In fact, we did such an “all-input” measurement. In this section, we show that it is possible to obtain a good approximation of the result of the “all-input” measurement from the data of one-input measurements. Let us consider the crosstalk at output port 8 in switch State #39265, which includes paths of 1 (input) −8 (output), 2-7, 3-6, 4-5, 5-4, 6-3, 7-2, and 8-1, as shown in Fig. 6(a).From the measurement results of the 1-8, 2-7, …, and 8-1 paths, we already have PL(2,8), PL(3,8), …, and PL(8,8) and P8 as shown in Fig. 6(b), where PL(i,j) is leaked power from the input port i to the output port j, and Pj is main-path output power from the output port j. Then, the crosstalk at output port 8 is calculated fromFigure 6(c) compares the estimated crosstalk with the result of a measurement with the “all-input” case, where light was really launched to all the eight input ports at the same time. The estimated crosstalk is in good agreement with the “all-input” measurement. This agreement is not trivial, but it is reasonable if signal mixture occurs more in element switches than in intersections. This presumption seems to be the case, because crosstalk degradation is significant in element switches, as we shall discuss below. We emphasize that it is a great advantage to be able to estimate the crosstalk of N! states from N 2 times of measurement.
Figure 7(a) plots the crosstalk that was estimated in the manner as described above for all switch states (8! = 40,320). The crosstalk is lower than −18.3 dB, and its median is −23.1 dB. Figure 7(b) reconfigures (a) to histogram, illustrating that 99% of the crosstalk is lower than −20 dB. Ideally, eight MZ switches and seven intersections connected in series are supposed to have crosstalk of −29 dB, if each switch and intersection has a crosstalk performance in Figs. 2 and 3. Crosstalk in Fig. 7 is, however, not as good as this. The deterioration originates from the switch-to-switch variation of the minimum-crosstalk wavelength. To evaluate such wavelength variation, we measured the wavelength dependence of the crosstalk by focusing on the input port 1 to the output port 8 in State #39265. The experimental setup is the same as the one shown in Fig. 4. The PILOSS switch was set to State #39265 at a wavelength of 1.55 μm, then the output power from the port 8 and the leaked powers to the other ports were measured while changing the input wavelength by 2.5-nm separations. Using the obtained data, the crosstalk at each wavelength was calculated in the same manner as described above. Figure 8 plots the results. The lowest crosstalk is −25.1 dB at a wavelength of 1.55 μm, where the switch-to-switch variation of the minimum-crosstalk wavelength is estimated to be approximately 5 nm. Allowing −20 dB crosstalk, the transmission bandwidth is 7.5 nm.
3.4 Switching of digital-coherent QPSK signal
We evaluated the switching of the signal between two switch states shown in Fig. 9.. A 43-Gbps QPSK signal (PRBS 231 – 1) was generated at a wavelength of 1.55 μm by using a clock source, a pulse-pattern generator, a tunable laser diode, and an IQ modulator. The QPSK signal was launched to the PILOSS switch with the state of polarization adjusted so as to excite only TM-mode of the waveguide. We set two switch states, #39265 and #36279, as shown in Fig. 9. Before the receiver, the optical signal-to-noise ratio (OSNR) of the output signal was adjusted to 13 dB for bit-error-rate (BER) measurement or 20 dB for constellation analysis by using a variable optical attenuator and a preamplifier. The OSNR-adjusted signal was detected by balanced photo-detectors after mixing local light at a 90-degree optical hybrid circuit, and analyzed with an optical modulation analyzer (Agilent, N4391A and DSO-X92004A), where carrier recovery was only enabled in the signal demodulation process. The BER of the bit sequence of 231 − 1 was measured directly, and the error-vector-magnitude (EVM) was obtained from the constellation diagram. Figure 10 shows the measured BER of each output port for States #39265 and #36279. There are almost no significant signal penalties, indicating that the PILOSS switch is capable of switching 43-Gbps QPSK signal. This switching capability can also be confirmed from constellation diagrams shown in Fig. 11.
We have demonstrated the 8 × 8 strictly-non-blocking PILOSS switch based on Si-wire waveguide, which was fabricated using e-beam lithography and CMOS-compatible process. The PILOSS switch includes 64 MZ switches and 49 intersections, whose footprint is 3.5 × 2.4 mm2. The on-chip loss is 6.5 ± 1.0 dB, and the crosstalk is around −23.1 dB. We also showed successful switching of the digital-coherent 43-Gbps QPSK signal. Although the wavelength and polarization dependence of the PILOSS switch are yet issues to be solved , these results demonstrate that the Si-wire based PILOSS switch can be a good candidate for the high-port-count strictly-non-blocking matrix switch in the integrated form.
This work was partly supported by Project for Developing Innovation Systems of MEXT, Japan. Authors are grateful to Messrs. K. Tashiro and K. Saitoh for their technical assistance in device fabrication.
References and links
1. Cisco Systems, Inc., “Visual networking index: Global mobile data traffic forecast update, 2012–2017,” http://www.cisco.com/en/US/solutions/collateral/ns341/ns525/ns537/ns705/ns827/white_paper_c11-520862.html.
2. S. Namiki, T. Kurosu, K. Tanizawa, J. Kurumida, T. Hasama, H. Ishikawa, T. Nakatogawa, M. Nakamura, and K. Oyamada, “Ultrahigh-definition video transmission and extremely green optical networks for future,” IEEE J. Sel. Top. Quantum Electron. 17(2), 446–457 (2011). [CrossRef]
3. K. Ishii, J. Kurumida, S. Namiki, T. Hasama, and H. Ishikawa, “Energy consumption and traffic scaling of dynamic optical path networks,” Proc. SPIE 8646, 86460A (2012). [CrossRef]
4. T. Goh, A. Himeno, M. Okuno, H. Takahashi, and K. Hattori, “High-extinction ratio and low-loss silica-based 8 × 8 strictly nonblocking thermooptic matrix switch,” J. Lightwave Technol. 17(7), 1192–1199 (1999). [CrossRef]
5. S. Sohma, T. Watanabe, N. Ooba, M. Itoh, T. Shibata, and H. Takahashi, “Silica-based PLC type 32 × 32 optical matrix switch,” in European Conference and Exhibition on Optical Communication, OSA Technical Digest (online) (Optical Society of America, 2006), paper Tu.4.4.3. [CrossRef]
6. S. Nakamura, S. Takahashi, M. Sakauchi, T. Hino, M. Yu, and G. Lo, “Wavelength selective switching with one-chip silicon photonic circuit including 8 × 8 matrix switch,” in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optical Society of America, 2011), paper OTuM2. [CrossRef]
8. M.-J. Kwack, T. Tanemura, A. Higo, and Y. Nakano, “Monolithic InP strictly non-blocking 8×8 switch for high-speed WDM optical interconnection,” Opt. Express 20(27), 28734–28741 (2012). [CrossRef] [PubMed]
9. G. W. Cong, T. Matsukawa, T. Chiba, H. Tadokoro, M. Yanagihara, M. Ohno, H. Kawashima, H. Kuwatsuka, Y. Igarashi, M. Masahara, and H. Ishikawa, “Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch,” Opt. Express 21(6), 6889–6894 (2013). [CrossRef] [PubMed]
10. S. Assefa, X. Fengnian, W. M. J. Green, C. L. Schow, A. V. Rylyakov, and Y. A. Vlasov, “CMOS-integrated optical receivers for on-chip interconnects,” IEEE J. Sel. Top. Quantum Electron. 16(5), 1376–1385 (2010). [CrossRef]
11. A. Narasimha, B. Analui, L. Yi, T. J. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. G. M. P. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, S. Dan, and T. Pinguet, “A fully integrated 4 × 10-Gb/s DWDM optoelectronic transceiver implemented in a standard 0.13 μm CMOS SOI technology,” IEEE J. Solid-State Circuits 42(12), 2736–2744 (2007). [CrossRef]
12. K. Suzuki, H. C. Nguyen, T. Tamanuki, F. Shinobu, Y. Saito, Y. Sakai, and T. Baba, “Slow-light-based variable symbol-rate silicon photonics DQPSK receiver,” Opt. Express 20(4), 4796–4804 (2012). [CrossRef] [PubMed]
13. B. G. Lee, A. Rylyakov, W. M. J. Green, S. Assefa, C. W. Baks, R. Rimolo-Donadio, D. Kuchta, M. Khater, T. Barwicz, C. Reinholm, E. Kiewra, S. Shank, C. Schow, and Y. A. Vlasov, “Four- and eight-port photonic switches monolithically integrated with digital CMOS logic and driver circuits,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference 2013, OSA Technical Digest (online) (Optical Society of America, 2013), paper PDP5C.3. [CrossRef]
14. Y. Shoji, K. Kintaka, S. Suda, H. Kawashima, T. Hasama, and H. Ishikawa, “Low-crosstalk 2 x 2 thermo-optic switch with silicon wire waveguides,” Opt. Express 18(9), 9071–9075 (2010). [CrossRef] [PubMed]
15. S.-H. Kim, Y. Shoji, G. Cong, H. Kawashima, T. Hasama, and H. Ishikawa, “Polarization diversity 2×2 switch with silicon-wire waveguide,” in European Conference and Exhibition on Optical Communication, OSA Technical Digest (online) (Optical Society of America, 2013), paper We.4.B.5.