Low-frequency noise and hole lifetime in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are analyzed, considering their use in photon detection based on single-hole counting. The noise becomes minimum at around the transition point between front- and back-channel operations when the substrate voltage is varied, and increases largely on both negative and positive sides of the substrate voltage showing peculiar Lorentzian (generation-recombination) noise spectra. Hole lifetime is evaluated by the analysis of drain current histogram at different substrate voltages. It is found that the peaks in the histogram corresponding to the larger number of stored holes become higher as the substrate bias becomes larger. This can be attributed to the prolonged lifetime caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small absolute substrate bias is favorable for short lifetime and low noise, leading to high-speed operation.
© 2014 Optical Society of America
A type of single-photon detector, which directly counts photo-generated and stored (or trapped) single charges by a sensitive electrometer, is drawing attention because of its potential as a photon-number-resolving detector [1–8]. Quantum dot field-effect transistor (QDFET) [2–4] utilizes the GaAs/AlGaAs two-dimensional electron gas (2DEG) channel as an electrometer to detect the photo-generated and trapped holes in the InAs self-organized QDs. Single-electron photodetector (photo-SET) [5,6] with nanocrystal silicon (nc-Si) dots formed by the deposition and annealing of Si-rich oxide utilizes single-electron transistor (SET) as an electrometer to detect photo-generated single charges trapped in the dot or Si/oxide interface. We have also studied the scaled-down silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) [7,8], in which photo-generated holes are stored below the negatively biased gate, and are detected as changes in the bottom-channel electron current. This SOI MOSFET is practically very attractive in that it can be manufactured by the standard Si integrated circuit technology and features small dark counts of ~10−2 s−1 at room temperature, but issues remain such as low quantum efficiency (QE) and the slow operation speed , and this report intends to address the latter.
There are two main factors affecting the operation speed. One is the drain current noise. If the noise spectral density, the required signal-to-noise ratio for discriminating the current levels, and the charge sensitivity (change in the drain current) to a single hole are SId [A2/Hz], SNR, and ΔId [A/hole], respectively, the maximum count rate can be roughly estimated as (ΔId/SNR)2/SId [s−1] indicating the low noise is required for high-speed operation. The other factor is the hole lifetime in the body of SOI MOSFET. In order to avoid the saturation of the number of stored holes at a high photon incident rate, short lifetime is desirable as long as the short output pulses can be resolved. In this report, we will describe the behavior of the drain current noise and the hole lifetime under different substrate voltages in search of optimum operation condition of the SOI MOSFET as a photon detector.
Although the original SOI MOSFET photon detector  had a special double-gate structure with a short lower gate (LG) and a long upper gate (UG) covering the p−-doped offset area between LG and n+-doped source/drain, we select the ordinary n-channel fully-depleted (FD) SOI MOSFET without offset region  as shown in Fig. 1 considering its structural simplicity and versatility, and the device is fabricated in a 300-mm-wafer facility for Si integrated circuits to ensure the reproducibility.
It has n+ poly-Si-gate and p− channel region with dopant concentration less than 1015 cm−3. The SOI is of a wafer-bonding type supplied by Soitec S.A . Thicknesses of buried oxide, SOI and gate oxide are 145, 50 and 5 nm, respectively. The gate length is fixed at 300 nm, and the channel width is varied among 90, 95 and 110 nm. In the noise measurement and the hole lifetime analysis, we changed the substrate voltage Vsub, while keeping the drain current at the constant level of 1 nA by adjusting the front gate voltage Vg. The drain current noise was measured in dark condition at 300 K, and the hole lifetime was evaluated by the analysis of drain current histograms for different levels of light intensity also at 300 K.
3. Results and Discussion
3.1. Analysis of drain current noise
Figure 2 shows an example of Id-Vg characteristics with Vsub as a parameter ranging from −10 to 10 V. Drain voltage Vd is kept at 50 mV. From these data, front-gate threshold voltage Vth corresponding to the Id of 1 nA is extracted for setting the operation condition and further analysis. Figure 3 shows noise power for the bandwidth of 5 Hz, and the threshold voltage Vth plotted against the substrate voltage for various channel widths. In the Vth-Vsub characteristics, the deflection point 1 corresponds to the transition point between front- and back-channel operations, and the deflection point 2 to the transition between inversion and accumulation conditions at the buried oxide/substrate interface .
The noise levels show horseshoe shape, and become low at around the deflection point 1 and in the back-channel region between deflection points 1 and 2. This behavior is common for three different channel widths W, although a slight inverse narrow-channel effect , i.e. the reduction of Vth for smaller W, can be seen.
Figure 4(a) shows the drain current noise spectra for front-channel operation. The drain current was kept at 1nA (substreshold operation), while the substrate voltage was varied from −10 to −3V. At Vsub = −3V the usual 1/f noise spectrum is observed, which can be explained by the McWhorter's model  based on the charge fluctuation in the slow oxide traps near the Si/oxide interface caused by the carrier tunneling to and from the inversion channel, and moreover includes the contributions of both front and back interfaces (coupling effects) in the present case of FD SOI MOSFET .
As the Vsub decreased, an excess Lorentzian noise begin to evolve at Vsub = −5V which corresponds to a weakly accumulated back interface, when the magnitude of Vsub increases the noise spectra asymptotically approach a single 1/f 2 line, indicating that the Lorentzian plateau level and time constant increase simultaneously. Figure 4(b) shows the noise spectra for back-channel operation in −3 ≤ Vsub ≤ 4V. The similar behavior of the evolution of the noise spectra can be observed, when the front interface is driven toward accumulation.
In SOI MOSFET, the Lorentzian excess noises are often associated with the body potential fluctuation caused by several mechanisms of majority carrier generation [13–15], such as (a) impact ionization, (b) gate-induced drain leakage (GIDL) and other drain-body junction leakage, (c) tunneling through a thin gate oxide, (d) tunneling between back-gate-induced (BGI) accumulation layer and source/drain region, etc. However, these floating-body (FB) induced excess noises are not likely in the present device primary due to its FD operation, in which lower potential barrier at the source/body junction alleviates the accumulation of the majority carriers. In addition, low drain voltage of 50 mV, nearly symmetric behavior of the noise with respect to Vsub, and thick gate oxide of 5 nm are also incompatible with the mechanisms (a), (b), and (c), respectively. BGI Lorentzian noise (d) was actually reported in FD SOI MOSFET , but the Lorentzian time constant decreased as |Vsub| increased, which contradicts the behavior observed in the present experiment. Apart from the above FB mechanisms, D. S. Ang, et al. reported the very similar evolution of the noise spectra in the transition from FD to near FD operation, caused by the generation-recombination (GR) processes at bulk defects in the depleted SOI layer . In our device, as can be seen in Fig. 4 (a) and (b), the asymptotic 1/f2 lines for both negative and positive Vsub, i.e. front- and back-channel operations, are quantitatively the same. This symmetric behavior strongly suggests the origin of the GR noise in the present device is not located at the front or back interface, but in the depleted SOI layer. This observation also excludes the possibility of random telegraph signal (RTS) , which is caused by the charge fluctuation in a single oxide trap and possibly shows the Lorentzian spectrum, because the individuality of the oxide traps in energy level and location in the oxide cannot lead to the common noise spectrum for both front- and back-channel operations.
3.2. Analysis of hole lifetime
Figure 5 shows typical drain current waveforms for different levels of light intensity at the wavelength of 550 nm. Baseline current is adjusted to 1 nA by Vg, and each waveform is shifted for clarity. Vd and Vsub, are 0.05 and 1.49 V, respectively. In this figure, we can see that the photo-generated holes modulate the drain current to discrete levels corresponding to the number of stored holes below the gate nh, while the operating condition is set to Vg< 0 and Vsub> 0, so that the electrons flow in the back-channel. Note that, in dark condition, we could not observe signal exceeding the level of nh = 1, or RTS-like behavior. Actually, the randomness in the waveforms of Fig. 5 is caused by the statistical fluctuation of the photon arrival (hole generation) and hole recombination, which follow the Poisson process.
As described in , the evolution of the state probability corresponding to each nh can be explained well by the rate equation taking the hole generation and recombination rates into account, and this is the basis of the hole lifetime analysis.
Figure 6 shows the histograms of drain current for (a) Vsub = 1.27 V, (b) Vsub = 1.49 V, (c) Vsub = 1.72 V, and (d) Vsub = 1.93 V with different Vg to keep the baseline drain current at the same level of 1 nA. The closed symbols are obtained data and solid lines are fitting curves with Gaussian distribution. The peaks from left to right correspond to the number of stored holes of 0, 1, 2 and 3. It can be seen that the peaks in the histogram corresponding to the larger number of stored holes become higher as the Vsub increases. This may be caused by the longer hole lifetime, higher light absorption efficiency or higher collection efficiency of the photo-generated holes.
In order to understand the bias dependence of the light absorption and hole collection, hole generation rate is plotted against the light intensity in Fig. 7. There is proportionality between hole generation rate and incident light intensity regardless of Vsub, indicating that light absorption or hole collection efficiencies is not much changed by the bias condition. This also means that the hole lifetime can be controlled without affecting the nominal QE (as defined by the fraction of photons entering the detection area that are counted), which amounts to 0.15% in this case assuming the detection area of 300 × 110 nm2.
The hole lifetimes are obtained as fitting parameters to describe the evolution of drain current histogram based on the rate equation under steady state conditions, fi / τi = fi-1 R and Σ fi = 1, where τi and fi are hole lifetime and probability of state corresponding to hole number i, and R is hole generation rate . The hole lifetimes at different Vsub are depicted in Fig. 8. It can be seen the hole lifetime increases significantly as Vsub increases. It is estimated that higher Vsub (higher transverse electric field) separates the stored hole and electron more effectively, and reduces the probability of recombination, leading to the longer lifetime.
In case of QDFET, the hole lifetime in InAs QDs is longer than a hundred seconds, and a reset gate pulse is necessary for refilling the dots with electrons after illumination [3,4]. In the photo-SET, electron lifetime in the nc-Si dots (detection time) can be as long as 350 s at a specific temperature with the contribution of Si/oxide traps . In the present SOI MOSFET, hole lifetime is much shorter probably due to the bulk defects in the SOI layer as estimated in the previous section, the presence of channel electrons in a short distance, and the lose confinement of holes in the shallow potential well created by the pn junction and gate electric field. The short lifetime is beneficial in that the device does not require reset operation, but there might be some difficulty in controlling the lifetime to an appropriate value. The contribution of the Si/oxide interface traps  to the hole lifetime seems to be small considering the fact that the lifetime becomes longer for higher transverse electric field that makes the hole distribution closer to the interface.
It is worthwhile to compare other performance indices of the QDFET and SOI MOSFET. The QE of QDFET is reported to be 0.14%  and comparable to 0.15% of the present SOI MOSFET. There are common issues in the small light absorption in thin active layer, and low transmittance of the metallic gate. Higher QE may be attained by the introduction of a resonant cavity structure and more transparent gate material. The dark count rate in the SOI MOSFET is less than 0.2 s−1 (no signal in the observation time of 5 s) at 300 K, and this outperforms the 10−8 ns−1 of the QDFET at 77 K , indication the SOI MOSFET is suitable to applications where the photon arrival time is not known.
3.3. Operation speed
Operation speed of the single-photon detection, i.e. maximum count rate, is limited by the noise and the hole lifetime as described in the Introduction. According to the results in Sections 3.1 and 3.2, the small |Vsub| leads to high-speed operation owing to the low noise and short lifetime. It can be seen in Fig. 3 that the minimum noise power for the band width of 5 Hz is 7 × 10−25 A2 (SId is 1.4 × 10−25 A2/Hz). ΔId is found to be 29 pA as the peak-to-peak spacing in Fig. 6. If we assume the required SNR of 10 dB ( = 3.16), the maximum count rate (ΔId/SNR)2/SId becomes 600 s−1. Figure 8 also indicates that the minimum hole lifetime τ1 of 2 × 10−3 s makes the maximum count rate to be about 500 s−1 ( = 1/τ1) to avoid the excessive accumulation of holes. In order to improve these values, ΔId could be increased by further down-scaling of the device sizes, and τ1 could be reduced by introducing defects.
Low-frequency current noise in SOI MOSFET was analyzed for photon detection under different Vsub's. It was found that the noise in the SOI MOSFET became low at the transition point between the front- and back-channel operations, and in the back-channel region near the transition point. On both sides, the noise spectra asymptotically approached a single 1/f 2 line, indicating that the Lorentzian plateau level and time constant increase simultaneously presumably due to the GR processes at bulk defects in the SOI layer. In order to understand the Vsub dependence of the hole lifetime, the drain current histograms of the SOI MOSFET were analyzed at different Vsub's and light intensities. It was found that the peaks in the histogram corresponding to the larger number of stored holes became higher as the Vsub decreased. This was attributed to the prolonged hole lifetimes caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small |Vsub| is favorable for short lifetime and low noise, leading to high-speed operation.
The Authors are indebted to Keisaku Yamada of University of Tsukuba, Toyohiro Chikyo of National Institute of Materials and Science, Tetsuo Endoh of Tohoku University, Hideo Yoshino and Shigeru Fujisawa of Semiconductor Leading Edge Technologies, Inc. for their cooperation in the device fabrication. This research was supported by Japan Society for the Promotion of Science Grant-in-Aid for Scientific Research 25286068.
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