Abstract: We demonstrate a novel on-chip two-mode division multiplexing circuit using a tapered directional coupler-based TE0&TE1 mode multiplexer and demultiplexer on the silicon-on-insulator platform. A low insertion loss (0.3 dB), low mode crosstalk (< −16 dB), wide bandwidth (~100 nm), and large fabrication tolerance (20 nm) are measured. An on-chip mode multiplexing experiment is carried out on the fabricated circuit with non return-to-zero (NRZ) on-off keying (OOK) signals at 40 Gbit/s. The experimental results show clear eye diagrams and moderate power penalty for both TE0 and TE1 modes.
©2013 Optical Society of America
On-chip optical interconnections based on silicon-on-insulator (SOI) nanowires are a promising technology for future massively-parallel chip multiprocessors . Compared to traditional copper wire-based electrical interconnects, silicon-based on-chip optical interconnects offer broad bandwidth, allowing to reach very high capacities using the wavelength-division multiplexing (WDM) technology . Mode-division multiplexing (MDM) offers a new dimension to increase the capacity of SOI optical links . The key to realize on-chip MDM is an efficient mode (de)multiplexer. On-chip mode multiplexers based on weakly guiding asymmetrical Ψ- and Y- junctions have been suggested [4–7]. Multimode interferometers have also been proposed as mode multiplexers [8, 9]. Recently, mode multiplexers based on asymmetrical directional couplers (DCs) have also been proposed [10–14]. However, those structures are limited by their sensitivity to fabrication errors. Currently, an efficient mode multiplexer built on the SOI platform with low insertion loss, low crosstalk, and large fabrication tolerance is still unreported.
A tapered DC has been shown to be an efficient design in order to relax the fabrication tolerance of conventional asymmetrical normal DCs used as polarization splitters and rotators . In this paper we demonstrate an on-chip two-mode division multiplexing circuit using a tapered DC-based TE0&TE1 multiplexer and demultiplexer. The device can furthermore be fabricated by a simple process on the SOI platform. A minimum insertion loss of 0.3 dB and mode crosstalk lower than −16 dB over a wide bandwidth of 100 nm are demonstrated together with a large tolerance of more than 20 nm for the width deviation of the narrow silicon waveguide (compared to only a few nanometers for a normal DC) and with relaxed coupling length sensitivity. The chip is further employed in a system experiment where two non return-to-zero (NRZ) on-off keying (OOK) channels, each modulated at 40 Gbit/s, are mode-multiplexed and demultiplexed. The experimental results show clear eye-diagrams, and only 1.6 dB and 1.8 dB power penalty for the two demultiplexed channels. To the best of our knowledge, this is the first system demonstration of on-chip mode multiplexing on an SOI waveguide for interconnect applications.
2. Principle and design of the TE0&TE1 mode multiplexer
The TE0&TE1 mode multiplexer is based on a tapered DC, which parallel-couples a narrow silicon waveguide (waveguide width w1) to a wide tapered waveguide (from w2a to w2b with center width of w2) with a coupling length and gap of L and g, respectively, as shown in Fig. 1. The structure is degenerated to a conventional asymmetrical normal DC when w2a = w2b = w2. For conventional DC-based TE0&TE1 mode multiplexers, the TE0-TE1 coupling relies on the phase matching between the waveguides, i.e. the effective refractive index of the TE0 mode of the narrow waveguide should be equal to that of the TE1 mode of the wide waveguide. In this case, if TE0 light is injected into the narrow waveguide, a high coupling efficiency rTE0-TE1 will be obtained at the output of the wide waveguide. On the other hand, because of the significant effective refractive index difference between the TE0 modes in the two asymmetrical waveguides, a very low coupling efficiency rTE0-TE0 (mode crosstalk) is obtained. However, in conventional asymmetrical DCs, the phase matching can be easily destroyed by fabrication errors of the narrow waveguide. A fabrication error-induced width deviation ∆w will result in a larger effective refractive index deviation ∆neff for the narrow waveguide than for the wide waveguide since the slope of the effective index of the TE0 modeversus waveguide width is larger than that of the TE1 mode, as shown in Fig. 2(a). The larger the slope difference, the easier it is for the phase matching condition to be destroyed due to waveguide width errors. Moreover, the length of the DC should be properly designed to avoid the converted TE1 light coupling back to the narrow waveguide. In order to relax these limitations, the wide waveguide is tapered from w2a to w2b in our proposed design. For the two widths w2a and w2b of the wide waveguide, the corresponding widths of the narrow waveguide enabling to satisfy the phase matching condition are w1a and w1b, respectively, as indicated in Fig. 2(a). Consequently, tapering the wide waveguide from w2a to w2b will result in a deviation tolerance between w1a and w1b for the narrow waveguide because a phase matching position can always be found along the taper. After the phase matching position, the conversion efficiency will be maintained and the fabrication error sensitivity of the coupling length will be relaxed. It should be noted that w2a should not be too close to the width where the TE1 and TM0 modes are hybridized (700 nm in our case). A large tapering strength (width difference between w2a and w2b) provides a larger fabrication tolerance (from w1a to w1b) for the narrow waveguide. However, a larger tapering strength requires a longer tapering length L in order to achieve a sufficiently long effective coupling length around the phase matching position. Widths w1 = 390 nm and w2 = 800 nm were chosen as a starting point since these widths satisfy the phase matching condition, as shown in Fig. 2(a). Tapering from w2a = 750 nm to w2b = 850 nm with center width w2 is selected for the wide waveguide. Figure 2(b) shows the TE0-TE1 coupling efficiency rTE0-TE1 and mode crosstalk rTE0-TE0 simulated as a function of wavelength using the eigenmode expansion (EME) method  with L = 50 μm and g = 100 nm. The residual TE0-TM0 coupling rTE0-TM0 is also shown. One can find that a high rTE0-TE1 with rTE0-TE0 lower than −22 dB are obtained over a large wavelength range of 200 nm. In addition, a very small rTE0-TM0 lower than −30 dB is also obtained thanks to the large refractive index difference between these two modes.
As mentioned previously, since the coupling efficiency rTE0-TE1 is much more sensitive to the width of the narrow waveguide than to that of the wide waveguide, only the sensitivity to the width deviation of the narrow waveguide is investigated. The width of the narrow waveguide is changed between w1 ± ∆w to investigate the fabrication tolerance, where ∆w is the width deviation due to fabrication error. A coupling gap g = 100 nm is selected. Figures 3(a) and 3(b) show the calculated coupling efficiency rTE0-TE1 and mode crosstalk rTE0-TE0 as a function of the width deviation ∆w and coupling gap g, respectively, for both tapered and normal DCs. One can find that rTE0-TE0 shows good tolerance to the width deviation ∆w for both tapered and normal DCs since the phase mismatch of TE0-TE0 coupling is large in both cases. In case of a tapered DC, a high rTE0-TE1 with rTE0-TE0 lower than −25 dB is obtained within a width deviation range of about 40 nm for L varying from 30 μm to 50 μm. Since a high rTE0-TE1 is maintained as L further increases, the width deviation tolerance is also expected for L longer than 50 μm. In addition, the tapered DC-based scheme also exhibits a good tolerance to the coupling gap, and a better gap tolerance is obtained for longer L. However, in the case of a normal DC, the width deviation tolerance is only a few nanometers, and the gap tolerance is even worse than for a tapered DC. Moreover, rTE0-TE1, the width deviation tolerance, and the gap tolerance are much more sensitive to L than in the case of tapered DC.
3. Device fabrication and characterization
Based on the proposed TE0&TE1 mode multiplexer design, a two-mode division multiplexing circuit was fabricated on a SOI wafer with 250 nm top silicon layer and 3 μm buried silicon dioxide by a single step of E-beam lithography (JEOL JBX-9500FS) and inductively coupled plasma reactive ion etching (STS Advanced Silicon Etcher). Polymer (SU8-2005) waveguides of dimensions 3.5 μm × 3.5 μm covering silicon inverse tapers were fabricated afterwards in order to reduce the coupling loss to tapered fibers. Figure 4(a) shows the fabricated device, which consists of a multiplexer (detailed in Fig. 4(b)) at the input side, a multimode data bus (750 nm wide), and a demultiplexer (identical to the multiplexer) at the output side. The width of the narrow waveguide is 355 nm, the wide waveguide is tapered from 748 nm to 848 nm, and the coupling gap is 100 nm, as shown in Figs. 4(c) and 4(d). Figure 5(a) shows the measured transmissions (normalized to a straight waveguide) from inputs CH1 and CH2 to the demultiplexed outputs CH1 and CH2, respectively, on the TE0 mode, and the corresponding mode crosstalk (from inputs CH1 and CH2 to the demultiplexed outputs CH2 and CH1 on the TE0 mode, respectively) for different widths w1 of the narrow waveguide and taper lengths L. High transmission from CH1 and CH2 to the corresponding demultiplexed CH1 and CH2 with lowest insertion loss of 0.3 dB and crosstalk lower than –16 dB are obtained over a large bandwidth of 100 nm for narrow waveguide widths of 360 nm and 380 nm, and taper length of 30 μm and 50 μm.
4. System demonstration
The fabricated chip was further employed for two-mode division multiplexing application with NRZ-OOK signals at 40 Gbit/s. Figure 6 shows the experimental setup. Continuous wave (CW) light at 1553.06 nm is modulated at 40 Gbit/s in the NRZ-OOK format in a Mach-Zehnder modulator with a pseudo-random binary pattern length of 231−1, and then amplified by an erbium-doped fiber amplifier (EDFA). The amplified signal is split into two tributaries by a 3 dB coupler afterward. Before being injected into the silicon chip, the two tributaries are decorrelated using a length of 1 km standard single mode fiber. Polarization controllers (PCs) are used in order to set the state of polarization of each tributary so that it excites the TE mode of the silicon chip. The two channels, labeled CH1 and CH2, are then simultaneously injected into the chip using a lensed fiber array for on-chip two-mode division multiplexing. The demultiplexed output signals from the chip are finally detected in a preamplified receiver.
Figure 7(a) shows the spectra of the signals recorded at the CH1 and CH2 demultiplexing ports when only either the CH1 or CH2 signal are injected into the waveguide, respectively. They correspond to either TE1 mode or TE0 mode propagation in the silicon multimode data bus, respectively. Crosstalk spectra (measured at CH2 output with CH1 excitation and at CH1 output with CH2 excitation) are also represented. Since the signal wavelength is tuned to the dip wavelength of the crosstalk spectrum (detailed in Fig. 5), a low crosstalk level below −20 dB is obtained for both channels. The corresponding demultiplexed signals exhibit clear eye diagrams, as shown in Figs. 7(c) and 7(d) when only the TE1 or the TE0 mode is propagating in the waveguide. When both TE1 and TE0 modes are multiplexed, clear eye diagrams are also obtained for the two demultiplexed signals thanks to the low mode crosstalk, as shown in Figs. 7(e) and 7(f). Figure 8 shows the results of bit-error-ratio (BER) measurements performed for the signals from the CH1 and CH2 demultiplexing ports with and without crosstalk. Low power penalties of 1.6 dB and 1.8 dB are obtained for CH1 and CH2 demultiplexing with crosstalk, respectively.
In conclusion, we have demonstrated an on-chip two-mode multiplexing circuit using a novel TE0&TE1 mode multiplexer built on the SOI platform. The circuit exhibits a lowest insertion loss of 0.3 dB, with mode crosstalk smaller than −16 dB over a wide bandwidth of 100 nm. A large fabrication tolerance of 20 nm and relaxed coupling length sensitivity are experimentally demonstrated. System experiments have been carried out for on-chip two-mode multiplexing application at 40 Gbit/s, showing clear eye diagrams for both demultiplexed channels and 1.6 dB and 1.8 dB power penalties with crosstalk for the two channels, respectively.
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1. FIMMWAVE/FIMMPROP, Photon Design Ltd, http://www.photond.com.