n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach–Zehnder interferometer optical switch having thermo–optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.
©2013 Optical Society of America
Monolithic integration of p-i-n phase shifters and CMOS [1–3] has been one of the main streams of the silicon photonics research. For transceiver applications , p-i-n phase shifters and CMOS are normally featured by high-speed operation. For applications where the high-speed response is not a high priority, the thermo-optic (TO) phase shifter remains a good option. For example, it is used in fine phase tuning even for p-i-n phase shifters . The TO phase shifter is also preferred for circuit switch applications [4,5] due to its low excessive loss. The TO phase shifter  requires a driving current of typically ten times that for the p-i-n phase shifter [6,7], and the CMOS optimized for the p-i-n phase shifter cannot drive the TO phase shifter. We are thus interested in how the large current MOSFETs (metal-oxide-semiconductor field-effect transistors) can be integrated on a silicon-on-insulator (SOI) wafer with a top silicon layer of 200 ~300 nm and a buried oxide (BOX) layer of 2 ~3 μm, which we call photonic SOI in this paper, as the electrical drivers for TO-based components.
In this paper, we report the monolithic integration of body-tied MOSFETs and a TO 2 × 2 Mach–Zehnder interferometer (MZI) switch. We present experimental results of the electronic control of the TO MZI switch using this MOSFET. Also, we discuss on remaining challenges in the practical fabrication steps. We believe that this work could expand the capability of the photonic SOI platform to large current applications.
2. Device description and measurement
The MOSFET was designed to the n-channel body-tied partially depleted (PD) type and to satisfy the current requirement for the TO phase shifter. The MOSFET for driving the p-i-n phase shifter usually takes the body-floating structure which is preferred for the high-speed operation, but it is not stable in large-current conditions. Even though it is possible to build a large-current driver by connecting many small-current MOSFETs in parallel, a large number of the gates make the driver complex and susceptible to fluctuations. For driving the low-speed TO phase shifter, a single-stage MOSEFT is simple and stable. This MOSFET would simplify the off-chip large-current driving accessories for multi-port circuit switches [8,9].
Figure 1(a) shows the integrated device consisting of a balanced MZI and two MOSFETs, fabricated on a two-inch SOI wafer with a 250-nm-thick top silicon layer and a 3-μm-thick BOX layer. First, the MOSFET was fabricated by the standard CMOS process, including the isolation trench formation, ion implantation, dry oxidation of the gate insulator (~7 nm), n + -poly-Si deposition and patterning, and rapid thermal annealing. The left-hand side of the MOSFET is enlarged in Fig. 1(b). The gate was designed to be 2-μm long and 200-μm wide, and the body was tied to the source to eliminate hysteresis in its dynamic response. Subsequently, the silicon wire waveguide (~500-nm wide) was patterned by electron beam lithography and formed by conventional reactive ion etching using an ~100 nm oxide hard mask. The MZI contains two input and two output ports (2 × 2 scheme) with two directional couplers and two arms. After the ~1-μm-thick oxide was covered as the top cladding layer, we deposited and patterned the ~80-nm-thick TiN to form the resistors with a width of ~5 μm and a length of ~50 μm as waveguide heaters. Finally, the contact holes of the TiN resistor and the MOSFETs were opened, AlSi electrodes were fabricated, and the device was treated with post-metallization annealing at 450°C for 30 min in H2/N2 gas. Figure 1(c) shows the connection between the MOSFET and the TiN resistor.
The device principle is shown by the electrical circuit diagram in Fig. 1(d). The MOSFET and the TiN resistor are connected in series. If the working voltage is applied to Vdd and the source is connected to the ground (GND), the gate voltage can be tuned to control the current flow in the TiN resistor, and thus, to adjust the thermal power generated by the resistor. When the thermal power generated on one MZI arm is sufficient to induce an optical phase shift of π, the light will be switched from the cross to the bar ports. Therefore, the MOSFET behaves as an electrical gate to control the MZI states.
Figure 1(e) shows the measurement system used for device characterization. The current–voltage (I–V) characteristics was evaluated using a sourcemeter (Keithley 2400) and a direct current source, which were connected to Vdd (or the drain) and the gate, respectively. The drain electrode allowed us to independently measure either the MOSFET or the TiN resistor, whereas for the switching control of the MZI via the MOSFET, we used the Vdd, source, and gate electrodes. The static optical transmissions of the MZI were measured simultaneously with the I–V measurement. For the dynamic switching, the gate was subjected to a square-wave pulsed voltage generated from an arbitrary waveform generator with 5 ns rising and falling edges, and the temporal optical responses were detected using a 150 MHz InGaAs photodiode connected to a digital phosphor oscilloscope. The tunable semiconductor laser source was a transverse electric continuous wave at the wavelength λ = 1572 nm. The light was coupled into the waveguide facet through a focusing lens and the transmitted light from the other facet was coupled into a lensed fiber. The facets were cleaved by cut-back method and the device is ~2.1-mm long. All voltages used the source (set to GND) as the reference, and all measurements were performed at room temperature.
3. Fundamental characterization of MOSFET, TiN heater, and MZI
The I–V curves in Fig. 2(a) show the representative feature of the n-channel MOSFET, i.e., the drain–source saturation current increases with the increase in the gate voltage (Vg). The MOSFET is capable of switching a current as large as 20 mA at a drain voltage (Vd) less than 3 V and a Vg of 3.5 V. For Vg less than 2V, the excessive current increase can be clearly seen after Vd increases beyond the saturation region, which is well known as the kink effect in PD MOSFETs due to the electron–hole ionization in the channel . The leakage current from the gate to the source was less than 4 pA even when the gate voltage was increased to 2 V (not shown), indicating the good quality of the gate insulator layer. The threshold voltage (Vt) is estimated to be ~0.6 V at the linear region on the basis of the constant current criteria (Vt = Vg at Id = Wg × 10−7/Lg = 10−5 in the linear region of the transistors, where Wg is the gate width and Lg is the gate length). The I–V curve of the TiN resistor [bottom of Fig. 2(b)] was used to analyze the heater resistance [top of Fig. 2(b)], which exhibited a nonlinear dependence on the voltage. This resistance–voltage relationship can be approximated as R = 130 × (1 + 0.06V2). The increase in resistance with increasing the voltage may originate from the aluminum migration into TiN at the contact holes which could change the contact resistance  and temperature enhancement effects . This resistance nonlinearity was considered in estimating the actual power consumption in the TiN resistor.
The switching characteristics of the MZI are shown in Fig. 2(c) where another device without MOSFET fabrication process but with the same process of MZI is compared in order to clarify the influence of MOSFET process on the insertion loss and MZI properties. At zero power, the insertion losses of the MZIs with and without MOSFETs both are about 14 dB considering a −3 dBm system background. This indicates that the introduction of MOSFETs does not worsen the insertion loss, which is beneficial to the integration of large numbers of MOSFETs. The insertion loss is actually dominated by the lens-device-fiber coupling loss. The on-chip waveguide loss is estimated to be less than 1 dB based on the propagation loss of ~2 dB/cm for our waveguide. The alternative occurrence of the transmission extrema in Fig. 2(c) between the bar and cross ports is a typical switching property of the MZI, and the two adjacent extrema correspond to the optical phase shift of π between the two arms. For the MZI with MOSFETs, the ~35-mW power induced a switching extinction ratio of ~25 dB at the cross port, whereas for that without MOSFETs, a ~18-mW power induced ~40-dB extinction ratio. The crosstalk at on and off states for both the cross and bar ports is ~15 dB lower for the MZI without MOSFETs than that with MOSFETs. The extinction ratio and crosstalk could be improved by optimizing the directional couplers on the wafer with MOSFET process. Several steps of high temperature treatment in MOSFET process may induce the changes in optical properties of the SOI layer, which may explain the difference in the switching power in Fig. 2(d) where the values are ~30 and ~18 mW/π for the MZIs with and without MOSFETs, respectively. The transmission extreme of the bar port does not occur exactly at zero power for the MZI with MOSFET, as shown in Fig. 2(c), because of the arm-length fabrication error, which explains the nonzero y-intercept of the fitting line in Fig. 2(d).
4. Static and dynamic switching control via MOSFET
Static switching indicates the variations in the optical output of the MZI in response to the gate voltage, Vg, and Vdd. Figures 3(a) and 3(b) show the transmission contour mapping versus Vg and Vdd, respectively, for cross and bar ports. Simultaneously, we monitored the drain–source current Ids that flows from Vdd to the source [Fig. 3(c)]. When Vg ≤ Vt (~0.6 V), the change in Vdd did not induce obvious transmission variations in both cross and bar ports because the MOSFET remained off. In this condition, the current flow in the TiN resistor was negligible so that almost no thermal power was generated. When Vg was larger than Vt and smaller than ~2.8 V, tuning Vdd from 0 to 5 V was still insufficient to completely switch on the MZI because the optical output at the cross port had not yet reached the minimum value in spite of its weakening. It means that the thermal power generated in this case was not sufficient to introduce a π-phase difference between the optical paths of the two MZI arms. For Vg = 3 V, a minimum optical output at the cross port was observed at Vdd ~4.5 V, which indicated the completion of the switching from off to on state. Meanwhile, a maximum optical output occurred at the bar port, as shown in Fig. 3(b). The corresponding current was around 13.5 mA and the partial voltage at the MOSFET was ~1.95 V. If we consider a switching extinction ratio of 20 dB for the cross port, the confidence region of the switching-on Vdd was ~4.2−4.6 V. For Vg larger than 3 V, the switching-on voltage point (Vdd, Vg) in Figs. 3(a) and 3(b) both tended to shift to the direction of a smaller Vdd, which can be understood from the current contour shown in Fig. 3(c). In other words, a smaller Vdd would be enough to achieve the same current for a larger Vg. In the switching-on state, power consumption occurred in two parts, namely, the TiN resistor and the MOSFET, which consumed ~35 and ~26 mW, respectively. The total operational power could be further decreased by introducing the heat insulating grooves  and by optimizing the effective resistance of MOSFETs, which is beneficial to the heat management for the device. Figures 3(a) and 3(b) show the clear complementary features of the transmission, denoting the static switching operation of the MZI via the MOSFET.
On the basis of the results of the static switching, we performed a dynamic switching operation of the device by applying a 10 kHz square-wave pulsed voltage signal with a 3 V peak-to-peak voltage [bottom of Fig. 4(a) ] to the gate of the MOSFET, while we set Vdd to a constant working voltage of 4.2 V. The temporal responses of both the bar and cross ports of the MZI are shown at the top of Fig. 4(a), where the peak-to-peak value of the cross port corresponds to the switching extinction ratio of 20 dB. The 10−90% rising and falling times were ~8 and ~10 μs, respectively, as shown in Fig. 4(b) and 4(c), from which the operational speed limit of this device is estimated to be about 25 kHz. These responses were faster than the previously reported values for the TO MZI switches , which can be attributed to the thinner upper cladding oxide (~1 μm) we adopted. The bar and cross port responses were in phase and out of phase, respectively, with respect to the gate voltage, because the light is at the cross port when the gate voltage is zero (MOSFET off), whereas it is at the bar port during the peak gate voltage (MOSFET on). The MOSFET-on-state causes a current flow in the TiN resistor, and thus, the generated thermal power induces an optical phase difference of π between the two MZI arms. The pulsed gate voltage periodically alternated the MOSFET between the on and off states; consequently, the light output of the MZI was periodically switched from one port to the other. The phase relation between the temporal waveforms of the MZI outputs and the gate voltage verifies the role of the MOSFET in controlling the switching state of the MZI switch as expected.
n-channel body-tied PD MOSFETs and MZI switches were fully monolithically integrated on a two-inch 250-nm-thick SOI wafer based on silicon wire waveguides. The MOSFET can drive a current as large as ~20 mA and a power larger than 30 mW for a >20 dB switching operation of the TO MZI switch with an ~4.2−4.6 V working voltage for the power supply and a ~3 V gate voltage, in both static and dynamic switching operations. This monolithically integrated device could be used to construct large-scale optical matrix switches with large-current analog drivers on the chip.
The authors would like to thank Mr. J. Tsukada and Mr. K. Saitou for their technical assistance in the CMOS fabrication process. This study was supported in part by Project for Developing Innovation Systems of MEXT, Japan. The wafer dicing was conducted at the Nano-Processing Facility, supported by IBEC Innovation platform, AIST.
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