An integrated tunable CMOS laser for silicon photonics, operating at the C-band, and fabricated in a commercial CMOS foundry is presented. The III-V gain medium section is embedded in the silicon chip, and is hermetically sealed. The gain section is metal bonded to the silicon substrate creating low thermal resistance into the substrate and avoiding lattice mismatch problems. Optical characterization shows high performance in terms of side mode suppression ratio, relative intensity noise, and linewidth that is narrow enough for coherent communications.
© 2013 Optical Society of America
Silicon Photonics is a promising technology platform for high speed, high capacity, and low cost optical communication systems [1–3]. Its appeal is in leveraging the readily available CMOS manufacturing technology for integrated electrical circuits, to manufacture integrated photonic circuits. Significant progress has been made in the development of silicon photonic macro-cells including modulators and detectors for integrated optical communication systems. However, a key component vital for the realization of the true potential of silicon photonics is still missing: a tunable CMOS-compatible integrated laser.
Although the high index contrast of silicon to silicon-dioxide makes silicon-on-insulator (SOI) an excellent platform for guiding and manipulating light, silicon suffers from a major drawback, namely, its indirect bandgap does not allow for generation of coherent light. Therefore, one common approach is to have the laser sources external to the silicon photonics chip . A more integrated approach is to flip-chip bond a semiconductor optical amplifier (SOA), particularly to form an external cavity tunable laser [4–6]. Although these lasers can have high performance, this method of integration suffers from low throughput and high cost. Recently integration of III-V materials and silicon for the creation of coherent light sources has been explored [7–9]. However, the challenge remains to develop a CMOS compatible low-cost laser integration method, which is suitable for commercial high-volume manufacturing.
In this paper, we present an integrated tunable CMOS laser, fabricated in a commercial foundry, and operating in the C-band. Unprocessed III-V epitaxial material is metal-bonded directly onto the silicon substrate, such that it is eventually embedded in the SOI chip. In contrast to previously explored configurations, the III-V gain section is planar with the silicon device layer, providing high efficiency direct optical coupling between the two regions. Other advantages of this approach include good thermal conductivity through the silicon substrate, and avoiding strains associated with lattice mismatch. Furthermore, having the III-V epitaxial material hermetically sealed under silicon dioxide removes the constraint of high cost hermetic packages, thereby presenting new opportunities in commercialization of Silicon Photonics. We discuss below the device configuration, its fabrication, and characterization.
2. Device configuration
The integrated CMOS tunable laser device configuration is shown in Fig. 1(a), and a cross-section view is given in Fig. 1(b). Unprocessed off-the-shelf epitaxial III-V (AlGaInAs multiple quantum wells) gain material pieces are metal-bonded within etched pit receptor sites inside the SOI wafer, onto the silicon substrate, and then processed according to the flow described in Section 3. The metal bond serves three purposes: the first is to facilitate the bottom electrical contact for the laser. The second purpose is to provide a low thermal resistance path to the silicon substrate, bearing in mind that silicon is a high thermal conductivity material. The third purpose is to avoid lattice mismatch issues formed by bonding the III-V material directly onto the silicon, as well as alleviating mismatch due to the difference in the thermal coefficient of expansion between silicon and III-V.
After the bonding of the III-V epitaxial material, a gap remains between the gain section and the crystalline silicon waveguide. To achieve high efficiency coupling, an integrated waveguide coupler, as seen in Fig. 1(b), is formed by reconstructing the buried oxide (BOX) layer in the gap and building an amorphous silicon waveguide with identical cross section to that of the crystalline silicon waveguide. The modal overlap between the III-V waveguide and the silicon waveguide is over 85%. Undesirable reflections between the gain waveguide and the silicon waveguide are suppressed by angling the waveguides with respect to the interface, as seen in Fig. 1(a).
Tuning is achieved using the Vernier effect, with two binary superimposed gratings connected via a multimode interference device (MMI) . Integrated heaters tune the refractive index of each grating using the thermo-optic effect, thereby controlling the frequency of overlap between the two reflection combs of each grating. An additional heater on the main cavity provides phase shifting of the longitudinal modes for better overlap with the grating peaks.
3. Fabrication process
The fabrication process of the tunable CMOS laser devices is performed in a commercial CMOS foundry, and it consists of three major parts: front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL).
At the FEOL, the passive and active silicon photonic devices are defined, and the pit receptor sites for the epitaxial material are etched. The process starts with conventional SOI wafers with a 1.5 µm thick silicon device layer and a BOX layer of 2 µm. First, the waveguide and grating structures are patterned, followed by a dry etch pattern transfer into the silicon device layer. Subsequently, resistive heaters and resistive thermal devices (RTD), that are part of the tuning and control mechanisms, are patterned. Finally, the pit receptor site for the unprocessed epitaxial material is etched.
The MOL portion of the fabrication includes bonding of the gain section into the SOI wafer, definition of the coupling region, and definition of the waveguides. It begins by metal-bonding unprocessed epitaxial gain material into the pit receptor sites in the SOI wafer. Next, integrated waveguide couplers are built to connect the epitaxial material to the crystalline silicon waveguides. The InP substrate is removed subsequent to bonding. After bonding and formation of the waveguide couplers, the waveguides are defined throughout the coupling regions and the III-V material, such that they are inherently aligned to the original SOI waveguides. This involves multiple steps of deposition, planarization, and etching. Figure 2 shows a scanning electron microscope (SEM) micrograph of the III-V epitaxial material and the amorphous silicon waveguide coupler region. Finally, silicon dioxide is deposited over the entire wafer, hermetically sealing the lasers. It is important to note that all processes, and particularly the temperatures used in the MOL, are designed such that they do not affect any of the structures defined in the FEOL, and do not hinder the ability to finish the metal contacts in the BEOL.
The BEOL process defines the device wiring, and particularly, metal vias and metal traces to contact the tuning structure, tuning feedback, and gain section. A photograph of the completed CMOS chip is shown at the inset of Fig. 2.
4. Device characterization
CMOS laser chip measurements were performed with the SOI chips mounted on a thermoelectric cooler (TEC), allowing for measurements over temperature. Figure 3 shows continuous wave (CW) optical output power versus current (L-I) curves for several temperatures as measured by an integrating sphere detector from the SOI chip facet. It should be noted that no control loops were implemented on the tuning heater or the laser pump current while performing these measurements. In addition, the main cavity heater was not used, resulting in some misalignment between the cavity longitudinal modes and the grating peaks, and consequently suboptimal performance. As the cavity is not actively controlled, mode hopping is observed along the L-I curves. A threshold current of about 41 mA is seen for a temperature of 20°C. The good thermal characteristics of this configuration allow laser action at a temperature of 80°C, with an optical output power of about 6.8 dBm, at an injection current of 250 mA. Further optimization of the cavity will reduce the threshold current and improve the output power and performance over temperature.
Laser chips were tuned using both of the grating heaters, producing the spectra shown superimposed in Fig. 4. The upper right frame shows tuning at a 50 GHz frequency spacing over the frequency range marked by a dashed line. All peaks exhibit a side mode suppression ratio (SMSR) larger than 40 dB. Relative intensity noise (RIN) was measured at an injection current of 125 mA, and found to be better than −130 dB/Hz, and as good as −138 dB/Hz. Linewidth measurement was performed using the heterodyne method , where the CMOS laser was beat against a narrow linewidth HP 8168F commercial tunable laser. The RF beating signal was sampled with a fast oscilloscope, and Discrete Fourier Transform (DFT) was performed for a record length of 25 µs. The RF spectrum of the beating signal is shown in Fig. 5, where it can be seen that the combined Lorentzian linewidth of the CMOS laser and the commercial laser is narrower than 200 KHz. As such, the integrated tunable CMOS laser is suitable for coherent optical communications.
As discussed above, the thermal characteristics of the demonstrated integrated CMOS laser are one of its important advantages. To quantify this, a thermal resistance measurement was performed. For this purpose a Fabry-Perot cavity was created from a CMOS laser chip by dicing one of the sides of the gain section, and focused ion beam (FIB) milling the other. The gain section length for this experiment was about 1 mm. To calculate the thermal resistance we perform two measurements . The first measurement is the lasing wavelength at CW pumping as a function of the dissipated electrical pump power, yielding dλ/dP = 1.97 nm/W as seen in Fig. 6(a). The second measurement is a pulsed measurement, where the lasing wavelength is measured as a function of the stage temperature set by the TEC, as shown in Fig. 6(b). For this measurement, a low duty cycle was used to eliminate laser self-heating effects. From the second measurement we obtain dλ/dT = 0.094 nm/°C. The thermal resistance is then given by dT/dP = (dλ/dP)(dλ/dT)−1 = 21°C/W. Consequently, if a pump power of 300 mW is assumed, the laser temperature difference above the ambient temperature would be ΔT = 6.3°C, which allows for uncooled operation, assuming an ambient of up to 100°C.
An integrated tunable laser for silicon photonics operating over the C-band, and fabricated in a commercial CMOS foundry, is presented. The gain region is metal-bonded onto the silicon substrate and embedded within the silicon chip, such that heat is easily extracted into the substrate resulting in good thermal characteristics, and lattice mismatch strain is avoided. Moreover, the laser structure is encapsulated by silicon dioxide, which hermetically seals the laser and eliminates the need for costly hermetic packaging. Optical characterization demonstrates high performance of SMSR, RIN, and linewidth, where the latter, which is better than 200 KHz, allows for usage in coherent communication. Laser performance is expected to improve under full closed loop control. The integrated tunable CMOS laser is a critical component to enable low cost, high speed, Silicon Photonics.
References and links
1. G. T. Reed, Silicon Photonics: The State of the Art (Wiley, 2008).
2. L. Vivien and L. Pavesi, Handbook of Silicon Photonics (CRC Press, 2013).
3. Y. A. Vlasov, “Silicon CMOS-integrated nano-photonics for computer and data communications beyond 100G,” IEEE Commun. Mag. 50(2), s67–s72 (2012). [CrossRef]
4. T. Chu, N. Fujioka, and M. Ishizaka, “Compact, lower-power-consumption wavelength tunable laser fabricated with silicon photonic-wire waveguide micro-ring resonators,” Opt. Express 17(16), 14063–14068 (2009). [CrossRef] [PubMed]
5. K. Nemoto, T. Kita, and H. Yamada, “Narrow-Spectral-Linewidth Wavelength-Tunable Laser Diode with Si Wire Waveguide Ring Resonators,” Appl. Phys. Express 5(8), 082701 (2012). [CrossRef]
6. S. Tanaka, S. H. Jeong, S. Sekiguchi, T. Kurahashi, Y. Tanaka, and K. Morito, “High-output-power, single-wavelength silicon hybrid laser using precise flip-chip bonding technology,” Opt. Express 20(27), 28057–28069 (2012). [CrossRef] [PubMed]
7. A. W. Fang, H. Park, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, “Electrically pumped hybrid AlGaInAs-silicon evanescent laser,” Opt. Express 14(20), 9203–9210 (2006). [CrossRef] [PubMed]
8. X. Sun, A. Zadok, M. J. Shearn, K. A. Diest, A. Ghaffari, H. A. Atwater, A. Scherer, and A. Yariv, “Electrically pumped hybrid evanescent Si/InGaAsP lasers,” Opt. Lett. 34(9), 1345–1347 (2009). [CrossRef] [PubMed]
9. A. Le Liepvre, C. Jany, A. Accard, M. Lamponi, F. Poingt, D. Make, F. Lelarge, J.-M. Fedeli, S. Messaoudene, D. Bordel, and G.-H. Duan, “Widely wavelength tunable hybrid III–V/silicon laser with 45 nm tuning range fabricated using a wafer bonding technique,” in 2012IEEE 9th International Conference on Group IV Photonics (GFP), pp. 54–56.
10. I. A. Avrutsky, D. S. Ellis, A. Tager, H. Anis, and J. M. Xu, “Design of widely tunable semiconductor lasers and the concept of binary superimposed gratings (BSG's),” IEEE J. Quantum Electron. 34(4), 729–741 (1998). [CrossRef]
11. D. M. Baney and W. V. Sorin, “High resolution optical frequency analysis” in Fiber Optic Test and Measurement, D. Derickson, ed. (Prentice Hall, 1998).
12. M. N. Sysak, H. Park, A. W. Fang, J. E. Bowers, R. Jones, O. Cohen, O. Raday, and M. J. Paniccia, “Experimental and theoretical thermal analysis of a hybrid silicon evanescent laser,” Opt. Express 15(23), 15041–15046 (2007). [CrossRef] [PubMed]