We report on the photoresponse of an asymmetrically doped p−-Ge/n+-Si heterojunction photodiode fabricated by wafer bonding. Responsivities in excess of 1 A/W at 1.55 μm are measured with a 5.4 μm thick Ge layer under surface-normal illumination. Capacitance−voltage measurements show that the interfacial band structure is dependent on both temperature and light level, moving from depletion of holes at −50 °C to accumulation at 20 °C. Interface traps filled by photo-generated and thermally-generated carriers are shown to play a crucial role. Their filling alters the potential barrier height at the interface leading to increased flow of dark current and the above unity responsivity.
© 2013 OSA
Silicon is the base material for electronic technologies and has emerged as a very attractive platform for photonic integrated circuits. Germanium, due to its low bandgap, maturity and compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infra-red wavelengths. For the integration of Ge with Si a high-quality defect-free, 100% Ge layer is desirable for realizing high-performance photodiodes. A low defect density in the Ge layer will lower the dark current by minimizing the leakage mechanisms and noise sources. Integration through epitaxial growth of Ge on Si is challenging due to a lattice mismatch of about 4.2% between Ge and Si resulting in the formation of a high density of misfit dislocations which increases the leakage current. In order to accommodate this lattice mismatch, different techniques such as deposition of graded SiGe buffer layers  and/or high temperature cyclic annealing [2,3] have been proposed. Highly effective integration of detectors with silicon waveguides has been achieved through rapid melting growth. However, this requires a high temperature process step (Ge melting point ~940 °C) and is limited to thin Ge layers . A side effect of the high temperature process is Si and Ge interdiffusion  resulting in a reduced responsivity at long wavelengths. For the integration of Ge with pre-fabricated Si circuits, the fabrication processes and temperatures have to be compatible with Complementary Metal Oxide Semiconductor (CMOS) process constraints and in particular a limited thermal budget and maximum temperature of 450 °C.
Direct wafer bonding has been used for the integration of Ge with Si waveguide structures . However, for normal incident structures where the current transport through the bonded interface is crucial, an important challenge is minimizing the thickness of the interfacial layer which forms at the metallurgical junction but also assists in the bonding. Bonding of surfaces activated by a plasma results in a thinner interfacial layer than when bonded by wet chemical treatments . The interfacial layer affects the electric field distribution across the junction and hence the carrier transport across the interface. The Ge/Si interface has been studied recently by bonding a p-Ge layer on an n+-Si substrate using direct wafer bonding and layer exfoliation  and also by bonding an n+-Si nanomembrane to a p+-Ge substrate .
In this letter, we report on a remarkable responsivity from a p−-Ge/n+-Si heterojunction photodiode especially at low incident powers. The p−-Ge/n+-Si photodiode arrangement was selected to enable collection of electrons into the Si due to the more favorable band-offset. Detailed analysis regarding the carrier transport across the junction and the band diagram of the interface is presented. The high responsivity is shown to be due to an increased dark current gated by the light generated carriers.
2. Device structure and fabrication
An n+-Si wafer (resistivity ≈0.001 Ω·cm, thickness ≈535 μm) and a p–-Ge wafer (resistivity ≈1 Ω·cm, doping level, Na ≈3.5 × 1015 cm−3, thickness ≈510 μm) were chemically cleaned and then bonded at 10−5 mbar . The surface activation step was performed by exposing the surface of the wafers to oxygen free radicals generated by a remote plasma ring at 100 W prior to bringing the wafers into direct contact. This step was followed by two 24-hour ex situ anneal steps at 200 °C and 300 °C in order to enhance the bond strength. Following the bonding, the Ge side of the bonded pair was thinned by mechanical grinding and polishing leaving a 5.4 μm thick Ge layer. The final thickness depends on the thinning process control capabilities and the bond strength. No delamination was observed during the processing of the devices after the grinding and polishing steps.
In order to characterize the electrical and optical properties of the Ge/Si heterojunction we fabricated mesa diodes (see Fig. 1(a)). Ohmic contacts were made to the p−-Ge and n+-Si using Ti/Au (25/250 nm) deposited by electron beam evaporation. Circular mesa structures ranging in diameter from 20 µm to 500 µm were formed by SF6/C4F8 inductively coupled plasma etching through the Ge/Si junction to a total depth of 10.2 µm. No anti-refection coating or sidewall passivation layers were used. After initial measurements, an annealing step was carried out for 30 min at 400 °C in H2/N2 (0.05/0.95) atmosphere. The entire fabrication process is done with the temperature ≤ 400 °C and is compatible with the backend processing of CMOS microelectronics.
3. Results and discussions
A high-resolution transmission electron micrograph (HR-TEM) of the Ge/Si heterojunction is shown in Fig. 1(b). The Ge and Si on both sides of the junction are single crystalline without any cracks or dislocations. An amorphous interfacial region is observed to be approximately 2 nm thick. However, there are additional regions at the interface on the Ge side, which are shown in the magnified images.
Figure 2(a) shows the dark current density (J) of a 500 μm-diameter device as a function of reverse bias (left axis) at two different temperatures. The reverse current is temperature dependent and the activation energy (Ea) obtained by performing current–voltage (I–V) measurements at different temperatures is 0.22 eV at −2 V. Ea decreases slightly at higher reverse bias voltages. Capacitance–voltage (C–V) measurements were performed at 20 °C and −50 °C and at different frequencies (10 kHz to 1 MHz) in order to understand the variation in depletion width which will occur mainly on the lightly doped Ge side of the junction. Figure 2(a) shows how the capacitance depends on the reverse bias voltage at 20 °C and −50 °C (right axis). The C–V characteristics are independent of frequency at −50 °C while at 20 °C the capacitance at V > −1 V increases at lower frequency. The difference in the characteristics is most probably due to the temperature dependence of the emission rates of charge carriers from the interface states. This suggests that interfacial traps are a factor and that these traps are being filled at room temperature. The inset of Fig. 2(a) illustrates the J–V characteristics of the device at two temperatures. This figure clearly shows the rectifying behavior of the p-n heterojunction and that the thin interfacial layer does not block carrier transport. The dark currents of the 500 μm-diameter device at −0.5 V, −1 V, and −2 V are 30 μA, 49 μA, and 94 μA, respectively, which correspond to dark current densities (DCD) of 15 mA/cm2, 25 mA/cm2, and 48 mA/cm2. The values of DCD compare very favorably with those reported to date for Ge/Si heterojunction photodetectors [10–13]. For the measured devices, the dark current density scales with device area and thus the contribution of sidewalls is negligible.
Figure 2(b) shows how 1/C2 depends on voltage at −50 °C and 20 °C at 100 kHz. As 1/C2 = 2(Ψbi –Vbias–2kT/q)/(qεNa), the extrapolation to 0 V defines the built-in potential (Ψbi) of Ge at the interface. k, T, q, ε, and Na are the Boltzmann constant, temperature, electronic charge, permittivity, and impurity concentration, respectively. The slope of the 1/C2 versus voltage curve gives the free-carrier concentration in Ge which is ~2 × 1015 cm−3 and ~6.5 × 1014 cm−3 at 20 °C and −50 °C, respectively. Ψbi is positive at −50 °C which means that the Ge surface at the junction is depleted of holes while the negative value of Ψbi at 20 °C suggests that the Ge surface at the interface is in the accumulation regime. This accumulation of holes at the Ge/Si interface is an indication of the presence of negative charges at the interface which attract holes from the Ge substrate toward the interface. Hence, it can be concluded that the interface traps are acceptor-type traps .
Considering the Ge surface potential (Ψs) at the interface, the amount of charge at the interface (Qs) which is a function of Ψs  is Qs@20°C = + 1.26 × 10−8 C/cm2. This leads to the density of traps below EF to be Ns@20°C = Qs@20°C/q = 7.88 × 1010 cm−2. The depletion width (WD) is also shown in the inset of Fig. 2(b) as a function of reverse bias voltage at the two temperatures. At −50 °C and 0 V, the junction is already depleted and WD is ~0.5 μm which then expands to 3.08 μm at −4 V. At 20 °C, however, the expansion of the depletion region occurs after ~−0.25 V (shaded area in the inset of Fig. 2(b)). This is due to the pile up of holes at the interface which should be swept away by the electric field to reach the flat-band condition before depletion starts.
Based on the above measurements and discussion, the band diagrams for the Ge/Si bonded interface at equilibrium at −50 °C and 20 °C, are shown in Figs. 3(a) and 3(b), respectively. The current transport at −50 °C is partially due to electron generation in the Ge depletion zone and tunneling across the barrier. Trap assisted carrier generation is also likely to be contributing. At 20 °C, the interface traps below EF are active and cause upward band bending of Ge at the interface, thus lowering the potential barrier for carrier transport by thermionic field emission (TFE) from the Ge to the Si conduction band. This temperature-induced potential barrier lowering effect increases the current flow. Based on TFE model  the band offsets between the edge of Ge conduction band and the top of potential barrier is extracted and shown in Figs. 3(a) and (b). Regarding the forward bias regime and as is shown in the inset of Fig. 2(a), there is a slow increase in the current both at −50 °C and 20 °C which is attributed to the large band offset between Si and Ge conduction band edges and to the presence of the interfacial layer.
The photoresponse of the 500 µm-diameter mesa which has a 320 µm-diameter open aperture at a wavelength of 1.55 μm with a bias, Vbias, of −2 V, and at −50 °C and 20 °C is shown in Fig. 4(a) where the responsivity decreases with increasing power. Light from an Agilent tunable laser is delivered to the detector through a standard cleaved single mode fiber and illuminates a spot much less than the open aperture of the detector. The output power from the fiber at each wavelength is measured using a calibrated Newport optical power meter and the detector current is measured using a Keithley source-meter. A remarkably high responsivity is measured and is well in excess of one electron per photon even if all photons were absorbed which is not the case. If the absorption coefficient of Ge at 1.55 μm is assumed to be 460 cm−1 only 13.5% of the incident light is absorbed in the 5.4 μm thick Ge layer. For an incident power of 10 μW at 1.55 μm, the responsivity is 3.5 A/W at −2 V and a temperature of 20°C. It is proposed that the interface traps are filled by the photo-excited electrons. This trapped negative charge causes additional band bending leading to increased thermionic field emission by reducing the potential barrier. Similar light-induced barrier lowering has been previously observed in GaN ultraviolet detectors  and in Cu-diffused Au-CdS diodes . To confirm this current transport mechanism, the built-in potential at the Ge interface is measured using C−V under illumination. The Ge built-in potential increases gradually by increasing the incident optical power until it saturates (see inset of Fig. 3(b)). A considerable increase from 0.06 V (in dark) to 0.51 V (under illumination at a wavelength of 1.62 μm, 10 μW) at 20 °C demonstrates that the interface is unpinned and suggests that the photo-excited electrons are captured by the empty interface traps above EF. As a result, the accumulation of holes at the Ge/Si interface increases which leads to a lower potential barrier and therefore higher current levels flowing at a given reverse bias. The carriers contributing to the current when the device is under illumination are also available under dark condition; however, due to the larger potential barrier when dark, they do not contribute to the current. Although the dark current density of the devices compares very favorably with similar structures fabricated by epitaxy [10–13], the high responsivity of the 500 µm-diameter device is partially a result of the high dark current of the device. For example, at a bias of −2 V, wavelength of 1.55 μm and optical power of 40 μW we measured the responsivity of 1.6 A/W, but with the signal-to-noise ratio (SNR) of ~1.5. For a 30 µm-diameter device a lower responsivity of 0.3 A/W is measured with higher SNR of 53.
The responsivity as a function of wavelength at different temperatures and at two bias voltages is shown in Fig. 4(b). The significant rise of the responsivity at −2 V at 20 °C compared to −1 V is likely to be due to the increase of the electric field at the Ge interface (Ge band bending) which in turn enhances the carrier transport by thermionic field emission (see inset of Fig. 3(b)). To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The responsivity could be further increased by using an anti-reflection coating.
In conclusion, we have demonstrated photodetectors with above-unity responsivity fabricated by low temperature wafer bonding of Ge to Si. Using C−V measurements the band alignment of the Ge and Si is shown to be offset and the Ge bands are shown to shift both with temperature and under illumination due to hole accumulation at the Ge interface resulting in an increase in the transported carriers providing the high response. Owing to the high responsivity and compatibility with CMOS processing, these devices are suitable to be integrated with Si-based read-out circuits for applications such as high-performance near infra-red imaging.
This work is supported by SFI under grant 07/SRC/I1173 (PiFAS). This work was conducted under the framework of the TYFFANI project funded through the Irish Government’s PRTLI Cycle 5, National Development Plan 2007-2013 and co-funded by the European Regional Development Fund. The authors thank Joe O’Brien (discussion) and Michael Schmidt (TEM).
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