An ultra-compact broadband TE-pass polarizer was proposed and demonstrated on the silicon-on-insulator (SOI) platform, using the horizontal nanoplasmonic slot waveguide (HNSW). Detailed design principle was presented, taking advantage of the distinct confinement region of the TE and TM modes in the HNSW. TM mode cut-off could be achieved when waveguide width was below 210nm. Proof-of-concept devices were subsequently fabricated in a CMOS-compatible process. The optimized device had an active region length of 1μm, three orders of magnitude smaller than similar device previously demonstrated on the SOI platform. More than 16dB polarization extinction ratio was achieved across 80nm wavelength range, with a relatively low insertion loss of 2.2dB. The compact device size and excellent broadband performance could provide a simple yet satisfactory solution to the polarization dependent performance drawback of the silicon photonics devices on the SOI platform.
© 2013 OSA
Polarization dependent performance has been identified as detrimental on the silicon-on-insulator (SOI) platform recently, originated from the SOI waveguide’s large structural birefringence and high index contrast . The associated polarization mode dispersion (PMD), polarization dependent loss (PDL) and polarization dependent wavelength shift (PDWS) deteriorate the performance of the devices on the platform [2, 3]. To circumvent the problem, polarization diversity circuit has been proposed. Orthogonal polarizations are split, rotated and processed separately using polarization beam splitters (PBS) and rotators in the scheme [4, 5]. A number of PBS and rotators have been subsequently demonstrated [6–9]. The solution is comprehensive, at the expense of increased system footprint and complexity. When polarization-division multiplex is not necessary, another simple yet satisfactory approach is to design the devices in one single polarization and strip off the unwanted polarization with a polarizer . In addition, integrated polarizer is essential for applications such as polarization filter, optical sensing, advanced optical processing and quantum communications. Various polarizers have been proposed on the SOI platform, utilizing photonic crystal slab , nanophotonics waveguide  and plasmonic waveguide . In particular, a transverse-electric (TE)-pass polarizer has been demonstrated using shallowly etched SOI ridge waveguide . The device is however 1mm-long, making it less attractive due to the precious space on-chip.
A more compact polarizer is needed on the SOI platform. Plasmonic waveguide could provide an answer, with its well-known capability to confine light below the diffraction limit . Two independent groups have shown theoretically that micron-size polarizer is achievable using plasmonic waveguides [10, 13]. To the best of our knowledge, no plasmonic polarizer has been demonstrated experimentally on the SOI platform. On the other hand, we recently presented a plasmonic platform using the horizontal nanoplasmonic slot waveguide (HNSW). The platform offers advantages of compact device size, relatively low propagation loss, high coupling efficiency to conventional silicon photonics devices and compatibility with the complementary metal-oxide-semiconductor (CMOS) fabrication process . Various devices have been realized, including an ultra-compact power splitter  and modulator . The HNSW-platform thus presents an ideal approach to address the long-device-length constraint of the integrated polarizer on the SOI platform. In this paper, we propose and realize an ultra-compact TE-pass polarizer based on the HNSW.
2. Design principle and simulations
The schematic diagram of the proposed HNSW-based polarizer is shown in Fig. 1(a). The entire structure sits on a commercially available SOI wafer. The device consists of five parts: i) an 500nm-wide input channel waveguide, ii) a linearly-tapered coupler of length Lc, iii) the HNSW active region of width Wp and length Lp, iv) another linearly-tapered coupler of the same length Lc, and v) an 500nm-wide output channel waveguide. To avoid ambiguity, part (iii) is named as the active region while polarizer refers to the entire structure. The cross-section of the HNSW in the active region is illustrated in Fig. 1(b). A ~10nm-thick (h) thermal oxide (SiO2) slot is inserted between the copper (Cu) and silicon (Si) core, capable to support the propagation of optical waves. Copper (Cu) is chosen as the metal material due to its CMOS-compatibility, as well as the low ohmic loss originated from the small imaginary part of the its permittivity (~-109 + 9.8i) at 1550nm wavelength. The coupler length (Lc) is set at 1µm throughout this work, sufficient to ensure a low coupling loss . The HNSW height (H) is kept at 340nm, corresponding to the un-etched silicon device layer thickness of the incoming SOI wafer. The polarizer can thus be defined in a single full-etch step to reduce fabrication complexity for yield enhancement.
To function as a TE-pass polarizer, the HNSW in the active region needs to prohibit the propagation of transverse-magnetic (TM) wave. We start by looking into the modal profile of the TE and TM modes of the HNSW, as shown in Fig. 2(a) and 2(b), respectively. The effective refractive index (neff) and modal profiles are computed by the finite element method (FEM) using commercial mode solver Rsoft-FemSIM. While the TE mode is concentrated in the two vertical SiO2 slots, the TM mode is mainly confined in the top horizontal slot. The distinct confinement regions for the TE and TM modes constitute the design principles of our HNSW polarizer. One can thus strips off the TM mode by reducing the HNSW (horizontal slot) width in the active region, while imposing minimum impact on the TE mode. The change of neff is subsequently plotted with respect to the HNSW width (Wp), as illustrated in Fig. 2(c). Continuous reduction of the HNSW width results in decreasing effective refractive index and poorer optical confinement in both TE and TM mode. The TM mode is much more susceptive to this trend, resulting in the mode cut-off below 210nm HNSW width. The inset of Fig. 2(c) corresponds to the TM modal profile beyond cut-off, in which leakage of light into the underneath bottom oxide (BOX) layer is clearly evident.
To further illustrate the concept, we proceed to simulate the entire polarizer structure. Three dimensional (3-D) finite-element-time-domain (FDTD) method is employed for this study, which has been well known for its ability to predict the performance of the plasmonic devices . In particular, two key polarizer performance parameters are studied. They are the insertion loss (IL) and polarization extinction ratio (PER), as in Eq. (1) following their conventional definition. PinX and PoutX stand for the input and output power after passing through the entire polarizer for the X-polarization (X = TE or TM), respectively. Figure 3 displays the change of these two parameters with respect to the HNSW width (Wp). The negative of the insertion loss is plotted for the compactness of the Y-axis. The active region length (Lp) is set at 1µm for the current simulation. The influence of it on the polarizer performance will be further illustrated in the next section. Polarization extinction ratio increases sharply around 210nm HNSW-width, mainly due to the TM mode cut-off. This is in good agreement with the FEM analysis, providing a further justification for the validity of the proposed polarizer. The PER increment gradually saturates towards narrower HNSW-width, with more than 17dB PER predicted at 50nm HNSW-width. On the other hand, insertion loss increases slightly as we decrease the HNSW-width from 260nm to 50nm. As shown in Eq. (1) (a), the insertion loss takes into account both the tapering losses (2 x Losstaper) and the propagation loss through active region (Lossprop) for the TE mode. A break-down analysis reveals that the HNSW-width reduction imposes opposite effects on these two losses. The trade-off between them accounts for the gentle increment, as well as the small fluctuation (<1dB) of the insertion loss curve.
3. Fabrication and experiments
As a proof-of-concept, we fabricated the proposed TE-pass polarizer in a CMOS-compatible process using an 8-inch SOI wafer with 340-nm-thick (H) silicon device layer and 2-μm-thick BOX layer. The entire process flow is illustrated in Fig. 4. The silicon waveguides were first defined using the 248nm DUV lithography, without the photo-resist trimming process . Instead, high energy exposure is used to create the narrow HNSW width. This will allow a better fabrication control of the waveguide dimensions, in addition to the inherent process simplification. With the help of a 70-nm-thick SiO2 hard mask deposited, the polarizer was formed by reactive ion etching (RIE) of the silicon through to the BOX layer [Fig. 4(b)]. The scanning electron microscope (SEM) image of the fabricated device after this step is shown in Fig. 5(a). After removing the SiO2 hard mask, a 75-nm-thick Si3N4 layer and a 1-μm-thick SiO2 layer were deposited sequentially in a plasma enhanced chemical vapor deposition (PECVD) process. Windows were then opened by removing the SiO2 layers in the designed copper (Cu) window [Fig. 4(c)]. A combination of dry and wet etch processes are employed to avoid over-etch the SiO2 layer, while ensuring a reasonable process time. The remaining Si3N4 layer was subsequently wet-etched, followed by thermal oxidation to form the ~10-nm-thick SiO2 layer (h) on the exposed Si core [Fig. 4(d)]. Si3N4 is chosen as the etch stop layer, due to its relatively high etch selectivity (1:20) with respect to silicon. Next, 1-μm-thick Cu was deposited on the whole wafer, followed by Cu chemical mechanical polishing (Cu-CMP) to remove those outside the intended window [Fig. 4(e)]. A 1-μm-thick SiO2 was further deposited as the upper cladding. Finally, Deep trench was form with > 100-μm-depth etch into the silicon substrate [Fig. 4(f)]. The deep trench eliminates the need of end-facet polishing for fiber coupling.
Two sets of devices with different HNSW width were fabricated (S1, S2), with their enlarged XTEM images illustrated in Fig. 5(b) and 5(c). The HNSW widths (Wp) are measured at 71nm and 144nm respectively. We note here that the fabricated core has a pentagonal shape, which is different from the simulated square core shape. An FEM analysis using Lumerical Mode Solution confirms that both cores possess identical modal profiles with small effective refractive index difference (<1%). Each set contains seven devices with different polarizer length (Lp) from 1µm to 10µm. According to the design principle presented earlier, both sets of devices satisfy the TM-cutoff condition. Figure 5(d) plots the stimulated and measured insertion losses of the seven devices in set S2 (144nm-width) for both TE and TM modes. A tunable laser source is used as the light source, with the wavelength fixed at 1550nm. The polarization of the input light is adjusted to either TE or TM using a polarization controller, before coupling into the waveguide devices through a lensed fiber of spot diameter 2.5µm. Another identical lensed fiber is used to couple light out from the devices to a power meter. The insertion loss is normalized with respect to an identical reference silicon waveguide without the polarizer inserted into it. A linear curve is obtained from the simulation result of the TE mode insertion loss with respect to the active region length. The propagation loss is computed at 0.68dB/µm. A similar trend is observed from the experiment, with a smaller propagation los of ~0.4dB/µm. The measured insertion loss for TE mode is also smaller than the simulated result. These could be due to the fact that the complex permittivity of our deposited Cu is different from that of the simulator material database . However, we have no direct evidence. A detail measurement of the optical property of Cu is beyond the scope of this work. On the other hand, stimulated TM mode insertion loss grows rapidly with active region length increment for Lp <1µm. The growth rate gradually reduces towards longer length when majority of the TM optical waves has been swept out. The TM mode measurement result supports the theoretical prediction with a slightly lower insertion loss. This could be due to the propagation of light in the BOX layer, as part of the leaked optical power is reflected back in the BOX/silicon substrate interface . Maximum polarization extinction ratio of greater than 16dB is achieved with 1-3μm active region length. The 1μm-length device thus represents the optimized choice from the energy efficiency point of view, with the lowest insertion loss of 2.2dB. This represents a three order of magnitude size reduction from the previous TE-pass polarizer reported on the SOI platform .
Figure 6 illustrates the transmission spectrum of the TE and TM modes for both sets of devices with 1µm active region length. An amplified spontaneous emission (ASE) source is used as the light source for this experiment. The power meter is also replaced by an optical spectrum analyzer (OSA) for output detection. Greater than 16dB polarization extinction ratio are achieved for both devices across the measured wavelength range from 1525nm to 1605nm, which is limited by the spectrum flatness from our ASE source. Further PER enhancement can be achieved through the introduction of 90-degree sharp bend into the polarizer active region . The average insertion losses are 2.2dB and 2.4dB for 144nm wide and 71nm-wide devices, respectively. A relatively flat transmission spectrum is obtained for the TE wave. The small fluctuation (<1dB) is believed to be originated from the experimental set-up and ASE source. The case for the TM input light is completely different, in which significant spectrum oscillation is observed. This could be again due to the propagation of light in the BOX layer, which also explains the similar TM mode insertion loss measured for both sets of devices. One possible solution to reduce such oscillation is to introduce a large horizontal miss-alignment between the input and out waveguides to the lensed fiber.
In summary, we have proposed and demonstrated an ultra-compact broadband TE-pass polarizer using the HNSW on the SOI platform. The design principle was clearly illustrated, utilizing the distinct confinement region of the TE and TM polarization in the HNSW. Both FEM and 3D-FDTD simulation confirmed that TM mode was cut-off below the HNSW-width of 210nm. Proof-of-concept devices were subsequently fabricated in a CMOS compatible process and characterized, leading to the first demonstration of plamonic polarizer on the SOI platform. The active region length was found to be optimized at 1μm in terms of energy efficiency, which agrees well with the theoretical prediction. This represents a one-thousand-times length reduction from similar device on the SOI platform. The broadband device response was finally measured. More than 16dB polarization extinction ratio was obtained across 80nm-wavelength-range, with a relatively low insertion loss of 2.2dB. The compact device footprint, coupled with the excellent broadband performance, could provide a simple yet satisfactory solution for the polarization dependent drawback on the SOI platform.
This work was supported by the Science and Engineering Research Council of A*STAR (Agency for Science, Technology and Research), Singapore. The SERC grant number is 092-154-0098.
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