The design and characterization of silicon-on-insulator mid-infrared spectrometers operating at 3.8μm is reported. The devices are fabricated on 200mm SOI wafers in a CMOS pilot line. Both arrayed waveguide grating structures and planar concave grating structures were designed and tested. Low insertion loss (1.5-2.5dB) and good crosstalk characteristics (15-20dB) are demonstrated, together with waveguide propagation losses in the range of 3 to 6dB/cm.
©2013 Optical Society of America
While silicon photonic waveguide circuits were originally conceived to be used for datacommunication and telecommunication applications, a myriad of other application domains have emerged in recent years, including the use of these waveguide circuits for sensing applications  and biomedical instrumentation [2,3]. Just like in datacommunication applications, the rationale for realizing these functions on a silicon photonics platform is related to the maturity and scalability of the CMOS fabrication technology used to fabricate these photonic integrated circuits, which can lead to low-cost advanced photonic integrated circuits. Typically one holds on to the 1.3-1.55μm wavelength range also for these non-communication oriented applications. However, spectroscopic sensing applications, which allow analyzing the content of gas or liquid samples of interest by probing their absorption spectrum, would benefit from the extension of the wavelength range supported by the silicon-on-insulator material platform. Research in this direction has started over the few last years, first by addressing the short-wave infrared wavelength range up to 2.5μm, both for linear  and nonlinear optics  applications. Silicon however is optically transparent up to 8μm, which allows to dramatically extend the wavelength range of operation of the platform . This is beneficial for spectroscopic sensing applications, since the absorption cross-sections of the molecules of interest become much stronger in the mid-infrared (2.5-8μm). In this paper we present the first integrated mid-infrared spectrometers realized on silicon-on-insulator, fabricated in a CMOS pilot line, targeting the 3.8μm wavelength range. This wavelength range lies close to the edge of the transparency window of the buried SiO2 layer , which defines the actual transparency window of the silicon-on-insulator material platform. The developed spectrometer can find applications in future integrated spectroscopic sensor systems, in miniature spectroscopic telescope systems (given the atmospheric transmission window of 3-5μm) or as a wavelength multiplexer for future quantum cascade / interband cascade laser light engines.
2. MidIR silicon photonics technology
We used two slightly different material platforms for the fabrication of midIR silicon photonic waveguide circuits in a CMOS pilot line: the imecAP and imec400 process. ImecAP is a multiple project wafer run service (MPW) offered by imec, Belgium through ePIXfab . In the imec400 process we used dedicated CMOS processing for the waveguide fabrication. The detailed fabrication process is explained in the following sub-sections.
The imecAP process starts with 200mm SOI wafers with 220 nm of crystalline silicon (c-Si) on top of 2000 nm of buried oxide. First 5 nm of thermal SiO2 is grown after which 160 nm of amorphous silicon (a-Si) is deposited using a low-pressure chemical vapor deposition process. The 5 nm of thermal SiO2 serves as protective layer for the underlying c-Si during the waveguide etching. On top of the a-Si 10 nm of SiO2 and 70 nm of SiN are deposited using plasma enhanced chemical vapor deposition process. This SiN layer serves as a hard mask for the waveguide etching and as a polish stop layer during the chemical-mechanical planarization of the wafer. The wafer stack is then annealed at 750 °C for 30 minutes, which converts the a-Si to poly-silicon (p-Si). This step is performed in order to increase the temperature budget for eventual post-processing on the silicon wafer. This wafer stack is used for waveguide circuit fabrication using 193nm deep UV lithography and halogen based dry etching. Figure 1 schematically shows the wafer-stack fabrication steps.
To define a waveguide in the Si device layer that is 380 nm thick (160 nm p-Si and 220 nm c-Si) different etch steps are available. For the waveguides presented in this paper we make use of single step 160nm etch and a two-step 380 nm etch (in a first step the 160 nm poly-silicon is etched while in a second step the 220 nm c-Si layer is etched after removal of the thin SiO2 intermediate layer). As a 193nm lithography stepper tool is being used the alignment accuracy for two etch step process is better than 50 nm. Additionally, a 230nm etch step is available for parts of the photonic integrated circuits, such as the grating couplers and distributed Bragg reflectors in the planar concave grating spectrometers.
After etching the photoresist is stripped and a blanket layer of SiO2 is deposited using a high density plasma process. After this deposition chemical mechanical planarization is performed to flatten the topography. This planarization process stops on the 70 nm SiN mask. Now this SiN is stripped off using hot phosphoric acid and 800 nm of blanket SiO2 layer is deposited again to serve as top cladding for the waveguide circuits. Also now a flat top surface is achieved which is desirable for some post-processing e.g. the bonding of III-V semiconductor material on top for light sources or photo-detectors. This lies however outside the scope of this paper. The imecAP process is offered in a multi-project wafer run service, which allows the cost-effective fabrication of mid-infrared photonic integrated circuits alongside conventional near-infrared circuits. Figure 2(a) shows a representative scanning electron microscope (SEM) cross-section of a waveguide realized in this advanced passive platform, with the associated mode profile at 3.8μm plotted in Fig. 2(d).
The imec400 process uses 200mm SOI wafers with a 400 nm thick crystalline silicon device layer on top of 2000 nm of buried oxide. A thermal oxide/LPCVD SiN stack is used as a hard mask for the waveguide definition, similar to the imecAP process. This pattern is further transferred to the underlying 400 nm Si using selective dry etching through the complete device layer stack. After waveguide etching the SiN hardmask is stripped. No top-cladding is applied in this case. Figure 2(b) shows a bird’s eye SEM view of an imec400 waveguide. The mode profile is shown in Fig. 2(e).
3. Spectrometer design and measurements
Single mode waveguides as well as two types of spectrometers (arrayed waveguide gratings and planar concave gratings) were realized in both the imecAP and imec400 processes. The waveguide circuits were characterized using grating coupler based fiber-chip interfaces connected to input and output ports of different devices on the chip. The details of the measurement setup are discussed in , to which only two changes were made. Firstly, the source now consists of a tunable quantum cascade laser (tuning range: 3725 nm – 3895nm) from Daylight Solutions which was used also in [10, 11] and secondly instead of butt coupling to the waveguide structures vertical coupling is used. The designs and corresponding measurements are discussed in the following sub-sections.
3.1 Waveguides and fiber-to-chip grating couplers
Three types of waveguide structures were designed and fabricated as shown in Fig. 2. WG1 and WG2 are designed for imecAP while WG3 is designed for imec400. The single mode widths for these waveguides are calculated using a full vectorial finite difference solver . WG1 is an imecAP rib waveguide fabricated by selectively etching only the p-Si and stopping on the 5nm thermal oxide grown between the 220nm c-Si and 160 nm p-Si. The waveguide dimensions are H = 380 nm, W = 1350 nm, D = 160 nm and it has a top oxide thickness of 800 nm. WG2 is an imecAP strip waveguide fabricated by using two selective etch steps (160 nm and 220 nm) lithographically aligned to each other. The waveguide dimensions are H = 380 nm, W1 = 1150 nm, W2 = 1450 nm, D = 380 nm and it also has a top oxide thickness of 800 nm. W2 is deliberately selected 300 nm wider than W1 to allow for a misalignment of the second lithography step, which is very safe considering the 50nm alignment accuracy. WG3 is an imec400 strip waveguide fabricated by selectively etching the 400 nm c-Si in one step. The waveguide dimensions are H = 400 nm and W = 1350 nm. No top oxide cladding is used in this case.
The different components fabricated in this work are connected to grating couplers as input and output ports for vertical coupling to optical fiber. The single mode waveguide structures are tapered up to 15 μm over 400 μm and the grating couplers are fabricated in this wider section. The grating coupler layouts are shown in Fig. 3. GC1 is connected to components with input/output waveguides type WG1, GC2 is connected to components with input/output waveguides type WG2 and GC3 is connected to components with input/output waveguides type WG3. The period, fill factor and etch depths for GC1, GC2 and GC3 are (2000nm, 50%, 230nm), (2000nm, 50%, 230nm) and (2140nm, 78%, 400nm) respectively. All grating couplers have 20 periods. In Fig. 3, for GC1 and GC2 the top oxide cladding is not shown. The simulated insertion loss and 3dB optical bandwidth of such grating coupler structures are (−10dB, 220nm), (−13dB, 220nm), (−5dB, 180nm) respectively around 3.8μm. These grating coupler structures are polarization sensitive and only couple transverse electric (TE) polarized light to the waveguide circuit. Therefore all subsequent measurements are for TE polarized light.
To characterize the waveguide losses we used cut back method where spirals of three different lengths are used for each waveguide type. The bend radii in the spirals (70 μm for WG1, 30 μm for WG2 and 70 μm for WG3) are at-least two times larger than the simulated minimum bend radius; therefore no excess bend loss is expected. From Fig. 4 one can find that the losses at 3760 nm are 5.3 dB/cm, 5.8 dB/cm and 3.1 dB/cm for waveguides WG1, WG2 and WG3 respectively. Figure 5 shows the waveguide loss as function of wavelength for the respective waveguide types. Part of this loss can be attributed to substrate leakage loss, especially at longer wavelengths, as illustrated in Fig. 6, which shows the simulated substrate leakage loss as a function of wavelength for the different waveguide geometries.
Clearly the losses of the WG3 geometry are lower than the waveguide structures implemented in the imecAP process. This is related to the scattering losses in the poly-crystalline silicon overlay (160nm p-Si) of WG1 and WG2. While less performant in terms of waveguide losses, the imecAP process has the advantage that near-infrared and mid-infrared circuits can be implemented side by side on the same multi-project wafer, thereby leveraging cost-sharing. Methods to further reduce the scattering losses have been presented in literature [13, 14], which can in principle also be applied to this imecAP process. The lower substrate leakage contribution for WG1 is related to the rib type geometry used, compared to the strip waveguide configurations for WG2 and WG3. Further reduction of the substrate leakage loss is possible by increasing the buried oxide layer thickness from 2μm to 3μm, which is also a commercially available buried oxide layer thickness [10, 11].
3.2 Arrayed waveguide gratings
Two arrayed waveguide grating (AWG) de-multiplexers for imecAP (named AWG1 and AWG2) and one for imec400 (named AWG3) were designed. The schematic of such an AWG is shown in Fig. 7 with important layout parameters labeled. An AWG consists of two free propagation regions (FPR) connected together through an array of delay waveguides with constant length increment between them. The other ends of the FPRs (also called star coupler) connect to input and output apertures. Light enters the input star coupler through an input port where it is diffracted towards the array of delay waveguides. Due to the constant length increment between delay waveguides, at the output star coupler the light in consecutive delay arms has a constant phase delay, which depends on the actual wavelength. As a consequence different wavelengths are focused at different output ports. More information on the design and operation principle of an AWG can found in .
The specifications and layout parameters of the different AWGs designed in this work can be found in Table 1. All AWGs are designed for TE-polarized light. In terms of specifications AWG1 and AWG2 are very similar but their layout and fabrication is different. AWG1 is fabricated in a single etch step using WG1 waveguide structures while AWG2 uses a shallow to deep transition for the star coupler apertures, as shown in Fig. 7(b), while the delay waveguides are fabricated using WG2 waveguide structures. AWG3 is also fabricated in single etch step but using WG3 waveguide structures. Phase errors due to different fabrication anomalies like silicon thickness variation, waveguide width variation, etc. limit the achievable crosstalk level . To make the AWGs more fabrication tolerant we used expanded waveguides in the straight sections of the delay lines, as shown in Fig. 7(a), in order to reduce the phase noise.
Figure 8 shows the transmission measurement results for all three AWGs. The transmissions are normalized to corresponding reference waveguides as to only represent the loss of AWGs themselves.
The performance of these AWG (de)multiplexers comes close to the state-of-the-art for silicon-on-insulator AWGs at telecommunication wavelengths (insertion loss of −1 dB and cross-talk of −25dB ), which is remarkable since these devices have gone through many optimization cycles. The higher insertion loss in AWG3 is related to the larger losses at the waveguide / star coupler interface due to the abrupt transition between fully etched strip waveguides and the 400nm silicon free propagation region. While there are differences in design between AWG1 and AWG2 as indicated in Table 1, their performance is similar.
3.3 Planar concave gratings
To show the flexibility and the potential of the platform for mid-infrared spectrometers two planar concave gratings (also known as echelle gratings) were also designed. The design is based on the Rowland geometry with one stigmatic point . PCG1 and PCG2 have been designed for and fabricated in imecAP and imec400 processes, respectively. The schematic of a PCG is shown in Fig. 9 mentioning important layout parameters. The PCG combines the functionality of a flat grating to spatially separate different wavelengths and a curved mirror, which can focus the light to one or more output waveguides. The light enters from an input aperture into the free propagation region (FPR) after which it diffracts and hits the concave grating on the other end, which reflects as well as focuses different wavelengths at different output waveguides.
In order to enhance the reflectivity of the grating facets, a distributed Bragg reflector (DBR) is implemented as can be seen in Fig. 9. More details about the design and functioning of a PCG can be found in [18, 19]. The specifications and layout parameters of both PCGs designed in this work are shown in Table 2. Both PCGs are designed for TE-polarized light.
Figure 10 shows the transmission measurement results for both PCGs. The transmissions are again normalized to reference waveguides such that only the insertion loss of PCGs themselves is shown. Similar conclusions as in the case of the arrayed waveguide gratings can be drawn with respect to the differences between the imecAP and imec400 device in terms of insertion loss. The higher crosstalk in PCG2 is attributed to (1) air top clad as compared to oxide top clad in PCG1 (2) different non-optimized layout parameters (e.g. aperture width of 5 μm as compared to 3 μm in PCG1 for same output waveguides spacing) and (3) aperture and star coupler abrupt deep etch transition.
In this paper we demonstrated the first complex midIR photonic integrated functionality, implemented on a silicon waveguide platform at wavelengths up to 3850nm. The devices were fabricated in a CMOS pilot line, illustrating the potential for large-volume and low-cost manufacturing of such circuits. Moreover, since the imecAP process is offered as a multi-project wafer run service, these midIR circuits can be designed alongside near-infrared photonic integrated circuits. Both arrayed waveguide grating demultiplexers as planar concave grating structures were designed and fabricated. Although among the devices reported in this paper the AWGs perform better than PCGs, for applications requiring a large channel spacing PCGs can be a better choice.
This work was carried out in the framework of the FP7-ERC-MIRACLE project. Goran Z. Mashanovich would like to acknowledge support by the Royal Society through his Royal Society Research Fellowship.
References and links
1. E. Hallynck and P. Bienstman, “Integrated optical pressure sensors in silicon-on-insulator,” IEEE Photon. J. 4(2), 443–450 (2012). [CrossRef]
2. M. C. Estevez, M. Alvarez, and L. M. Lechuga, “Integrated optical devices for lab-on-a-chip biosensing applications,” Laser Photon. Rev. 6(4), 463–487 (2012). [CrossRef]
3. K. De Vos, I. Bartolozzi, E. Schacht, P. Bienstman, and R. Baets, “Silicon-on-Insulator microring resonator for sensitive and label-free biosensing,” Opt. Express 15(12), 7610–7615 (2007). [CrossRef] [PubMed]
4. G. Roelkens, W. M. J. Green, B. Kuyken, X. Liu, N. Hattasan, A. Gassenq, L. Cerutti, J. B. Rodriguez, R. M. Osgood, E. Tournie, and R. Baets, “III-V/silicon photonics for short-wave infrared spectroscopy,” J. Quantum Electron. 48(2), 292–298 (2012). [CrossRef]
5. X. Liu, B. Kuyken, G. Roelkens, R. Baets, R. M. Osgood Jr, and W. M. J. Green, “Bridging the Mid-Infrared-to-Telecom Gap with Silicon Nanophotonic Spectral Translation,” Nat. Photonics 6(10), 667–671 (2012). [CrossRef]
6. R. Soref, “Mid-infrared photonics in silicon and germanium,” Nat. Photonics 4(8), 495–497 (2010). [CrossRef]
7. R. A. Soref, S. J. Emelett, and W. R. Buchwald, “Silicon waveguided components for the long-wave infrared region,” J. Opt. A, Pure Appl. Opt. 8(10), 840–848 (2006). [CrossRef]
9. G. Z. Mashanovich, M. M. Milošević, M. Nedeljkovic, N. Owens, B. Xiong, E. J. Teo, and Y. Hu, “Low loss silicon waveguides for the mid-infrared,” Opt. Express 19(8), 7112–7119 (2011). [CrossRef] [PubMed]
10. M. M. Milosevic, M. Nedeljkovic, T. B. Masaud, E. Jaberansary, H. M. H. Chong, N. G. Emerson, G. T. Reed, and G. Z. Mashanovich, “Silicon waveguides and devices for the mid-infrared,” Appl. Phys. Lett. 101(12), 121105 (2012). [CrossRef]
11. C. Reimer, M. Nedeljkovic, D. J. M. Stothard, M. O. S. Esnault, C. Reardon, L. O’Faolain, M. Dunn, G. Z. Mashanovich, and T. F. Krauss, “Mid-infrared photonic crystal waveguides in silicon,” Opt. Express 20(28), 29361–29368 (2012). [CrossRef] [PubMed]
14. Q. Fang, J. F. Song, S. H. Tao, M. B. Yu, G. Q. Lo, and D. L. Kwong, “Low Loss (~6.45dB/cm) Sub-Micron Polycrystalline Silicon Waveguide Integrated with Efficient SiON Waveguide Coupler,” Opt. Express 16(9), 6425–6432 (2008). [CrossRef] [PubMed]
15. M. K. Smit and C. Van Dam, “Phasar-based wdm-devices: Principles, design and applications,” IEEE J. Sel. Top. Quantum Electron. 2(2), 236–250 (1996). [CrossRef]
16. W. Bogaerts, P. Dumon, D. Van Thourhout, D. Taillaert, P. Jaenen, J. Wouters, S. Beckx, V. Wiaux, and R. Baets, “Compact wavelength selective functions in silicon-on-insulator photonic wires,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1394–1401 (2006). [CrossRef]
17. W. Bogaerts, S. Selvaraja, P. Dumon, J. Brouckaert, K. De Vos, D. Van Thourhout, and R. Baets, “Silicon-on-Insulator Spectral Filters Fabricated with CMOS Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 33–44 (2010). [CrossRef]
18. R. Marz, Integrated Optics, Design and Modeling. (Artech House Inc., 1994)
19. J. Brouckaert, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Planar concave grating demultiplexer fabricated on a nanophotonic silicon-on-insulator platform,” J. Lightwave Technol. 25(5), 1269–1275 (2007). [CrossRef]