Abstract

This paper presents an ultra-low power SiGe BiCMOS IC for driving a 10 channel electro-absorption modulator (EAM) array at 113Gb/s for wavelength division multiplexing passive optical network (WDM-PON) applications. With an output swing of 2.5Vpp, the EAM driver array consumes only 2.2W or 220mW per channel, 50% below the state of the art. Both the output swing and bias are configurable between 1.5 and 3.0Vpp and 0.75-2.15V respectively.

© 2013 OSA

1. Introduction

WDM technologies have been successfully deployed for many years in metro and core networks; they provide tremendous system capacity with long distance transmission. Lately, service providers are deploying passive WDM technologies for wireless/wireline backhauling, business connectivity, and fiber-to-the building (FTTB) applications. In access networks, however, WDM technology is not commonly used yet. This is due to the relatively low required per-user data rates at present and more importantly due to the higher cost needed to deploy entire WDM access networks compared to already massively deployed time division multiplexing (TDM) PONs. There is a strong need for new WDM access components which are compact, cost-competitive and mass-manufacturable, in particular at the optical line termination (OLT) of a central office (CO) where high degree integration is a must. While a WDM-PON OLT could in principle be built from pluggable transceivers, a cost-, footprint- and energy-optimized solution is not available today, mainly due to the lack of highly integrated multi-channel transceiver arrays [1].

A reflective WDM-PON network as shown in Fig. 1 was proposed in [1]. The major component integration challenge for this scheme is at the OLT. In its downstream direction 10 wavelength channels of reflective transmitters (R-TXs) using 10 reflective electro-absorption modulators (REAMs) are integrated into an array. One of the most challenging components to be developed for R-EAM TXs is an ultra-low power consumption 10 channel EAM/REAM driver array operating at 10-11.3 Gb/s data rates. As typically a discrete EAM driver consumes 1W, integrating 10 such EAM devices into a single array would require a total power consumption of 10W, which is much too high for a single IC to handle without a costly, power consuming thermo electric cooler (TEC). By lowering the power consumption of the drivers, TECs can be avoided, giving components that aren’t only compact and cost-efficient, but also energy-efficient.

 

Fig. 1 Reflective WDM-PON network

Download Full Size | PPT Slide | PDF

In this paper, an array of 10 EAM drivers at 10-11.3Gb/s each is presented, to achieve a total data rate of 113Gb/s. To the best of our knowledge such EAM driver arrays are not currently available on the open market, nor published in the literature. This is the first 10 channel driver array for EAMs and the lowest power consumption for an EAM driver so far reported, 50% below the state of the art.

The remainder of this paper is organized as follows. The next section illustrates the chip level architecture of the EAM driver array. Different techniques to reduce the power consumption are explained in section 3. The fourth section presents the experimental results. After that the power consumption of the designed array is discussed and compared to the state of the art in section 5. Finally, conclusions are drawn in the last section.

2. EAM driver chip architecture

Figure 2 depicts the simplified building blocks of the EAM driver. It includes an input that is differentially matched to 100Ω, a predriver block to amplify the input signal and to drive the large capacitive input of the driver output stage. This predriver can also control the pulse width to compensate for the non-linearity of the (R)EAM. The predriver is directly followed by an EAM driver stage, which can control the bias current and modulation current of the EAM modulator. The control is implemented using a serial peripheral interface (SPI), which can set both the bias and modulation current with a 4-bit resolution. The bias and modulation current can be set independently for every channel to optimize the settings of the 10 EAMs according to the transmitted wavelength.

 

Fig. 2 EAM driver array IC building blocks with DC-coupled outputs.

Download Full Size | PPT Slide | PDF

3. Power consumption reduction techniques

Figure 3(a) shows a simplified schematic of the driver output stage in order to clarify the origins of the driver power consumption [2]. Keeping in mind that the EAM needs a swing between 2 and 3Vpp, one can identify a number of reasons for the large power consumption of commercial drivers, which is typically as high as 1W for a single driver. First of all, there is a necessity for a high supply voltage to provide sufficient headroom for transistors when generating the required relatively large output swings. For commercial EAM driver ICs, 5.2V is a recurring supply voltage (Vcc2 in Fig. 3(a)), which is used for all building blocks in the IC. However, most blocks can operate at much lower power supplies. Secondly, the EAM is typically shunted by a 50Ω termination resistor and as the EAM and driver are several inches/cm apart in most cases, the output impedance of the driver IC also needs to be 50Ω, to minimize reflections. As a consequence, the driven load is 25Ω, which means an output swing of 2.5Vpp requires a modulation current, IMOD, of 100mA. This yields a power consumption of 520mW in the last stage alone, when the supply is 5.2V. In third place, the driver stage uses a differential pair, while only a single-ended output is needed for the EAM. The pair switches the modulation current between the right arm, containing the EAM, and the left arm, connected to a dummy load to preserve symmetry. Since only the right arm drives the EAM, the current in the left arm is a waste of power

 

Fig. 3 Simplified driver output stages, (a) typical, (b) reduced power.

Download Full Size | PPT Slide | PDF

These observations led to a new design, combining different power reduction techniques as shown in Fig. 3(b). Unfortunately, a relatively high supply voltage is always necessary in the output stage of the driver. However, the supply voltage can be lowered depending on the required bias and modulation voltage (set by IBIAS and IMOD respectively). In this design a supply up to 4.5V was chosen (Vcc2 in Fig. 3(b)). On the other hand it isn’t necessary to use this (high) supply voltage across the entire IC. Other block can be supplied by a far lower voltage of 2.5V (Vcc1 in Fig. 2). Secondly, the 50Ω that terminates the driver can be increased when the transmission line between the EAM and the driver is made shorter. By tightly integrating the EAM and the driver, the transmission line can become as short as 2.5mm. An increased output impedance, RBT, of 250Ω was chosen, which allows for a lower modulation and bias current, I’MOD and I’BIAS, in the driver to achieve the same bias and modulation voltage. This reduces the power consumption by 35% for an output swing of 2.5Vpp. Increasing RBT further would deteriorate the signal quality due to reflections, while it would only reduce the power consumption marginally. Note that this technique is only possible in case the driver is DC-coupled to the EAM. Using an AC-coupled output would make the supply voltage grow with increasing output impedance in order to maintain sufficient headroom. Also broadband bias-tees were avoided since their sizes are too large to be used in the 10 channel array, both on- and off-chip.

Finally, the power consumption wasted in the left arm of the differential pair is reduced by using a third power supply, Vcc3, of 1.8V. This provides a power reduction of 20%. Careful modeling of the assembly and the on-chip/off-chip interconnections allowed to co-simulate the driver circuits with various parasitic elements and the EAM equivalent model in order to optimize the signal quality at strongly reduced power consumption.

4. Experimental results

The 10 channel x 11.3Gb/s EAM driver IC was fabricated in a 0.13µm SiGe BiCMOS process. Figure 4 shows its die micrograph. The array of 10 separate drivers is clearly visible. The SPI-register can be seen on the lower left side, with the data path running from bottom to top. The total chip area is 5.5 × 1.3mm2, which is determined by the 500µm pitch between the 10 EAM channels and the number of I/O pads. This gives sufficient room for on-chip decoupling capacitances, which is more than 2.5nF for each power supply.

 

Fig. 4 EAM driver array IC micrograph.

Download Full Size | PPT Slide | PDF

Figure 5(a) shows the measured optical eye diagram at a data rate of 10Gb/s using a commercially available 10 Gb/s EAM. An extinction ratio of 8dB was measured with a 231-1 pseudo random bit sequence (PRBS), consuming as little as 173mW on-chip, while reaching an output voltage swing of 2.5Vpp with a bias voltage of 1.7V.

 

Fig. 5 Output signal (231-1 PRBS): (a) Optical, (b) Electrical (0.5 V/div, 20 ps/div).

Download Full Size | PPT Slide | PDF

Measurement result of an electrical eye diagram, with a 50Ω oscilloscope as load instead of the EAM, is shown in Fig. 5(b). This was measured at the output of the EAM driver at a data rate of 11.3Gb/s and using a 231-1 PRBS sequence. A 20-dB attenuator was added to avoid overloading the high-speed oscilloscope. Multiple adjacent channels were measured to check the influence of crosstalk, which was negligible. With a differential input voltage of 600mVpp and a supply voltage of 4.5V a swing of 2.5Vpp was achieved consuming only 188mW on-chip and 31mW in the external 50Ω, resulting in a total power consumption of 219mW per channel. The 20-80% rise/fall times are 24 and 31ps respectively. The measured output jitter is 18.3 pspp and 2.45psrms, using a data generator with the measured jitter of 14.6pspp and 2.25psrms. Also the pulse width control operates adequately and the programmable crossing point can be adjusted between 38.6% and 59.4% in 8 steps, as shown in Fig. 6 .

 

Fig. 6 Pulse width control, (a) minimum, (b) maximum (231-1 PRBS, 0.5V/div, 20ps/div).

Download Full Size | PPT Slide | PDF

5. Power consumption discussion

A comparison with the power consumption of previous works is shown in Table 1 . (Note that it isn’t always clear whether the papers only report the on-chip power consumption or also include the dissipation in the external resistor.) This table only contains single drivers, except for our presented work. The lowest power consumption reported was 470mW, which shows that this work is 50% below the state of the art. Even though reference [3] had twice the power consumption and the data rate was 10 times lower than the rate in this work, its output swing is considerably higher. By using the techniques reported here, a swing of 3.9V would give a power consumption of 405mW. Note that reference [3] didn’t use a resistor RBT, which corresponds to the technique of increasing it (to infinity). If this was done in this work, the power consumption would decrease to 335mW which was almost 30% below the reported consumption but at 10 times the data rate.

Tables Icon

Table 1. Power consumption comparison

Reference [4] has a similar power/data rate, but only has a swing of 1Vpp. If this work would be designed for a swing of 1Vpp, the power consumption would be below 90mW. This gives a power/data rate that is less than 40% of reference [4].

Figure 7 shows the range of output swings and output bias voltages together with their corresponding power consumptions. It shows that the power consumption can be as low as 200mW for a swing of 2.4Vpp and below 300mW for a swing of 3Vpp. It increases considerably when the bias voltage across the EAM goes up, even though the swing remains the same, especially at higher modulation voltages. This can partly be designated to the increase of the supply voltage, but it is mostly due to the increase of the bias current. Note that a great portion of this rise in power consumption is consumed in the external 50Ω. In the case of a 3V output swing the power consumption grows from 288mW to 401mW for minimum to maximum bias, which corresponds to an increase of 113mW or 40%. The power consumption in the external 50Ω grows from 45mW to 92.5mW, which is a difference of 47.5mW or 42% of the total increase. This points out that the on-chip power and heat generation isn’t that profound, making a coolerless operation still possible.

 

Fig. 7 Reach of the modulation and bias voltage with the corresponding power consumptions.

Download Full Size | PPT Slide | PDF

It should be noted that the power consumption can be decreased even further when the modulator is closely integrated with the driver and the back termination resistor, RBT, can be omitted, as discussed earlier. In this way a reduction of about 15% can be achieved, depending on the swing and biasing. Another possibility to decrease the consumption is to increase the external resistor in parallel with the EAM modulator. Changing the 50Ω into 66Ω would also give a reduction of 15%.

6. Conclusion

We have presented results of an ultra low power 10-channel EAM driver array with an output voltage up to 3Vpp at a total of 113Gb/s for OLT TX arrays in WDM-PON applications. The power consumption is below 220mW per channel, which makes coolerless operation possible, while the eye diagram measurements revealed excellent signal quality.

Acknowledgments

This work was supported by the EU-funded FP7 ICT project C3PO, FWO-Vlaanderen and the Special Research Fund of Ghent University. We would like to thank the COT Business Unit of the Wireline Infrastructure Division of STMicroelectronics for providing chip fabrication, and Ludo Viaene and Danny Frederickx of IMEC for the chip on board wire bonding.

References and links

1. P. D. Townsend, A. Clarke, P. Ossieur, D. Smith, A. Borghesani, D. Moodie, I. Lealman, X.-Z. Qiu, J. Bauwelinck, X. Yin, K. Grobe, B. T. Teipen, R. Jensen, N. Parsons, and E. Kehayas, “Towards colourless coolerless components for low power optical networks,” 37th European Conference and Exhibition on Optical Communication (ECOC, Geneva, 2011), Tu.5.LeSaleve.

2. E. Sackinger, Broadband Circuits for Optical Fiber Communication (John Wiley & Sons, 2005), Chap. 8.

3. B. Liang, D. Chen, B. Wang, G. Situ, T. Kwasniewski, and W. Zhigong, “A monolithic high modulation efficiency cmos laser diode/modulator driver,” in International Conference on Telecommunications (ICT, 2009), pp. 361–363.

4. A. Konczykowska, F. Jorge, C. Kazmierski, F. Blache, and J. Godin, “EAM DFF-driver optimization for 40 Gb/s transmitter,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 12–17, 2005, pp. 1853–1856.

5. T. Yamase, M. Sato, H. Uchida, H. Noguchi, K. Sato, and T. Kato, “10-Gb/s In-line centipede electrode InP MZM and low-power CMOS driver with quasi-traveling wave generation,” in Proceedings OptoeElectronics and Communications Conference (OECC, 2011), pp. 61–62.

6. D.-U. Li, L.-R. Huang, and C.-M. Tsai, “Low power consumption 10 Gb/s SiGe modulator drivers with 9 vpp differential output swing using intrinsic collector-base capacitance feedback network,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC, 2005), pp. 317–320.

7. S. Galal and B. Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18 µm CMOS Technology,” IEEE J. Solid-state Circuits 38(12), 2138–2146 (2003). [CrossRef]  

References

  • View by:
  • |
  • |
  • |

  1. P. D. Townsend, A. Clarke, P. Ossieur, D. Smith, A. Borghesani, D. Moodie, I. Lealman, X.-Z. Qiu, J. Bauwelinck, X. Yin, K. Grobe, B. T. Teipen, R. Jensen, N. Parsons, and E. Kehayas, “Towards colourless coolerless components for low power optical networks,” 37th European Conference and Exhibition on Optical Communication (ECOC, Geneva, 2011), Tu.5.LeSaleve.
  2. E. Sackinger, Broadband Circuits for Optical Fiber Communication (John Wiley & Sons, 2005), Chap. 8.
  3. B. Liang, D. Chen, B. Wang, G. Situ, T. Kwasniewski, and W. Zhigong, “A monolithic high modulation efficiency cmos laser diode/modulator driver,” in International Conference on Telecommunications (ICT, 2009), pp. 361–363.
  4. A. Konczykowska, F. Jorge, C. Kazmierski, F. Blache, and J. Godin, “EAM DFF-driver optimization for 40 Gb/s transmitter,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 12–17, 2005, pp. 1853–1856.
  5. T. Yamase, M. Sato, H. Uchida, H. Noguchi, K. Sato, and T. Kato, “10-Gb/s In-line centipede electrode InP MZM and low-power CMOS driver with quasi-traveling wave generation,” in Proceedings OptoeElectronics and Communications Conference (OECC, 2011), pp. 61–62.
  6. D.-U. Li, L.-R. Huang, and C.-M. Tsai, “Low power consumption 10 Gb/s SiGe modulator drivers with 9 vpp differential output swing using intrinsic collector-base capacitance feedback network,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC, 2005), pp. 317–320.
  7. S. Galal and B. Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18 µm CMOS Technology,” IEEE J. Solid-state Circuits 38(12), 2138–2146 (2003).
    [Crossref]

2003 (1)

S. Galal and B. Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18 µm CMOS Technology,” IEEE J. Solid-state Circuits 38(12), 2138–2146 (2003).
[Crossref]

Galal, S.

S. Galal and B. Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18 µm CMOS Technology,” IEEE J. Solid-state Circuits 38(12), 2138–2146 (2003).
[Crossref]

Razavi, B.

S. Galal and B. Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18 µm CMOS Technology,” IEEE J. Solid-state Circuits 38(12), 2138–2146 (2003).
[Crossref]

IEEE J. Solid-state Circuits (1)

S. Galal and B. Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18 µm CMOS Technology,” IEEE J. Solid-state Circuits 38(12), 2138–2146 (2003).
[Crossref]

Other (6)

P. D. Townsend, A. Clarke, P. Ossieur, D. Smith, A. Borghesani, D. Moodie, I. Lealman, X.-Z. Qiu, J. Bauwelinck, X. Yin, K. Grobe, B. T. Teipen, R. Jensen, N. Parsons, and E. Kehayas, “Towards colourless coolerless components for low power optical networks,” 37th European Conference and Exhibition on Optical Communication (ECOC, Geneva, 2011), Tu.5.LeSaleve.

E. Sackinger, Broadband Circuits for Optical Fiber Communication (John Wiley & Sons, 2005), Chap. 8.

B. Liang, D. Chen, B. Wang, G. Situ, T. Kwasniewski, and W. Zhigong, “A monolithic high modulation efficiency cmos laser diode/modulator driver,” in International Conference on Telecommunications (ICT, 2009), pp. 361–363.

A. Konczykowska, F. Jorge, C. Kazmierski, F. Blache, and J. Godin, “EAM DFF-driver optimization for 40 Gb/s transmitter,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 12–17, 2005, pp. 1853–1856.

T. Yamase, M. Sato, H. Uchida, H. Noguchi, K. Sato, and T. Kato, “10-Gb/s In-line centipede electrode InP MZM and low-power CMOS driver with quasi-traveling wave generation,” in Proceedings OptoeElectronics and Communications Conference (OECC, 2011), pp. 61–62.

D.-U. Li, L.-R. Huang, and C.-M. Tsai, “Low power consumption 10 Gb/s SiGe modulator drivers with 9 vpp differential output swing using intrinsic collector-base capacitance feedback network,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC, 2005), pp. 317–320.

Cited By

OSA participates in Crossref's Cited-By Linking service. Citing articles from OSA journals and other participating publishers are listed here.

Alert me when this article is cited.


Figures (7)

Fig. 1
Fig. 1

Reflective WDM-PON network

Fig. 2
Fig. 2

EAM driver array IC building blocks with DC-coupled outputs.

Fig. 3
Fig. 3

Simplified driver output stages, (a) typical, (b) reduced power.

Fig. 4
Fig. 4

EAM driver array IC micrograph.

Fig. 5
Fig. 5

Output signal (231-1 PRBS): (a) Optical, (b) Electrical (0.5 V/div, 20 ps/div).

Fig. 6
Fig. 6

Pulse width control, (a) minimum, (b) maximum (231-1 PRBS, 0.5V/div, 20ps/div).

Fig. 7
Fig. 7

Reach of the modulation and bias voltage with the corresponding power consumptions.

Tables (1)

Tables Icon

Table 1 Power consumption comparison

Metrics