A strictly non-blocking 8 × 8 switch for high-speed WDM optical interconnection is realized on InP by using the phased-array scheme for the first time. The matrix switch architecture consists of over 200 functional devices such as star couplers, phase-shifters and so on without any waveguide cross-section. We demonstrate ultra-broad optical bandwidth covering the entire C-band through several Input/Output ports combination with extinction ratio performance of more than 20dB. Also, nanoseconds reconfiguration time was successfully achieved by dynamic switching experiment. Error-free transmission was verified for 40-Gbps (10-Gbps × 4ch) WDM signal.
©2012 Optical Society of America
During the past few years, continuous increase in the internet traffic as well as emergence of cloud-based data-intensive services has drastically accelerated the bandwidth demand at the datacenter networks. To meet this growing demand, extremely large-scale datacenters, consisting of over 100,000 servers, are now being built [1, 2]. In these datacenters, servers arranged in each rack are first connected to the top-of-rack (TOR) switch, which is then uplinked to the cluster switches to provide interconnection between the racks. With the increasing data-rate of the aggregated signal inside these cluster switches, however, the existing electronic packet switches are facing more and more challenges in terms of power consumption and latency [3–6].
Under this circumstance, electrical-optical hybrid datacenter network has been proposed as an effective solution in decreasing the power consumption [4–6]. Optical circuit switching (OCS) is the key technology to achieve such hybrid networks. There are several proposals of using micro-electro-mechanical-systems (MEMS) based optical circuit switches for OCS [4, 5]. It has been pointed out, however, that the relatively slow response of MEMS-based switches may limit the effective throughput of these architectures [7, 8].
In order to realize OCS with faster reconfiguration time, high-speed large-scale optical matrix switches are attracting renewed interest. Several monolithically integrated InP photonic switches have been demonstrated based on different approaches. A rearrangeable non-blocking 16 × 16 switch was achieved in a hybrid Clos-Tree architecture by integrating 192 semiconductor optical amplifier (SOA) gate switches on a single InP chip . A monolithic InP 8 × 8 switch was also demonstrated by using an arrayed-waveguide grating (AWG) and integrated tunable wavelength converters .
It has been pointed out that the future datacenter networks would most likely employ commodity network interface cards with WDM (e.g., 10-G × n) optical interfaces [7,11]. In addition, recent analytical studies elucidated the essential benefits of using a strictly non-blocking architecture that allows decentralized control of optical switches to meet the latency requirement . It is therefore of particular importance to develop strictly non-blocking high-speed switches that is transparent to WDM data formats.
In this work, we demonstrate a novel strictly non-blocking WDM-transparent 8 × 8 photonic switch, which is monolithically integrated on an InP chip. Our scheme employs integrated phased-array antennas (PAA) to allow dynamic interconnection between the selected ports with less than 5 ns of reconfiguration time. Owing to the all-passive structure and wavelength-insensitive operation over the entire C-band, 40-Gbps (10-Gbps × 4ch) WDM signal is transmitted successfully with a power penalty below 2 dB.
2. Principle and concept of the N × M switch
Figure 1 shows the schematic of the strictrly non-blocking InP N × M matrix switch, which is based on a similar architecture demonstrated theoretically by Doerr and Dragone . The switch consists of a central large slab region and PAAs attached at both the input and output sides. Each PAA consists of one star coupler and several optical phase shifters to achieve beam-steering/collecting functions. By tuning the phase shifters, arbitrary combination of the input and output ports can be interconnected at the central slab. Since each port is controlled independently to the setting of the other ports, this scheme offers strictly non-blocking (or wide-sense non-blocking) switching. Moreover, there is no waveguide crossing on the entire device, which should provide a significant advantage over the other schemes in terms of scaling the number of port. With an appropriate design of the array shape, optical path length difference can be minimized to achieve nearly wavelength-insensitive operation across the C-band .
We analyze the transmittance through the N × M switch under Fraunhofer approximation. We assume that the number of phase shifters in each PAA at the input and output side is A and B, respectively. Ignoring the propagation loss and excess losses at the phase shifters, the complex amplitude transmittance from the nth input port to the mth output port is expressed asFig. 1, αnp (βnp) represent the angular coordinates of the phase shifter np at the input star couplers (the central slab region). The optical phase shift applied at each phase shifter is described by Δφnp. The function ηs(θ1, θ2) represents the transmittance across a slab coupler, which denotes both side couplers (s = 1 or 3) and central coupler (s = 2), from the input port angle θ1 to the output port angle θ2. Also it is expressed under the Fraunhofer approximation as13]. By coherently adding the contribution from all the possible optical paths of the light (p = 1, …, A, q = 1, …, B), the total transmission is calculated by using Eq. (1).
3. Design and fabrication of the 8 × 8 switch
For the layer structure design of entire InP chip, we appropriated an identical epitaxial structure of p-i-n InP/InGaAsP heterojunction as shown in Fig. 2 . The guiding layer is 500-nm-thick undoped bulk InGaAsP, having a photoluminescence peak at 1.37-μm wavelength to maximize the phase-shifter efficiency . A 300-nm-thick undoped InP layer is inserted in between the InGaAsP core and p-InP upper cladding to reduce the propagation loss.
In order to achieve the 8 × 8 switch with high extinction ratio and low insertion loss, we estimated the switching property by calculating Eq. (1). We consider an 8 × 8 switch design with waveguide width of 2 μm and phase-shifter width of 4 μm, and array pitch at the star coupler of 3 μm and the central slab of 4μm to prevent the directional coupling in the waveguide array. Effective indices are estimated as 3.3 (core) and 3.2 (clad) at the entrance and exit of the slab couplers under the conditions mentioned above. We set the number of phase shifter both A and B in a PAA as 12, and also set the slab length fs for star couplers (f1 and f2) and the central slab (f2) as 168 μm and 3.2 mm, respectively.
Figure 3 shows calculated transmittance of output m when the light is injected into input 1 (a) and input 5 (b). Plots are from all-possible switching combination. This combination consists of the process when input n (n = 1 or 5) is pointing destination output port d (d = 1 to 8), and output m (m = 1 to 8) pointing destination of input port r (r = 1 to 8) simultaneously. Dots indicate the transmittance of ON-states when the input n and the output m are pointing each other (d = m, r = n). On the other hand, circles indicate the transmittance of OFF-states when both input n and output m are pointing diverse ports (d ≠ m, r ≠ n). From both cases of (1) and (2), the insertion loss of lower than 6.3 dB and the extinction ratio of more than 20 dB were achieved at every output port.
Owing to the all-passive waveguide structure, the switch was fabricated by a single metal-organic vapor phase epitaxy (MOVPE) growth followed by double-step reactive ion etching (RIE), polyimide deposition for planarization and electrical isolation, contact opening and electrodes formation by Ti/Au deposition and lift off. The processed chip was mounted on aluminum nitride (AlN) chip carriers by using a conductive epoxy. The electrode pads were wire-bonded to the chip carrier electrodes to access p-contacts. The n-contact was used as a common ground. The chip carrier was mounted on a copper plate with a thermally conductive epoxy for heat removal. To control the phase shifters independently, the electrodes on the chip carrier were wire-bonded to a printed circuit board (PCB), which was electrically connected to a multi-channel switch controller.
Figure 4 shows the photograph of the fabricated InP 8 × 8 switch and its enlarged views in the insets. The switch contains 192 phase shifters, 96 waveguides array attached on the each side of the central slab, 16 star couplers, and a number of other passive waveguides. The complete matrix switch, including the bonding electrode pads, fits in a footprint of 14.3 × 7.2 mm2.
4. Characterization of the 8 × 8 switch
First, static switching was demonstrated by using a TE-polarized light. The driving voltage to each phase shifters was optimized in the range from −2.3 V to + 2.3 V at 1550-nm wavelength. Due to the limitation of wire-bonding and our driver circuit, we could not test all the 8 input/output ports simultaneously. Instead, in this measurement, we have randomly selected 3 input ports and 3 output ports (Input 1, 4, 5, Output 4, 5, 8) to be tested. Such a combination of ports should theoretically represent both the worst case (i.e., edge-to-edge connection from Input 1 to Output 8) and the best case (i.e., center-to- center connection from Input 4, 5 to Output 4, 5).
Figure 5 shows the fiber-to-fiber transmission through every possible connection between the selected input and output ports, which consists of input 1, 5 and output 4, 8 (a) and input 4, 5 and output 4, 5 (b). The ON and OFF-states represent the same notion given in chapter 3. The On-state of d = m, r = n is denoted by In⬄Om, and the OFF-state of d ≠ m, r ≠ n is denoted by In→Od/ Ir←Om. For all the ON-state cases, wavelength-dependent loss is kept within ± 1.5 dB in the entire C-band (1530-1570 nm). At 1550 nm, we obtained the extinction ratio of more than 25 dB and 18 dB for the case (a) and the case (b), respectively. The fiber-to-fiber loss was between 34 dB (I4⬄O5 of (b)) and 38.5 dB (I5⬄O8 of (a)). Out of this large loss, approximately 10 dB (5 dB/facet) is attributed to the fiber coupling.
Finally, dynamic switching experiment was also performed. Figure 6 shows the observed waveforms at Output 4 when the connection is dynamically switched from ON state (I5⬄O4) to OFF state (I5→O8/I1←O4). The rise and fall times (10-90%) are 4.2 and 3.8 ns, respectively, which include the response time of the driver circuit.
5. 40-Gbps (10-Gbps × 4Ch) WDM signal transmission
Owing to the wavelength-insensitive property of the switch, it should operate transparent to the modulation format of the signals.
The experimental setup for testing the WDM data transmission is shown in Fig. 7 . At the transmitter, 40-Gbps (10-Gbps × 4Ch: 1547.72, 1549.32, 1550.92, and 1552.5 nm) WDM payload was generated by using a single LiNbO3 Mach-Zehnder modulator (LN) driven with a 10-Gbps non-return-to-zero (NRZ) signal (PRBS 31). Four different lengths of fiber delay lines (FDL) were employed to decorrelate the data patterns among channels.
Figure 8 shows the measured BER of the WDM signal transmitted from Input 4 to Output 5. Thanks to the wide optical bandwidth of the switch, we obtain clear eye openings and power penalty of less than 2 dB at BER = 10−9 for all WDM channels.
Although the successful switching performance has been achieved, several issues have been raised on this particular device.
We need to note that in this particular device, due to the unstable dry-etching condition, has been spotted for serious sidewall roughness at the waveguides. From a separate Fabry-Perot measurement, the propagation loss at the straight waveguide section is estimated to be as large as 18 dB/cm, which would account for at least 16.5 dB of the total propagation loss in the 8 × 8 switch. In an optimized dry-etching condition, waveguide propagation loss of less than 1 dB/cm is achievable . Moreover, a fiber-to-chip coupling loss as low as 1 dB has recently been reported for spot size converting optical fibers and InP photonic integrated circuits . These facts imply that the total insertion loss of the switch could be improved by at least 24.4 dB with an optimized fabrication process and an enhanced experimental setup.
We have employed comparatively deep-etched waveguides to reduce the bending radius of the curvature, which is responsible for a footprint of entire chip size. From this on, the high-intensity plasma was directly irradiated to the Q1.37 u-InGaAs layer of the phase shifter region when the IRE dry etching process was done. Contrary to our expectation, the comparatively large range of driving voltage was required to operate phase shifters. This low efficiency of phase shifter was estimated by above process, which may cause crystallographic damage in the regions close to the surface. However, if we apply shallow etched waveguides to prevent the phase shifter region from the damages mentioned above, the DC power consumption of the switch can be kept less than 0.34pJ/bit (<1.4mW/PS for 2π-phase modulation ) for 100-Gbps transmission with fully non-blocking 8 × 8 interconnection.
Due to the large number of electrode, we could not evaluate all the ports of InP switch caused by limitation of wire-bonding. Such a physical problem disturbs the implementation of the larger scale matrix switches. There are epic flip-chip bonding technics that can bond more than 4000 contacts with almost 100% yield without problem . We believe that we can use these well-established technologies to make a breakthrough in scale limitation of the switches. One top of that, by this technology, our switch can be bonded directly to the CMOS driver circuit.
A monolithic InP strictly non-blocking 8 × 8 optical switch matrix based on optical phased array has experimentally been demonstrated for the first time. Sufficient static switching was performed with more than 18.5 dB extinction ratio for the worst case and wavelength-dependent loss of ± 1.5-dB inside the C-band (1530-1570 nm). Dynamic interconnection between the selected ports is achieved with less than 4.2-ns reconfiguration time. Error-free forwarding of 40-Gbps (10-Gbps × 4Ch) WDM signal is demonstrated successfully with <2-dB power penalty. In addition, this phased-array switch architecture scheme is very excels in scaling the port count owing to the no waveguide crossing. In the future, the application of the flip-flop chip bonding technology and the silicon photonics technology  will offer further advantages in scaling the port count to 100 × 100 and beyond hopefully.
This work was funded by Grant-in Aid for Scientific Research (S) #20226008, Japan Society for the Promotion of Science.
References and links
1. Google - Data centers, http://www.google.com/about/datacenters.
2. Microsoft – Server & Cloud, http://www.microsoft.com/en-us/server-cloud/default.aspx.
3. C. Lam, H. Liu, B. Koley, X. Zhao, V. Kamalov, and V. Gill, “Fiber optic communication technologies: what’s needed for datacenter network operations,” IEEE Commun. Mag. 48(7), 32–39 (2010). [CrossRef]
4. N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: a hybrid electrical/optical switch architecture for modular data centers,” in SIGCOMM '10 Proceedings of the ACM SIGCOMM 2010 Conference on SIGCOMM (ACM, 2010), pp. 339–350.
5. G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: part-time optics in data centers,” in SIGCOMM '10 Proceedings of the ACM SIGCOMM 2010 conference on SIGCOMM (ACM, 2010), pp. 327–338.
6. X. Ye, P. Mejia, Y. Yin, R. Proietti, S. J. B. Yoo, and V. Akella, “DOS—a scalable optical switch for datacenters,” in ANCS '10 Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ACS, 2010), article 24.
7. A. Vahdat, H. Liu, X. Zhao, and C. R. Johnson, “The emerging optical data center,” in Proceedings of Optical Fiber Communication Conference (OFC, 2011), paper OTuH2.
8. N. Farrington, Y. Fainman, H. Liu, G. Papen, and A. Vahdat, “Hardware requirements for optical circuit switched data center networks,” in Proceedings of Optical Fiber Communication Conference (OFC, 2011), Paper OTuH3.
9. A. Wonfor, H. Wang, R. V. Penty, and I. H. White, “Large port count high-speed optical switch fabric for use within datacenters,” J. Opt. Commun. Netw. 3(8), A32–A39 (2011). [CrossRef]
10. S. C. Nicholes, M. L. Mašanović, B. Jevremović, E. Lively, L. A. Coldren, and D. J. Blumenthal, “An 8×8 InP monolithic tunable optical router (MOTOR) packet forwarding chip,” J. Lightwave Technol. 28(4), 641–650 (2010). [CrossRef]
11. H. Liu, C. F. Lam, and C. R. Johnson, “Scaling optical interconnects in datacenter networks opportunities and challenges for WDM,” in 18th IEEE Symposium on High Performance Interconnects (IEEE, 2010), pp. 113–116.
12. S. Di Lucente, N. Calabretta, J. A. C. Resing, and H. J. S. Dorren, “Scaling low- latency optical packet switches to a thousand ports,” J. Opt. Commun. Netw. 4(9), A17–A28 (2012). [CrossRef]
13. C. R. Doerr and C. Dragone, “Proposed optical cross connect using a planar arrangement of beam steerers,” IEEE Photon. Technol. Lett. 11(2), 197–199 (1999). [CrossRef]
14. I. M. Soganci, T. Tanemura, K. A. Williams, N. Calabretta, T. de Vries, E. Smalbrugge, M. K. Smit, H. J. S. Dorren, and Y. Nakano, “Monolithically integrated InP 1×16 optical switch with wavelength-insensitive operation,” IEEE Photon. Technol. Lett. 22(3), 143–145 (2010). [CrossRef]
15. I. M. Soganci, T. Tanemura, and Y. Nakano, “Integrated phased-array switches for large-scale photonic routing on chip,” Laser Photon. Rev. 6(4), 549–563 (2012). [CrossRef]
16. L. H. Spiekman, Y. S. Oei, E. G. Metaal, F. H. Green, I. Moerman, and M. K. Smit, “Extremely small multimode interference couplers and ultrashort bends on InP by deep etching,” IEEE Photon. Technol. Lett. 6(8), 1008–1010 (1994). [CrossRef]
17. Chiral photonics – sport size converting interconnect, http://www.chiralphotonics.com/Web/coupler.html.
18. H. D. Thacker, I. Shubin, Y. Luo, J. Costa, J. Lexau, X. Zheng, G. Li, J. Yao, J. Li, D. Patil, F. Liu, R. Ho, D. Feng, M. Asghari, T. Pinguet, K. Raj, J. G. Mitchell, A. V. Krishnamoorthy, and J. E. Cunningham, “Hybrid integration of silicon nanophotonics with 40nm-CMOS VLSI drivers and receivers,” in proceeding of IEEE 61st Electronic Components and Technology Conference (ECTC, 2011), pp. 829–835.