Abstract

One of the most serious issues in information industries is the bandwidth bottleneck in inter-chip interconnects. We propose a photonics-electronics convergence system to solve this issue. We fabricated a high density optical interposer to demonstrate the feasibility of the system by using silicon photonics integrated with an arrayed laser diode, an optical splitter, silicon optical modulators, germanium photodetectors, and silicon optical waveguides on a single silicon substrate. Error-free data transmission at 12.5 Gbps and a transmission density of 6.6 Tbps/cm2 were achieved with the optical interposer. We believe this technology will solve the bandwidth bottleneck problem in the future.

©2012 Optical Society of America

1. Introduction

The CPU-CPU and CPU-memory inter-chip bandwidths in personal computers and servers are currently doubling every two years, and have been estimated to reach tera-scale by the mid 2010s [1]. Although the wiring pitches in logic circuits are expected to shrink exponentially on the basis of Moore’s law, LSI I/O pad pitches, such as flip-chip pad pitches, are presently expected to remain large scale [2]. Consequently, the scaling gap between intra- and inter-chips is going to widen annually. This is why the line speed for inter-chip interconnects in the future will need to be much higher than that for intra-chip ones. The required line speed is estimated to exceed 40 Gbps by the late 2010s, and currently there are no known solutions that are able to be manufactured with electrical interconnects [2].

Optical interconnects with silicon photonics have been expected to be used as candidates for solving the bandwidth bottleneck problem with LSI chips and they have been researched by many organizations [1, 36] because of the intrinsic properties of optical signals, such as wide bandwidth, low latency, low power consumption, and low mutual interference, and the industrial advantages of silicon for use as resources in the electronics industry. However, there have been few reports on inter-chip interconnects achieved by using silicon photonics that have been fully integrated with light sources, optical modulators, and photodetectors (PDs) on a single silicon substrate.

We proposed a photonics-electronics convergence system to solve the bandwidth bottleneck problem in inter-chip interconnects in our previous paper [7]. We also fabricated a high density optical interposer to demonstrate the feasibility of the system by using silicon photonics integrated with a 13 channel arrayed laser diode (LD), silicon optical modulators, germanium PDs, and silicon optical waveguides on a single silicon substrate for the first time. We achieved error-free data transmission at 5 Gbps and transmission density of 3.5 Tbps/cm2 by using this system. We believe that was an important milestone to overcome the bottlenecks in inter-chip interconnects.

In this paper, we present optical interconnects that had higher transmission density than our previous ones, which were accomplished by integrating a 1 × 4 optical splitter and improved optical components on a single silicon substrate.

2. Photonics-electronics convergence system for inter-chip interconnects

The conceptual model of the photonics-electronics convergence system for inter-chip interconnects is outlined in Fig. 1 . The upper-left LSI chip on the silicon optical interposer has been removed to enable the substrate surface area that it covered to be seen. Arrayed LDs, optical splitters, optical modulators and PDs are integrated on a silicon substrate and are optically linked to each other via silicon optical waveguides. Together, they form an optical interposer. LSI bare chips are mounted on the interposer and are electrically connected to the optical modulators and PDs by flip-chip bonding. This system enables us to replace the function of conventional electronic wires on a printed circuit board (PCB) with the optical interconnects on a silicon substrate, which is one hundredth the size of a PCB. This silicon optical interposer has wide bandwidth capabilities due to the properties of its optical signals. Since the silicon substrates can be fabricated using a CMOS compatible process, they have quite high density and are low in cost. Furthermore, because this system is optically closed without any optical inputs or outputs, users do not have to worry about any optical issues (such as optical coupling, optical reflection, or polarization dependence).

 figure: Fig. 1

Fig. 1 Conceptual model of photonics-electronics convergence system for inter-chip interconnects.

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3. Improvements to design and fabrication process of optical components

As stated in the introduction, we previously reported error-free data transmission at 5 Gbps and transmission density of 3.5 Tbps/cm2 by using a high density silicon optical interposer. We made some improvements in terms of the design and fabrication process to the optical components of the silicon optical interposer to achieve higher transmission density.

3.1 Improvements to fabrication process

The fabrication flow for the optical interposers was basically the same as that in our previous paper [7]. However, we mainly fabricated the optical interposers by using a foundry service in the previous work. We fabricated them in this research by using CMOS facilities in the Super-Clean-Room at AIST Tsukuba West, as well as some process facilities specified for silicon photonics in the same clean room. The many specifications in manufacturing design were newly established through careful evaluations of the processes used in these facilities for photonics-specified structure design, such as the overlays for the upper layer to the silicon core pattern and anisotropic etching of the thick cladding layer. The cooperation between researchers who designed devices and integrated processes strongly contributed to improved device performance and enlarged process margins.

3.2 Improvements to optical waveguides

We used silicon optical waveguides with rib-type cross-section cores in the previous work [7], which had relatively lower propagation loss than those with rectangular cores. However, the rib-type waveguides also posed difficulties with the fabrication process in that we had to stop etching the silicon layer to leave a precisely thin silicon slab. We think this issue is critical in terms of yields in mass production, especially for yields of optical modulators as will be explained later. Therefore, we decided to switch our silicon optical waveguides from rib-type to rectangular cores, and we developed fine lithography and etching processes in our clean room for rectangular core waveguides [8]. As a result, we attained propagation loss as low as 0.4 dB/mm with a rectangular core that was 480-nm wide and 220-nm thick at a wavelength of 1530 nm.

3.3 Improvements to optical modulators

The optical modulator was a Mach-Zehnder interferometer composed of phase shifters and multimode interference (MMI) couplers. The phase shifters could change their refractive indices by using the carrier plasma effect in lateral P-I-N diode structures.

We used a slab in the rib-type waveguides for carrier injection or extraction path in the phase shifters in our previous work [7]. The gap between P and N-doping areas should be wider than the width of the optical mode profile to prevent the optical absorption loss due to the highly doped carriers. The optical mode profile in the rib-type waveguides extended to the slab area, and the thicker slab caused the wider mode profile and P-N gap. Then, the wider P-N gap caused higher resistivity, lower modulation efficiency, and lower modulation speed. Because optical modulator characteristics such as optical loss, modulation efficiency, and speed were sensitive to the slab thickness in this way, we had to stop etching the silicon layer to leave a precisely thin silicon slab.

Figure 2(a) is a schematic of the structure of our new optical modulator [9], and Fig. 2(b) shows microscope and SEM images of the fabricated modulator. As was previously stated, we switched our silicon optical waveguides from rib-type to rectangular cores to avoid process difficulties in this work. We also simultaneously introduced a side-wall grating for the carrier injection or extraction path in the phase shifters instead of the slab in the rib waveguides, as shown in the inset of Fig. 2. Because the waveguides had a uniform thickness of silicon over the entire modulator, the etching process was much easier than that for rib-type waveguides. Moreover, this structure enabled stronger lateral optical mode confinement, a narrower optical mode profile, a narrower P-N gap, lower resistivity, higher efficiency, and higher speed than the previous modulator. The pitch of the side-wall grating was designed so that the stop-band wavelength was much shorter than the operation wavelength. The interaction length of the phase shifter was 250 μm.

 figure: Fig. 2

Fig. 2 Structure and images of optical modulator.

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The measured DC response of the optical modulator is plotted in Fig. 3 . The π-phase shift voltage (Vπ) was 0.13 V and the modulation efficiency (Vπ*L) was 0.003 Vcm, which was four times as high efficiency as that of our previous modulator with rib-type waveguide. The extinction ratio (ER) was 14.3 dB.

 figure: Fig. 3

Fig. 3 DC response of optical modulator.

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3.4 Improvements to photodetectors

There are generally two types of germanium PDs that we can monolithically integrate on a silicon substrate. The first are PIN-PDs and the second are metal-semiconductor-metal (MSM) PDs. MSM-PDs require fewer fabrication steps but finer patterning and alignment than PIN-PDs. We made vertical PIN-PDs in our previous work [7], which allowed us to carry out relatively rough patterning and alignment. We fabricated MSM-PDs with fewer fabrication steps in this work due to the more precise fabrication process in our own clean room. Fig. 4(a) is a schematic of the structure of our new germanium MSM-PD [10], and Fig. 4(b) shows microscope and SEM images of the one that we fabricated.

 figure: Fig. 4

Fig. 4 Structure and images of MSM-PD.

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The measured frequency responses of PDs with 4- to 10-V biases are plotted in Fig. 5 . The 3-dB cutoff frequencies were 6 GHz with a 4-V bias voltage and 9 GHz with a 10-V bias voltage. The fabrication process in our own clean room also contributed to reducing the contact resistance of the electrodes, and consequently to improving the frequency response of the PDs. As a result, the cutoff frequency in this work was twice that in the previous research. The dark current of the PDs was about 1 μA. The photo to dark current ratio was higher than 30 dB.

 figure: Fig. 5

Fig. 5 Frequency responses of PDs.

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3. 5 Improvements to spot-size converters

We used a taper waveguide for the spot-size converter (SSC) between the LD and silicon waveguide in our previous research, and the coupling loss was about 11 dB [7]. We introduced a novel SSC in this work, called a trident [11]. Figure 6 is a schematic of the structure of the trident SSC and an SEM image of it. It consists of three narrow silicon waveguides and enables less mode mismatch between the LD and silicon waveguide and higher tolerance against alignment errors. As a result, we achieved 2.3-dB coupling loss by using the trident SSC and a passive alignment technique [12].

 figure: Fig. 6

Fig. 6 Schematic structure of trident SSC and SEM image.

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4. Data transmission experiments with integrated silicon optical interposers

We fabricated silicon optical interposers integrated with the improved optical components. There is a photograph of a fabricated silicon optical interposer in Fig. 7 . The substrate was 5 × 5 mm. A trident SSC array, a 1 × 4 optical splitter, an optical modulator array with side-wall gratings, and an MSM-PD array were monolithically integrated on a single silicon substrate, an arrayed LD chip was mounted on the substrate with a passive alignment technique, and these optical components were optically linked to each other via a silicon optical waveguide array. The LD chip was a 13-channel arrayed InGaAsP LD with a 30-μm channel pitch. Each channel was a Fabry-Perot type with a spot-size converter. The LD chip had a single pair of electrodes for all 13 channels that simultaneously emitted. The wavelength was 1530 nm.

 figure: Fig. 7

Fig. 7 Photograph of fabricated silicon optical interposer.

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The setup for the data transmission experiments was similar to that in our previous paper [7]. The experiments were carried out as follows. All 13 channels of the arrayed LD were simultaneously driven by a single DC current. The CW light from the LD was divided into four by the 1 × 4 optical splitter and each of them launched into the optical modulator. RF input signals were pre-emphasized by a differentiator and input to the modulator. The voltage amplitude after pre-emphasis was 3.4 V peak to peak. The modulated optical signals propagated along the optical waveguides, and were then input to the PD array and converted into electrical signals.

The measured eye diagram of PD output at 12.5-Gbps NRZ with a 27-1 pseudo-random binary sequence (PRBS) is shown in Fig. 8(a) . The clear eye opening suggests that the optical links were capable of data transmission at 12.5 Gbps. The measured bit error rate (BER) for the 12.5-Gbps PRBS is plotted in Fig. 8(b). We confirmed that BER was smaller than 10−12 when the PD input power was larger than −5 dBm. Error-free data transmission at 12.5 Gbps was achieved. Because this system was optically closed, we did not need to align fibers, control polarization, or control temperature throughout the experiments.

 figure: Fig. 8

Fig. 8 Results from data transmission experiments.

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The optical power budget per channel is summarized in Table 1 . The overall optical loss was 18 dB, including inherent 6-dB branching loss and 3-dB modulation loss. We could gain an optical power margin that enabled us to introduce the 1 × 4 optical splitter due to the novel trident SSC with quite low coupling loss. These results suggest that integrating a 13-channel arrayed LD, 13 1 × 4 optical splitters, 52 modulators and PDs enables the optical interposer to achieve a bandwidth of 650 Gbps on a single silicon substrate.

Tables Icon

Table 1. Optical power budget

The footprints of optical components per channel are listed in Table 2 . Thanks to the 1 × 4 optical splitter, the footprint of laser diode per channel was also split into four. The total footprint was 0.19 mm2 per channel, meaning we could achieve a transmission density of 6.6 Tbps/cm2 with a channel line rate of 12.5 Gbps. About two-thirds of the total footprint was occupied by electrode pads in these experiments. Therefore, we expect to improve the transmission density further with smaller pads in the near future.

Tables Icon

Table 2. Footprints of optical components per channel

6. Conclusion

We proposed a photonics-electronics convergence system with a silicon optical interposer by using silicon photonics in order to solve the bandwidth bottleneck problem that inter-chip interconnects have. We investigated the improvements to design and fabrication process of optical components for the silicon optical interposer: silicon optical waveguides, silicon optical modulators, germanium photodetectors, arrayed laser diodes, and spot-size converters. We then demonstrated the feasibility of the system by fabricating a high density optical interposer integrated with these optical components on a single silicon substrate. We achieved error-free data transmission at 12.5 Gbps and transmission density of 6.6 Tbps/cm2 with the optical interposer. We believe that this technology will solve the bandwidth bottleneck problem in the future.

Acknowledgments

This research is supported by the Japan Society for the Promotion of Science (JSPS) through its “Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).” Part of the fabrication was conducted at the Nano-Processing Facility, supported by IBEC Innovation Platform, AIST.

References and links

1. I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010). [CrossRef]  

2. International Technology Roadmap for Semiconductors 2009 Edition, Assembly and Packaging, Table AP2 and AP3. http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_Assembly.pdf

3. L. Chen, K. Preston, S. Manipatruni, and M. Lipson, “Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors,” Opt. Express 17(17), 15248–15256 (2009). [CrossRef]   [PubMed]  

4. K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

5. G. Kim, J. W. Park, I. G. Kim, S. Kim, S. Kim, J. M. Lee, G. S. Park, J. Joo, K. S. Jang, J. H. Oh, S. A. Kim, J. H. Kim, J. Y. Lee, J. M. Park, D. W. Kim, D. K. Jeong, M. S. Hwang, J. K. Kim, K. S. Park, H. K. Chi, H. C. Kim, D. W. Kim, and M. H. Cho, “Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s,” Opt. Express 19(27), 26936–26947 (2011). [CrossRef]   [PubMed]  

6. X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012). [CrossRef]  

7. Y. Urino, T. Shimizu, M. Okano, N. Hatori, M. Ishizaka, T. Yamamoto, T. Baba, T. Akagawa, S. Akiyama, T. Usuki, D. Okamoto, M. Miura, M. Noguchi, J. Fujikata, D. Shimura, H. Okayama, T. Tsuchizawa, T. Watanabe, K. Yamada, S. Itabashi, E. Saito, T. Nakamura, and Y. Arakawa, “First demonstration of high density optical interconnects integrated with lasers, optical modulators, and photodetectors on single silicon substrate,” Opt. Express 19(26), B159–B165 (2011). [CrossRef]   [PubMed]  

8. N. Hirayama, H. Takahashi, Y. Noguchi, M. Yamagishi, and T. Horikawa, “Low-loss Si waveguides with variable-shaped-beam EB lithography for large-scaled photonic circuits,” The extended abstract of 2012 International Conference on Solid State Devices and Materials (SSDM), A-2–2 (2012).

9. S. Akiyama, T. Baba, M. Imai, T. Akagawa, M. Takahashi, N. Hirayama, H. Takahashi, Y. Noguchi, H. Okayama, T. Horikawa, and T. Usuki, “12.5-Gb/s operation with 0.29-V•cm V(π)L using silicon Mach-Zehnder modulator based-on forward-biased pin diode,” Opt. Express 20(3), 2911–2923 (2012). [CrossRef]   [PubMed]  

10. J. Fujikata, M. Noguchi, M. Miura, D. Okamoto, T. Horikawa, and Y. Arakawa, “Si waveguide-integrated MSM Ge photodiode,” Proceeding of International Conference on Solid State Devices and Materials (SSDM), CI-6–3 (2011).

11. N. Hatori, T. Shimizu, M. Okano, M. Ishizaka, T. Yamamoto, Y. Urino, M. Mori, T. Nakamura, and Y. Arakawa, “A novel spot size convertor for hybrid integrated light sources on photonics-electronics convergence system,” Proceeding of 9th International Conference on Group IV Photonics (GFP), ThB2 (2012).

12. N. Fujioka, T. Chu, and M. Ishizaka, “Compact and low power consumption hybrid integrated wavelength tunable laser module using silicon waveguide resonators,” J. Lightwave Technol. 28, 3115–3120 (2010).

References

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  1. I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
    [Crossref]
  2. International Technology Roadmap for Semiconductors 2009 Edition, Assembly and Packaging, Table AP2 and AP3. http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_Assembly.pdf
  3. L. Chen, K. Preston, S. Manipatruni, and M. Lipson, “Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors,” Opt. Express 17(17), 15248–15256 (2009).
    [Crossref] [PubMed]
  4. K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).
  5. G. Kim, J. W. Park, I. G. Kim, S. Kim, S. Kim, J. M. Lee, G. S. Park, J. Joo, K. S. Jang, J. H. Oh, S. A. Kim, J. H. Kim, J. Y. Lee, J. M. Park, D. W. Kim, D. K. Jeong, M. S. Hwang, J. K. Kim, K. S. Park, H. K. Chi, H. C. Kim, D. W. Kim, and M. H. Cho, “Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s,” Opt. Express 19(27), 26936–26947 (2011).
    [Crossref] [PubMed]
  6. X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
    [Crossref]
  7. Y. Urino, T. Shimizu, M. Okano, N. Hatori, M. Ishizaka, T. Yamamoto, T. Baba, T. Akagawa, S. Akiyama, T. Usuki, D. Okamoto, M. Miura, M. Noguchi, J. Fujikata, D. Shimura, H. Okayama, T. Tsuchizawa, T. Watanabe, K. Yamada, S. Itabashi, E. Saito, T. Nakamura, and Y. Arakawa, “First demonstration of high density optical interconnects integrated with lasers, optical modulators, and photodetectors on single silicon substrate,” Opt. Express 19(26), B159–B165 (2011).
    [Crossref] [PubMed]
  8. N. Hirayama, H. Takahashi, Y. Noguchi, M. Yamagishi, and T. Horikawa, “Low-loss Si waveguides with variable-shaped-beam EB lithography for large-scaled photonic circuits,” The extended abstract of 2012 International Conference on Solid State Devices and Materials (SSDM), A-2–2 (2012).
  9. S. Akiyama, T. Baba, M. Imai, T. Akagawa, M. Takahashi, N. Hirayama, H. Takahashi, Y. Noguchi, H. Okayama, T. Horikawa, and T. Usuki, “12.5-Gb/s operation with 0.29-V•cm V(π)L using silicon Mach-Zehnder modulator based-on forward-biased pin diode,” Opt. Express 20(3), 2911–2923 (2012).
    [Crossref] [PubMed]
  10. J. Fujikata, M. Noguchi, M. Miura, D. Okamoto, T. Horikawa, and Y. Arakawa, “Si waveguide-integrated MSM Ge photodiode,” Proceeding of International Conference on Solid State Devices and Materials (SSDM), CI-6–3 (2011).
  11. N. Hatori, T. Shimizu, M. Okano, M. Ishizaka, T. Yamamoto, Y. Urino, M. Mori, T. Nakamura, and Y. Arakawa, “A novel spot size convertor for hybrid integrated light sources on photonics-electronics convergence system,” Proceeding of 9th International Conference on Group IV Photonics (GFP), ThB2 (2012).
  12. N. Fujioka, T. Chu, and M. Ishizaka, “Compact and low power consumption hybrid integrated wavelength tunable laser module using silicon waveguide resonators,” J. Lightwave Technol. 28, 3115–3120 (2010).

2012 (2)

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

S. Akiyama, T. Baba, M. Imai, T. Akagawa, M. Takahashi, N. Hirayama, H. Takahashi, Y. Noguchi, H. Okayama, T. Horikawa, and T. Usuki, “12.5-Gb/s operation with 0.29-V•cm V(π)L using silicon Mach-Zehnder modulator based-on forward-biased pin diode,” Opt. Express 20(3), 2911–2923 (2012).
[Crossref] [PubMed]

2011 (2)

2010 (3)

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

N. Fujioka, T. Chu, and M. Ishizaka, “Compact and low power consumption hybrid integrated wavelength tunable laser module using silicon waveguide resonators,” J. Lightwave Technol. 28, 3115–3120 (2010).

2009 (1)

Akagawa, T.

Akiyama, S.

Arakawa, Y.

Asghari, M.

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Baba, T.

Block, B. A.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

Chang, P. L. D.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

Chen, L.

Chi, H. K.

Cho, M. H.

Chu, T.

Cunningham, J. E.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Fujikata, J.

Fujioka, N.

Hatori, N.

Hirayama, N.

Ho, R.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Horikawa, T.

Hwang, M. S.

Imai, M.

Ishizaka, M.

Itabashi, S.

Jang, K. S.

Jeong, D. K.

Joo, J.

Kem, A. M.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

Kim, D. W.

Kim, G.

Kim, H. C.

Kim, I. G.

Kim, J. H.

Kim, J. K.

Kim, S.

Kim, S. A.

Koka, P.

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Krishnamoorthy, A. V.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Lee, J. M.

Lee, J. Y.

Lexau, J.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Li, G.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Liao, J. T. S.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

Lipson, M.

Liu, F.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

Luo, Y.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Manipatruni, S.

McCracken, M.

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Mitchell, J.

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Miura, M.

Mohammed, E. M.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

Nakamura, T.

Noguchi, M.

Noguchi, Y.

Oh, J. H.

Okamoto, D.

Okano, M.

Okayama, H.

Palermo, S.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

Park, G. S.

Park, J. M.

Park, J. W.

Park, K. S.

Pinguet, T.

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Preston, K.

Raj, K.

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Reshotko, M. R.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

Saito, E.

Schwetman, H.

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Shimizu, T.

Shimura, D.

Shubin, I.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Takahashi, H.

Takahashi, M.

Thacker, H.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Tsuchizawa, T.

Urino, Y.

Usuki, T.

Watanabe, T.

Yamada, K.

Yamamoto, T.

Yao, J.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Young, I. A.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

Zheng, X.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

IEEE Commun. Mag. (1)

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010).
[Crossref]

IEEE Photon. Technol. Lett. (1)

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012).
[Crossref]

J. Lightwave Technol. (1)

Opt. Express (4)

Proc. SPIE (1)

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

Other (4)

International Technology Roadmap for Semiconductors 2009 Edition, Assembly and Packaging, Table AP2 and AP3. http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_Assembly.pdf

J. Fujikata, M. Noguchi, M. Miura, D. Okamoto, T. Horikawa, and Y. Arakawa, “Si waveguide-integrated MSM Ge photodiode,” Proceeding of International Conference on Solid State Devices and Materials (SSDM), CI-6–3 (2011).

N. Hatori, T. Shimizu, M. Okano, M. Ishizaka, T. Yamamoto, Y. Urino, M. Mori, T. Nakamura, and Y. Arakawa, “A novel spot size convertor for hybrid integrated light sources on photonics-electronics convergence system,” Proceeding of 9th International Conference on Group IV Photonics (GFP), ThB2 (2012).

N. Hirayama, H. Takahashi, Y. Noguchi, M. Yamagishi, and T. Horikawa, “Low-loss Si waveguides with variable-shaped-beam EB lithography for large-scaled photonic circuits,” The extended abstract of 2012 International Conference on Solid State Devices and Materials (SSDM), A-2–2 (2012).

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Figures (8)

Fig. 1
Fig. 1 Conceptual model of photonics-electronics convergence system for inter-chip interconnects.
Fig. 2
Fig. 2 Structure and images of optical modulator.
Fig. 3
Fig. 3 DC response of optical modulator.
Fig. 4
Fig. 4 Structure and images of MSM-PD.
Fig. 5
Fig. 5 Frequency responses of PDs.
Fig. 6
Fig. 6 Schematic structure of trident SSC and SEM image.
Fig. 7
Fig. 7 Photograph of fabricated silicon optical interposer.
Fig. 8
Fig. 8 Results from data transmission experiments.

Tables (2)

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Table 1 Optical power budget

Tables Icon

Table 2 Footprints of optical components per channel

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