We present new generation and detection methods for high symbol-rate 64-ary quadrature amplitude modulation (64QAM). The 64QAM signal is created by tandem in-phase/quadrature (I/Q) modulators driven by electrical binary signals. The first I/Q modulator, which has four drive arms (i.e. a dual-drive I/Q modulator), yields 16QAM with an offset at the 1st quadrant of the complex plane. Subsequently, the second modulator switches this 16QAM signal over four quadrants via the typical quadrature phase-shift-keying (QPSK) modulation scheme, hence the desired 64QAM is generated. To mitigate the impacts of transmitter imperfections, we also propose a phase-folded decision-directed (PF-DD) linear equalizer at the receiver. Using these new techniques, we experimentally demonstrate the 120- and 240-Gb/s polarization-division-multiplexed (PDM) return-to-zero (RZ) 64QAM systems. The required optical signal-to-noise ratio (OSNR) for a bit-error rate (BER) of 2.4x10−2 is measured at 20.2 or 23 dB, respectively, which is ~3.5 dB off the theoretical limit.
©2012 Optical Society of America
The 64-ary quadrature amplitude modulation (64QAM) format, together with a polarization-division-multiplexing (PDM) technique, is a promising candidate for a spectrally efficient dense wavelength-division-multiplexing (DWDM) transmission system. Accordingly, there have been numerous efforts to effectively generate high-speed 64QAM signals (> 10 Gbaud) [1–6]. Most high-speed 64QAM generation methods are based on the use of a single in-phase/quadrature (I/Q) modulator with electrical 8-level drive signals. In particular, various techniques for synthesizing the electrical 8-level signal have been proposed, such as a high-speed digital-to-analog converter (DAC) [1, 2], opto-electronic scheme , and direct additions of electrical binary signals with passive components . However, these methods have at least one of the following drawbacks and may not be so promising for practical applications: i) difficulty in increasing the symbol rate [1, 2] because the high-speed DAC with high resolution remains challenging, ii) complex to implement , and iii) requiring linear drive amplifiers for electrical 8-level signals [1–4]. On the other hand, for 64QAM generation without these sophisticated high-speed electronics, a new synthesizing approach using optical-time-division (OTD) multiplexing and electrical-time-division (ETD) demultiplexing has been demonstrated . However, this approach requires a short-pulsed light source for OTD multiplexing and, meaning it is unsuitable for DWDM systems. Furthermore, a new 64QAM transmitter using electrical binary drive signals has been proposed and demonstrated . This transmitter technology is based on the hybrid integration of a silica planar lightwave circuit and LiNbO3 phase modulators. Although this technique has the potential to increase the symbol rate of the optical 64QAM signal due to the use of binary data only, the back-to-back performance of the 20-Gbaud PDM-64QAM signal generated by this transmitter remains poor where the bit-error rate (BER) floor is observed at ~1x10−2.
In this paper, we present a new 64QAM transmitter using an optical binary synthesizing approach. The proposed optical transmitter consists of tandem I/Q modulators with electrical binary drive signals. Thanks to the dual-drive (DD) structure of the first I/Q modulator (i.e. its sub Mach-Zehnder modulators (MZMs) have dual traveling-wave electrodes), we produce 16QAM placed in the 1st quadrant of the complex plane. This 16QAM output is then duplicated over four quadrants through the quadrature phase shift keying (QPSK) modulation scheme by the second typical I/Q modulator, thus resulting in the desired 64QAM. In addition, to effectively compensate for the signal distortion induced by transmitter imperfections, we propose a phase-folded decision-directed (PF-DD) linear equalizer at the receiver. Using the proposed transmitter and receiver, we experimentally demonstrate the 10- and 20-Gbaud PDM-64QAM systems with return-to-zero (RZ) pulse shaping and evaluate their BER performances with respect to the optical signal-to-noise ratio (OSNR). The back-to-back OSNR sensitivities of 120- and 240-Gb/s PDM-RZ-64QAM signals are 20.2 and 23 dB at 2.4x10−2 BER, respectively, which are ~3.5 dB off the theoretical limits.
2. Generation of 64QAM
The configuration of the proposed 64QAM transmitter is illustrated in Fig. 1 . This transmitter comprises a DD I/Q modulator and a typical single-drive I/Q modulator in tandem with electrical binary drive signals (Data1~Data6) where v1(t)~v6(t) and A1~A6 denote binary data taken values between 0.5 and −0.5 and its corresponding amplitude, respectively. It is noted that we can independently utilize four phase modulators integrated in the DD I/Q modulator. As shown in Fig. 1, the DD I/Q modulator is used to produce an offset square 16QAM by applying four independent binary data, Data1~Data4, to each drive arm. Subsequently, the modulated 16QAM is switched to other quadrants by the QPSK modulation scheme of the second I/Q modulator driven with two other binary inputs, Data5 and Data6, hence the desired 64QAM is generated at the transmitter output. The operating principle and conditions of the DD I/Q modulator are visualized in Fig. 2 . For convenience, two DD-MZMs embedded in the DD I/Q modulator are designated by MZMA and MZMB. When the transfer functions of MZMA and MZMB are HA(t) and HB(t), assuming even splitting/combining ratios of all MZMs, the output signal Eo(t) of the DD I/Q modulator is expressed as7]. From (1)~(3), we find that the amplitude and phase of the optical signal are arbitrarily modulated by adjusting the amplitudes Ax of the electrical drive signals. In other words, according to the driving voltages (A1~A4) of the input binary signals for MZMA and MZMB, the phase differences (2ϕA and 2ϕB) of the phase-modulated optical binary symbols in each arm of MZMA and MZMB are determined as and , as shown in Fig. 2. Consequently, MZMA and MZMB produce the offset 4QAM outputs by adding individual phase-modulated symbols in each arm with a quadrature phase (i.e. va = 0.5Vπ and vb = 0.5Vπ). In the main MZ interferometer of the DD I/Q modulator, these offset 4QAM signals are then linearly added (i.e. vc = 0), which results in an offset 16QAM placed in the 1st quadrant. For proper 16QAM modulation of the DD I/Q modulator, it requires two conditions regarding the relative size and position: i) and ii) . In other words, these conditions signify that i) the symbol distance of 4QAM from MZMB is twice as large as that of MZMA and ii) the vector sum (i.e. 16QAM) of two 4QAM signals from MZMA and MZMB is placed in the 1st quadrant of the complex plane. From these requirements, we can find the operation conditions for the DD I/Q modulator as follows: A1 = A2 ≈0.25Vπ and A3 = A4 ≈0.56Vπ. In addition, each symbol of the MZMA output is coupled to the MZMB output in the main MZ interferometer. The produced symbols at each arm and the process of synthesizing the final offset 16QAM can be found in the insets of Fig. 2. Consequently, we can obtain the desired 16QAM placed in the 1st quadrant of 64QAM at the output of the DD I/Q modulator.
To verify the operation of the proposed transmitter, we carried out a numerical simulation. Figure 3 shows the constellations of the modulated signals, including all transitions between symbols at the output of each modulator. From these results, we can confirm that the proposed transmitter can effectively generate the desired 64QAM signal with the electrical binary drive signals.
3. Detection of 64QAM
We introduce the signal processing procedure used in a digital coherent receiver, as shown in Fig. 4 . From the coherent receiver front-end, we obtain the sampled data of the complex signals on two perpendicular polarizations. The received samples are processed offline as follows. First the receiver imperfections, such as skew, power imbalance, error in orthogonality, etc., are simply corrected and the matched filter is applied. After resampling of twice the symbol rate, linear equalization and polarization demultiplexing are performed simultaneously using butterfly-structure finite impulse response (FIR) filters. For pre-equalization, a half-symbol-spaced equalizer adapted by a constant-modulus algorithm (CMA) is implemented and then switched to a radius-directed algorithm (RDA) . The carrier is recovered using a decision-directed phase-locked loop and a decision-directed linear equalizer without training sequences is then applied [9, 10]. The tap coefficient Cn of the decision-directed linear equalizer with an error signal εk = rk - sk (where sk and rk denote the equalized output and reference signal at the k-th symbol sequence) is updated as follows:Fig. 4(b) shows the distorted 64QAM constellation when . The spiral symmetry of the signal distortion is observed due to the QPSK modulation scheme of the transmitter. However, this signal distortion is not compensated by FIR filters and/or a decision-directed linear equalizer. To effectively compensate for this signal distortion, we propose a phase-folded decision-directed (PF-DD) linear equalizer. We first divide 64QAM into four parts and rotate 16 symbols in each quadrant through −0.5π, 0.5π, or π to reach the 1st quadrant. After phase folding, a decision-directed linear equalizer is executed with a new reference constellation of 16QAM placed in the 1st quadrant and then the rotated phases are unfolded back. Using the proposed PF-DD equalizer, we can effectively remove the unwanted distortion caused by transmitter imperfections. Furthermore, the PF-DD equalizer is expected to be useful for other generation methods using a tandem configuration [11–13]. The equalized data in two polarizations are then sent to the 64QAM demodulator and BER is calculated.
4. Experimental setup and results
Figure 5 shows the experimental setup to evaluate the performance of 240-Gb/s PDM-RZ-64QAM generated by the proposed transmitter. To create six 20-Gbaud drive signals, four independent binary data of a 5-Gb/s pseudo-random bit sequence (PRBS) with a pattern length of 215-1 from a pulse pattern generator (PPG) were electrically multiplexed and one of the two 20-Gb/s output signals of the 4:1 multiplexer (Mux) was split again. Three 20-Gb/s binary signals were reshaped by D-type flip flops (DFFs) and then six reshaped data were applied to each modulator with a different electrical delay. Thanks to the use of sufficiently long patterns and relative delays, the random data were successfully emulated. First, a free-running tunable laser (linewidth < 200 kHz) operating at 193.4 THz was fed into a conventional MZM driven by a 20-GHz clock for 50% RZ pulse shaping and it was then modulated with 120-Gb/s 64QAM using the proposed transmitter consisted of tandem I/Q modulators. RZ pulse shaping is beneficial to improve the tolerance to inter-symbol interference . The modulated RZ-64QAM signal was split into two paths and then orthogonally recombined with an optical delay of several hundreds of symbol periods for polarization multiplexing. The optical eye diagrams of 120- and 240-Gb/s PDM-RZ-64QAM are also shown in Fig. 5(a). On the other hand, for the reception of 64QAM, we implemented a self-homodyne coherent receiver (i.e. a local oscillator (LO) was the same as a transmitter laser) since we utilized a relatively-wide-linewidth laser. The coherent receiver was realized using a dual-polarization 90° optical hybrid and four balanced photodetectors (BPDs) followed by a 50-GS/s digital storage oscilloscope with 16-GHz bandwidth as an analog-to-digital converter (ADC). The sampled data were processed offline as described above. In offline signal processing, we utilized the 20-tap half-symbol-spaced FIR filters, 150-tap decision-directed linear equalizer, and 350-tap PF-DD linear equalizer. For BER measurements, ~4x105 symbols were calculated.
We first investigated the effectiveness of PF-DD linear equalization used in a coherent receiver. Figures 6(a) and 6(b) show the constellations before and after applying the PF-DD equalizer of 10- and 20-Gbaud RZ-64QAM signals for the single-polarization case, respectively. As shown in Fig. 6, even after decision-directed linear equalization, the equalized signals still contained signal distortion caused by transmitter imperfections, such as inaccuracy of bias position, noise accumulation due to the limited signal-to-noise ratio (SNR) of drive signals, etc. However, after applying the PF-DD linear equalizer, such signal distortion was effectively offset. In addition, based on the 64QAM constellations without PF-DD equalization, we can easily estimate that the BER performances of the 64QAM signals without PF-DD equalization may be very poor if we count errors based on a rectilinear decision grid. Figures 6(c) and 6(d) depict the measured BER performances of the 10- and 20-Gbaud RZ-64QAM signals. Even at 38-dB OSNR, the back-to-back BERs of the 10- and 20-Gbaud signals were measured at ~2x10−3 and ~4x10−3, respectively. However, with PF-DD equalization, the BER performances were significantly improved to ~1x10−4 and ~3x10−4. We also evaluated the back-to-back BER performances of 120- and 240-Gb/s PDM-RZ-64QAM signals while varying OSNR. In Fig. 7 , the solid lines represent the theoretical limits for the 10-Gbaud (blue) and 20-Gbaud (green) 64QAM signals  and the triangle and square symbols indicate the BER measurements of the 10- and 20-Gbaud signals, respectively. In the case of the 10-Gbaud RZ-64QAM signal, the OSNR sensitivity to achieve a BER of 2.4x10−2 (soft-decision forward error correction (FEC) threshold with 20% overhead ) was measured at 16.7 dB, differing by only ~3 dB from the theoretical value. In addition, the OSNR penalty induced by PDM adaptation was 0.5 dB (i.e. the OSNR difference between single-polarization and PDM was 3.5 dB). On the other hand, the OSNR sensitivities of 20-Gbaud RZ-64QAM with single polarization and PDM were 19.5 and 23 dB. Before noise loading (OSNR = ~40 dB), the BER floors of the 120- and 240-Gb/s PDM-RZ-64QAM signals were observed at 4.5x10−4 and 8x10−4, respectively. Figure 7 also shows the recovered constellations of 240-Gb/s PDM-RZ-64QAM at full OSNR.
We have proposed new generation and detection methods for high-speed 64QAM. The proposed transmitter effectively synthesizes the desired 64QAM using commercial I/Q modulators with electrical binary drive signals. In addition, a new PF-DD equalizer is introduced to mitigate the impacts of signal distortions induced by transmitter imperfections. We have experimentally verified the feasibility of these new proposals by evaluating the performances of the 120- and 240-Gb/s PDM-RZ-64QAM systems. The OSNR sensitivities of the 120- and 240-Gb/s PDM-RZ-64QAM signals (at the threshold BER of the soft-decision FEC = 2.4x10−2) are found to be 20.2 and 23 dB, respectively, which are only ~3.5 dB off the theoretical limits.
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