A silicon microring modulator utilizing an interleaved p-n junction phase shifter with a VπL of 0.76 V-cm and a minimum off-resonance insertion loss of less than 0.2 dB is demonstrated. The modulator operates at 25 Gbps at a drive voltage of 1.6 V and 2-3 dB excess optical insertion loss, conditions which correspond to a power consumption of 471 fJ/bit. Eye diagrams are characterized at up to 40 Gbps, and transmission is demonstrated across more than 10 km of single-mode fiber with minimal signal degradation.
©2012 Optical Society of America
Projected developments in data center and high performance computing systems place stringent requirements on the cost and power budget of short to mid-range optical communications technology . Silicon photonics shows great promise to soon become a leading platform for future low-cost and low-power datacom applications , leveraging the benefits of highly advanced silicon fabrication technology [3–5]. However, in order for silicon photonics to be relevant for new datacom standards such as 100 Gigabit Ethernet , InfiniBand , and Fibre Channel , it is necessary to develop a silicon photonic modulator operating at the necessary high bit rates up to 25 Gbps with CMOS-compatible drive voltages and low insertion loss.
High-speed operation at extended bit rates even above 40 Gbps has been previously reported in Mach-Zehnder modulators [9–13]. However, those devices required drive voltages of at least 4 V which cannot be supplied by conventional low-voltage CMOS circuits, and have insertion losses of 4 dB or greater. Mach-Zehnder devices aiming for lower bit rates have achieved lower drive voltages, such as 0.63 Vpp at 20 Gbps  and 0.5 Vpp at 26 Gbps , but still exhibit high insertion losses above 4 dB [14–18].
In general, limiting the modulator insertion loss plays an important role in meeting the stringent link budget requirements of datacom standards [6–8]. Higher doping levels in the silicon waveguide generally result in a lower VπL figure of merit, and accordingly lower driving voltages. However, this inevitably induces higher insertion losses, creating a fundamental tradeoff in the design of efficient modulators. For example, the design of Mach-Zehnder modulators [9–18] requires that all of the light must pass through the full length of doped waveguide, unavoidably resulting in high insertion loss. To decrease the insertion loss, therefore, either the active length or the doping level would need to be decreased. This would result in either an increase of the drive voltage requirements (and hence power consumption), or a decrease in the extinction ratio.
In contrast, silicon photonic modulators based on a microring resonator design [19–32] can have very low insertion loss, as most of the light at the off-resonant ‘one’ level will bypass the ring entirely, having minimal interaction with the lossy dopants. As a result, doping levels can be optimized for the highest modulation efficiency and largest capacitance per unit length without having a significant impact upon the modulator loss. Even with very high doping levels, the shorter active length and lower capacitance enabled by the microring’s resonant enhancement also allow microring modulators to achieve high bit rates [25, 30–32] without the need for traveling wave electrode structures [9–18]. This simplifies design and fabrication, potentially leading to lower operating power and to higher yield.
Here we demonstrate a 25 Gbps silicon microring modulator operating with 1.6 V drive voltage, an insertion loss of less that 0.2 dB, and a power consumption of 471 fJ/bit. In order to achieve these metrics, a novel phase shifter design is developed that combines the familiar idea of a vertical p-n junction  with the recent concept of p- and n-doped regions interdigitated along the length of the waveguide [22, 28, 32]. This phase shifter design allows a very low figure of merit VπL of only 0.76 V-cm to be achieved with a relatively low propagation loss of 36 dB/cm. Lower VπL figures of merit have been reported for MOS-capacitor designs [34, 35], but thus far these values have been achieved at the expense of higher propagation losses of 70 dB/cm  or lower bit rates of 12.5 Gbps or below [34, 35].
2. Phase shifter design
2.1 General considerations for design
The refractive index change in a silicon phase shifter is proportional, according to Soref’s equations , to the electrical charge moved in and out of the silicon waveguide. This refractive index change causes a change in the effective index of the optical mode, determined by the weighted overlap between the change in the charge distribution and the optical mode profile. The total amount of charge moved is
The power consumption of the modulator per bit of modulated data is approximately P = ¼CV2 for a non-return to zero (NRZ) signal . Therefore, to achieve low power consumption, both capacitance and voltage should be minimized. However, the power consumed is quadratic in the voltage, but only linear with respect to the capacitance. Moreover, high drive voltages can be extremely difficult to achieve in CMOS circuitry. As the voltage increases, the circuits become increasingly power-inefficient, and the long-term circuit reliability is often reduced. With these considerations, it is desirable to increase the capacitance rather than the voltage in order to increase the total phase shifter efficiency, as long as this increased capacitance retains a good overlap with the optical mode.
Setting an upper limit on the total capacitance, the modulation bandwidth is mostly limited by the RC time constant for a phase shifter that is short enough to be considered a lumped element for a given bit rate. As the phase shifter length increases, the parasitic capacitance and inductance increase as well, decreasing the overlap factor, and the propagation velocity mismatch between the electrical and optical signals can eventually become a major limiting factor. Therefore, a shorter phase shifter is preferred to minimize the impact of these effects.
All of these factors taken together imply that, in order to achieve an optimized silicon diode phase shifter for a lumped element modulator, it is very important to realize not only a large capacitance and high overlap factor, but also a large capacitance per unit length. Such an optimized phase shifter would be able to operate at low voltages and high bandwidth in lumped element devices with the required extinction ratio for contemporary applications.
2.2 Interleaved phase shifter design
In order to increase the effective capacitance per unit length of the phase shifter, the surface area of the reverse-biased p-n junction overlapping the optical mode as it propagates down the waveguide should be maximized. Following this approach, the phase shifter was designed as illustrated in Fig. 1 . Two cross-sections are shown in the left inset, illustrating two distinct segments that alternate along the waveguide length. The first segment, displayed in the upper cross-section, is predominantly a vertical p-n junction diode in which the depletion region under reverse bias extends mostly in the vertical direction. The second segment, shown in the lower cross-section, is predominantly a horizontal p-n junction. To provide a continuous electrical contact to all p-doped regions, all segments have one side of the waveguide doped p-type. The alternation of vertical and horizontal p-n junctions along the waveguide length creates an additional p-n junction that is formed at the interface between segments, thus further increasing the capacitance per unit length.
As shown in the right inset of Fig. 1, the period Λ of the interleaved phase shifter segments is 560 nm, with equal length (half-period) p- and n-doped fingers. This period was chosen to be as small as possible to generate a large junction area, while still retaining high yield in fabrication. The p-type finger region was targeted to extend 110 nm below the top surface, occupying the upper half of the waveguide. The length δ that the p-doped edge region extends into the waveguide is 100 nm, intended primarily to connect the p-doped finger regions to the contact but also generating additional active junction area interacting with the optical mode. The silicon waveguide itself is 500 nm in width and 170 nm in height, with a 50 nm thick silicon slab providing carrier transport between the active region and the contacts. A combination of phosphorus and arsenic were used as dopants for the n-type regions, and boron for the p-type regions. A doping concentration of 2 × 1018 cm−3 was chosen as a target for both the p- and n-type regions, while 1 × 1019 cm−3 was the target for the n+ and p+ regions and 1 × 1020 cm−3 for the n++ and p++ regions. Dopants were activated with a standard rapid thermal anneal step at temperatures near 1000°C.
2.3 Experimental results
The phase shifter design described above is fully compatible with the IBM CMOS-Integrated Nano-Photonics (CINP) process discussed in Refs. [3–5]. To fully characterize the phase shifter performance, a special testsite was fabricated with this process. In order to accurately determine the capacitance per unit length and the resistivity of the phase shifter, the testsite contained phase shifters of 250 µm, 1000 µm, and 2490 µm in length, as well as calibration structures with open and short circuits. Wafer-scale electrical I-V and C-V measurements were collected on 27 dies from phase shifters of different lengths as well as from calibration structures.
The capacitance per unit length of the interleaved phase shifter was determined from the slope of the measured capacitances of devices with different lengths, measured under a reverse bias of Vb = −1V to reflect typical bias conditions for modulation. After the parasitic capacitance originating from the pads and wiring was calibrated out, the resulting low-frequency capacitance was found to be 0.65 fF/µm. To the best of our knowledge, this is the largest experimentally measured reverse biased PN diode phase shifter capacitance per unit length [10, 14, 16, 18, 24, 32], although higher values have been predicted theoretically .
The resistance values of the phase shifters were measured on the same testsite, with the diode strongly forward biased in order to extract the series resistance. The measured values are dominated by the contact resistance, and did not show a clear trend among the different phase shifter lengths, placing an upper limit on the phase shifter series resistivity of <1 kΩ*µm. Considering both of these values, the inherent RC time constant of the phase shifter section (1/2πRC) should be greater than 100 GHz.
The optical propagation loss was determined by measuring the transmission through a set of phase shifters of different lengths. A propagation loss of 35dB/cm was estimated in the 1550 nm wavelength range, which compares favorably to other modulator designs optimized for high capacitance and low drive voltage [10, 11, 17, 33, 34]. Fundamentally, phase shifter propagation loss in microring modulator designs does not contribute significantly to the overall modulator insertion loss, as mentioned above in Sec. 1. However, it can affect the microring optical quality factor Q, hence also limiting the achievable drive voltage reduction from resonant enhancement. The intrinsic Q of the microring modulator created from the interleaved phase shifter with 35 dB/cm propagation loss can be estimated as about 20,000. In reality, the optical design of a microring modulator operating at 25Gbps requires a Q of less than 10,000 in order to avoid unwanted effects caused by exceedingly long cavity photon lifetimes at the resonance [21, 23]. Therefore, the optical loss of the interleaved phase shifter is not a limiting factor in either insertion loss or device performance for a ring modulator targeting 25 Gbps.
3. Microring modulator design
A microring modulator based on the interleaved phase shifter design was fabricated using the IBM CINP process [3–5]. Figure 2 shows micro-photographs of the complete device before (a) and after (b) processing of Cu metal interconnects.
The ring presented in this paper is in a racetrack add-drop configuration with a 301 μm circumference and 250 µm length of interleaved phase shifter, with a gap between the ring and bus waveguides of 250 nm. The device as tested had a low-frequency capacitance of 184 fF at a DC bias of −1V, and a series resistance of 12 Ω as extracted with the diode strongly forward biased. The device is connected to a pair of pads through 10 μm wide patterned electrical lines, which contribute to an additional parasitic capacitance of 112 fF. The parasitic contact resistance, including the contact resistance between the RF probe and the pads, is measured to be 7 Ω. With the intrinsic resistance and capacitance, and including the parasitics originated from the pads and wiring, the entire device has an RC time constant of 28 GHz.
Optical measurements at the through port showed a series of resonances around 1550 nm wavelength with a free spectral range of 2 nm. A spectrum containing three consecutive resonances was fitted with a transfer-matrix model of a microring resonator . Loss from two directional couplers, the phase shifter, and 50 µm of passive waveguide was included. The passive waveguide propagation loss was measured to be 3 dB/cm from separate cutback measurements done on four lengths of passive waveguide. This fitting procedure allows for simultaneous extraction of the roundtrip loss, microring free spectral range, coupling coefficient to the buses (assuming the two directional couplers are identical), the round trip loss of the microring, and the intrinsic quality factor Q. The fit showed an off-resonance insertion loss of less than 0.2 dB. The loaded optical quality factor estimated from the fitting procedure was found to be 7,500. This value is lower than the intrinsic Q based on the phase shifter loss of 20,000, as discussed in Sec. 2.3, due to the coupling to the add and drop bus waveguides. The loaded Q is high enough to achieve significant resonant enhancement, while still not limiting the modulator bandwidth due to the optical lifetime. The loaded Q of 7,500 gives a bandwidth limitation of ~26 GHz. Combined with the intrinsic RC time constant of the modulator including pads and wiring, the final predicted device bandwidth is 19 GHz, which is sufficient bandwidth for the target bit rate of 25 Gbps.
4. Measurements of electro-optic figure of merit VπL
Figure 3(a) shows a set of optical transmission spectra measured at the through port of a microring modulator at various applied bias voltages. All measurements were performed at room temperature, and the spectra were normalized to the maximum transmission of each resonance. The observed fringe contrast of 7 dB at 0 V is determined by the chosen coupling coefficients at the add and drop ports, which are set by the fabricated width of the coupling gap and length of the coupling region in Fig. 2. For reverse bias voltages, the leakage current does not exceed 1 nA even for very large biases above 5 V. As the reverse bias voltage increases, the spectral position of the resonance shifts to longer wavelengths, indicating an increase of the effective optical index. This spectral shift is a result of a depletion of the free carriers that overlap with the optical mode in the phase shifter.
The optical transmission spectrum at each applied voltage was fitted with a model of a microring resonator that was modified to reflect the additional drop port coupler of the add-drop filter, as described in Sec. 3. From the change in resonant wavelength extracted from the fit as the applied voltage is changed, the phase shift that light experiences in a single round trip can be determined. The phase shifter length that the light interacts with in a single round trip is simply the physical length of phase shifter within the microring, in this case 250 µm. Therefore, this method allows a calculation of the intrinsic phase shifter electro-optic figure of merit (FOM), VπL: the phase shifter length required to achieve a 180° phase shift for a given applied bias voltage change Vπ. The method used to measure the FOM takes advantage of the sensitive nature of the microring resonance to achieve more accurate results, but the FOM extracted is an inherent property of the given phase shifter design. Thus, it is independent of the specific optical configuration of the modulator, for example microring or Mach-Zehnder interferometer configurations.
Figure 3(b) presents the extracted FOM across a range of bias voltage changes. Error bars represent the spread of extracted FOM values measured under the same conditions on 4 different dies across the wafer, showing relatively small die-to-die variations. From Fig. 3(b), it can be seen that a 0 V to −1 V bias change on the modulator produces a FOM of 0.76 V-cm, increasing to 0.84 V-cm for a 2 V bias change and decreasing to ~0.64 V-cm in the limit that the required bias voltage becomes very small (i.e. for a very long device or a high Q resonator). This dependence of the FOM on voltage is common to all silicon modulators based on the free-carrier induced phase shift. In contrast to the linear Pockels effect used in lithium niobate modulators , the charge injected and/or depleted within a silicon p-n diode phase shifter varies strongly across applied bias voltages due to the nonlinear capacitance response of the diode. Therefore, when quoting the FOM for a silicon modulator to compare with the existing literature, it is important to specify the applied bias voltage range across which the phase shift is measured.
The FOM presented in Fig. 3(b) is defined using a phase shift between V = 0 and the applied bias voltage listed in the figure, and can be used to predict the extinction ratio of a modulator operating with a RF data signal in the same range of applied voltages. For example the FOM data point at −1 V reverse bias is applicable for a modulator driven with a single-ended RF signal of Vpp = 1 V under a DC bias of VDC = −0.5 V. Under these bias conditions, in the range from −1 V to 0 V, the measured FOM of the interleaved phase shifter is 0.76 V-cm. This is comparable to the current record value of 0.71 V-cm for a reverse-biased p-n diode phase shifter measured from −0.5 to 0.5 V . Phase shifters based on MOS-capacitor structures have been demonstrated with lower FOM values of 0.5 – 0.67 V-cm measured from −2 to 0 V , and 0.24 V-cm for a MOS-capacitor phase shifter above 2.5 V reverse bias . However, the modulators utilizing these high-FOM phase shifters were limited to data rates at or below 12.5 Gbps. In the next several sections, operation of a microring modulator based on the interleaved phase shifter is demonstrated at higher data rates of 25 Gbps and above.
5. High-speed modulator performance
To test the high-speed operation of the interleaved microring modulator, eye diagram measurements were performed using a SHF BPG 40A 40 Gbps pattern generator. Picosecond Pulse Labs 40 GHz 5510K attenuators were used as needed to decrease the pattern generator output voltage swing from 3.9 Vpp to the desired modulator applied drive voltage. A Picosecond Pulse Labs 40 GHz 5542 bias tee was used to combine the high-speed data signal with a DC bias voltage, and both were sent through a GGB 40 GHz picoprobe to the microring modulator. The modulated optical output was received by an Agilent 86100C oscilloscope fitted with an Agilent 28 GHz 86115B optical module, with the internal bandwidth limit set to 22 GHz to decrease instrument noise. An Agilent 86107A precision timebase module was used to limit instrument jitter. In order to isolate the effects of intersymbol interference from the incoherent instrument and setup noise, two sets of eye diagrams were measured: one set with non-averaged PRBS 231 data (eye diagram), and one with pattern-locked and 16-fold averaged PRBS 27 data (eyeline diagram). All measurements were performed at room temperature.
Figure 4(a) shows measured PRBS 231 NRZ eye diagrams from 15 to 40 Gbps at an applied drive voltage of 1.6 V (peak-to-peak). DC bias values and laser wavelength were optimized at each bit rate to maximize extinction ratio while minimizing excess modulation loss. Increasing DC bias decreases junction capacitance slightly, which can provide a small increase in speed at the cost of a minor decrease in extinction ratio, hence the DC bias value chosen for optimal modulator performance varies with bit rate. The excess modulation loss is defined as the difference between the maximum transmission of the modulator (in this case, the transmission when the laser is off-resonance with the ring) and the one-level of the data signal during operation. Bias values ranged from −1.5 V at low bit rates to −3 V at higher bit rates, trading lower extinction ratio for increased speed, due to smaller overall junction capacitance. This results in an excess modulation loss, defined in Fig. 5(b) , that changes from 2 dB at low bit rates to 3 dB as the bit rate and DC bias voltage increases. Note that the RF drive voltages quoted are the applied voltages at the input to the electrical probe. The drive voltage experienced by the device may be higher than this, as much as double, owing to signal reflection because of the impedance mismatch between the un-terminated probe and the high impedance reverse-biased p-n diode.
Figures 4(b) and 4(c) show a detailed analysis of the vertical eye closure penalty (VECP) and the extinction ratio for the pattern-locked and averaged PRBS 27 eyeline diagrams, measured under the same DC bias and laser wavelength conditions as Fig. 4(a). The VECP is defined as the relative eye opening on an averaged eyeline diagram,Fig. 5(a). The extinction ratio (ER) is a complementary measure to the VECP, giving the ratio of on-state power to off-state power. It is measured from the lowest frequency components present in each eye diagram so as not to consider the effects of eye closure due to the VECP in this metric:
In Fig. 4(b), the VECP is presented across a range of data rates from 10 Gbps to 40 Gbps. These penalties are compared at four different applied drive voltages: 0.4 V, 0.8 V, 1.6 V, and 2.3 V. The data rate at which a 3 dB VECP occurs can be estimated from the data in Fig. 4(b) as 22 Gbps for 0.4 V drive, 26 Gbps for 0.8 V, and 32 Gbps for applied voltages of 1.6 and 2.3 V. This can be considered as the limiting bit rate above which the modulator performance is strongly affected by intersymbol interference. In Fig. 4(c), ER measurements for the interleaved microring modulator are presented across the same range of drive voltages and bit rates as in Fig. 4(b), using the same averaged eyeline diagrams for the calculation. At the bit rates for which a 3dB VECP occurs for each of the four voltages, the ER is measured to be 1.6 dB, 2.4 dB, 3.3 dB, and 4.2 dB, respectively.
The 3 dB VECP occurs at lower bitrates than would be expected when considering the intrinsic interleaved microring modulator limit of 19 GHz, which was previously estimated in Sec. 3. Considering that a bandwidth of approximately 0.7 times the bit rate is required for NRZ data transmission, a modulator with a bandwidth of 19 GHz should support a bit rate of 27 Gbps without measurable VECP. The additional delay observed in measurement is due to the 50 Ω output impedance of the pattern generator, which lengthens the RC time constant of the combined system over that of the modulator in isolation. Taking this additional factor into account, the combined electrical and optical-lifetime bandwidth limit of the externally driven interleaved microring modulator decreases to 7.2 GHz. This results in a degradation of the signal at bit rates above 10 Gbps, as measured.
However, in a monolithically integrated transmitter, with the modulator and driver co-designed on the same chip, the driver impedance can be more favorably matched to the modulator. In addition, the 112 fF parasitic capacitance due to the large electrical probe pads can be eliminated, as the pads would be unnecessary in a monolithic transmitter. In this case, the combined RC and optical-lifetime bandwidth limit would increase substantially to 18 GHz, capable of supporting 25 Gbps data rates and beyond.
6. Impact of drive voltage
Achievable drive voltages on CMOS chips are limited to approximately 1 – 2 V for current technologies, and are projected to decrease further at future technology nodes. In addition, the power consumption of a lumped-element reverse-biased silicon modulator scales quadratically with increasing drive voltage, indicating that low drive voltage is an essential requirement if a silicon photonic interconnect based on such a modulator is to fulfill the demanding power requirements for datacom standards [6–8]. To determine the lowest drive voltage at which the interleaved microring modulator can operate at 25 Gbps, Fig. 5(a) compares 25 Gbps NRZ PRBS 27 eyeline diagrams, pattern-locked and averaged 16 times, for all four drive voltages measured.
At the lowest drive voltage of 0.4 V, the modulator is in the small-signal regime, illustrated schematically in Fig. 5(b). In this regime, the optical response is approximately linear and the bandwidth of the modulator is primarily controlled by the RC time constant of the device and the 50 Ω pattern generator impedance. Even in this very low voltage regime, the modulator still performs at 25 Gbps, albeit with a VECP of 4 dB. The 20% - 80% rise time can be estimated from the eye diagram as 34 ps, measured at a bit rate of 10 Gbps to extract the effects of intersymbol interference. This rise time is comparable to the rise time from the estimated 7.2 GHz modulator bandwidth limit, calculated as 31 ps.
With increasing drive voltage in Fig. 5(a), the modulator transitions into the optically-limiting regime, illustrated schematically in Fig. 5(c). In this regime, the voltage swing is large enough that the laser line samples the nonlinear portions of the ring resonance. Because the slope of the spectral response decreases both at the resonance peak and far off-resonance, the resonance acts as an optical limiter on both the ‘zero’ and the ‘one’ rails, compressing any eye closure due to electrical bandwidth limitations and resulting in a more open eye with faster transitions. In Fig. 5(a), the eyes at 0.8 V and 1.6 V drive voltages display rise times significantly shorter than at 0.4 V, estimated as 25 ps and 21 ps respectively. The results of this limiting behavior can also be seen clearly in Fig. 4(b) for all bit rates, with the 0.8 V drive VECP being consistently smaller than that for 0.4 V, and the VECP at 1.6 V drive being even further reduced.
At the highest drive voltage of 2.3 V, the rise time decreases even further to 17 ps, due to the large optical limiting present. At this drive voltage, limitations due to the optical lifetime begin to become important. The overshooting visible in the 2.3 V eye of Fig. 5(a) is a characteristic feature that occurs when the rise time of the modulator approaches the lifetime of the optical cavity, which is approximately 6 ps. Though the rise time is still significantly longer than the optical lifetime, the effects of the long photon lifetime within the resonant cavity can still be observed. The overshooting is due to interference between the cavity photons that have been adiabatically tuned along with the resonator, and the steady-state non-resonant photons outside the ring [21, 23]. This cavity lifetime limitation is one reason why a continued improvement in the VECP is not observed between 1.6 V and 2.3 V drive in Fig. 4(b). It can also be seen in Fig. 4(c) that the steady improvement of ER with drive voltage plateaus around 2.3 V. This is, again, due to the optical limiting effect: at these higher voltages, the resonance shifts through a large fraction of the total ring resonance depth. The slope of the resonance flattens significantly near the top and bottom of the resonance, as can be seen in Fig. 3(a), meaning that the noise on the rails is compressed, but any additional resonance shift has a diminishing impact on the ER.
Low drive voltage is essential to minimize the power consumption of a lumped-element silicon photonic modulator, as discussed in Sec. 2. As these modulator devices are fabricated in a standard CMOS front-end platform and ultimately target monolithic integration, the large pad capacitance can be subtracted when making estimates of the RF power consumption. Even assuming that the drive voltage present at the device is doubled due to reflections, the worst-case power consumed for 25 Gbps operation with 1.6 V drive is 471 fJ/bit. At the lowest drive voltage of 0.4 V, which maintains a VECP of 4 dB at 25 Gbps, and can be driven by very low-power CMOS drivers, the power consumption would be only 29 fJ/bit.
The interleaved microring modulator performs well even at very low RF drive voltages, and performance at high bit rates improves further as the drive voltage is increased, at the cost of higher power consumption. Even assuming an effective drive voltage of twice what was applied, the lower two voltages (0.4 V and 0.8 V) measured in Figs. 4(b) and 4(c) and Fig. 5(a) are still readily accessible by CMOS drive circuits . If lower drive voltages or higher bit rates are desired, it has been shown that VECPs much larger than 4 dB can be compensated by a relatively small amount of pre-emphasis added to the drive signal, with reasonable costs in power consumption [20, 26, 40]. The optical lifetime limitation on the modulation bandwidth can be mitigated by lowering the quality factor on the resonator such that the optical lifetime is much shorter than the desired rise time of the modulator. This will decrease the resonant enhancement slightly, but will allow a faster optical response to be achieved.
To maximize the benefits of the optical limiting behavior caused by the nonlinear ring transfer function, the depth of the steady-state ring resonance should be matched to the desired ER of the modulator. This will result in a system that is similar to Fig. 5(c) rather than Fig. 5(b), even for small electrical drive voltages. This scenario will draw the maximum benefit from the nonlinearity of the optical transfer function, while also minimizing the excess modulation loss on the one level. Similar devices to the modulator presented in this paper, but fabricated with integrated thermally tunable couplers, have achieved ring resonance depths and extinction ratios of greater than 16 dB [29, 31].
7. Evaluation of 10 km reach
Figure 6(a) shows a back-to-back 25 Gbps eye diagram, in which the optical output of the modulator is measured after a minimal length of fiber. The eye is measured using PRBS 231 data at a drive voltage of 1.6 V, a DC bias of 1.76 V, and an optical wavelength of 1545.94 nm. The back-to-back extinction ratio is 3.23 dB, the RMS jitter is 1.9 ps, and the excess modulation loss on the one level is approximately 3 dB.
The modulator performance after a transmission distance exceeding 10 km is tested through an 11.4 km length of single-mode fiber connected after the modulator, under the same measurement conditions. Figure 6(b) presents the resulting eye diagram, showing less than 1 dB of increased VECP relative to the back-to-back eye diagram in Fig. 6(a). Further characterization is necessary to determine the performance power penalty for different lengths of fiber, however this is an initial step towards demonstrating a modulator that can fulfill the requirements for mid- to long-range operation.
A microring modulator operating with CMOS compatible drive voltages and with bit rates up to 40 Gbps is demonstrated. Power consumption at 25 Gbps for a monolithically integrated chip is estimated at 471 fJ/bit, and at 20 Gbps could be as low as 29 fJ/bit. The modulator insertion loss is lower than 0.2 dB, and the excess loss on the ‘one’ level during modulation at 25 Gbps is 3 dB. The extinction ratio of current devices hits a maximum of 4 dB, however a simple modification to the microring coupling will increase that value dramatically, and can be optimized to take advantage of the optical nonlinearity to achieve fast transitions and low excess modulation loss on the optical transmission. Stable performance is demonstrated across more than 10 km of single-mode optical fiber, showing minimal signal degradation. Together, all of these characteristics indicate that this modulator platform shows promise for achieving the necessary metrics for contemporary datacom standards.
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