We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 μm Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data.
©2012 Optical Society of America
The Germanium (Ge) photodetector (PD) is a critical building block in Silicon photonic links. To meet low-power requirements for high-bandwidth-density chip-to-chip interconnects, the PD should minimize capacitance while attaining a high responsivity. The receiver in a Si photonic link often includes a PD followed by a transimpedance amplifier (TIA). The TIA signal-to-noise ratio (SNR) for a bandwidth-constrained design is maximized when its input capacitance (Ci) is made roughly equal to the PD capacitance (Cd) . Since the TIA power consumption is proportional to its size, and hence to its capacitance, Ci, further reducing the PD capacitance can help reduce the TIA power consumption, which is often a significant part in the power consumed by the link. A small PD capacitance is especially desirable for high-speed links, since the maximum SNR is proportional to (BW2 × Cd)−1 , where BW is the bandwidth of the TIA connected with the PD.
Ge PDs on SOI have been extensively researched, and various fabrication techniques and device structures have been developed [2–12]. To achieve high responsivity, waveguide PD geometries are advantageous over surface illuminated PDs due to their ability to create longer absorption length without causing carrier-transit-time limits to their bandwidths. To mitigate the 4% lattice mismatch for Ge-on-Si heteroepitaxy, a popular growth approach is to first grow a thin Ge seed layer at a low temperature (<400 °C) that aims to flatten Ge-on-Si nucleation, and then grow a thicker Ge layer at higher temperature (>700 °C) for dislocation reduction. This method can produce high-quality tensile-strained Ge films [6–10]. The tensile strain causes bandgap shrinkage, which enhances the Ge absorption in the C-band. The absorption coefficient at 1550nm wavelength can be increased from <1000 cm−1 in bulk Ge up to 5000 cm−1 in high-temperature-grown Ge films [9, 10]. However, the high-temperature Ge growth may be difficult to integrate into a standard CMOS process [3–5]. In terms of light coupling from the Si waveguide to the Ge absorber, evanescent coupling [3–8, 11] and butt coupling [9, 10] have both been demonstrated. Evanescently coupled structures are generally easier to fabricate, although butt-coupled structures are more efficient and can result in shorter Ge absorption length and potentially lower capacitance. In terms of electrical design, vertical PIN junctions [6–8, 11] generally exhibit higher capacitance, but they offer lower dark current since the defected Ge buffers can be excluded from the junctions; whereas lateral PIN and MSM junctions [3–5, 9, 10] have the advantages of easier fabrication and lower capacitance, but usually with higher dark current.
In this paper we report improvements to Ge PDs using low-temperature-grown Ge with evanescent coupling to the Si waveguide. PDs built with this structure and material normally require longer absorption length (thus higher capacitance) to avoid low responsivity in the C-band. Our improvements to the PD device include:
- 1) The addition of a distributed Bragg reflector (DBR).
- 2) The use of fingered 1st-layer metal (M1) electrodes.
- 3) The optimization of the metal contact positions.
With these improvements, a 10-μm-long Ge PD manufactured in a commercial CMOS process achieves >0.8 A/W responsivity over the entire C-band, with a very low capacitance of <7 fF.
2. Device structure and simulations
Our Ge PD was manufactured with Luxtera/Freescale’s 130nm CMOS Photonics technology. Figure 1 is a 3D schematic view of the baseline device structure. The Ge epitaxy is inserted after the poly gate process, and the PDs share the same metal contacting process with transistors [3, 4]. The Ge film was grown on top of the un-etched SOI at a relatively low temperature (<600 °C) in order to minimize the thermal impact to the transistors. A lateral PIN junction is employed to collect the photocurrent, as shown in Fig. 2 . These choices of PD structure and fabrication process allow the straightforward integration of the Ge module into the standard CMOS process, but the drawbacks are that it requires a longer absorption length (thus higher capacitance) to avoid low responsivity in the C-band, and that it may result in higher dark current. In the baseline design shown in Fig. 1 and Fig. 2, a responsivity of 0.85 A/W at 1550 nm was achieved for a 28-μm-long PD reverse-biased at 1 V, with a dark current of 3 μA [3, 4].
To further reduce the absorption length and the device capacitance while still maintaining a high responsivity in the C-band, we have implemented a number of design improvements based on the optical analysis and simulations. First, we add a DBR at the end of the PD so that the residual un-absorbed optical power can be reflected back and be absorbed for a second time. This method in principle can double the absorption length without adding any device capacitance. Since the structure is not resonant, no spectral bandwidth narrowing occurs. The DBR can be implemented in the Si layer, as shown in Fig. 3(a) .
By virtue of its evanescently coupled structure, the optical wave entering into the PD waveguide will excite multiple modes centered at different vertical positions. Coupling between these modes forces the unabsorbed optical power to oscillate between the Si and Ge layers while propagating through the PD, which results in certain spots in the Ge layer having very low optical power densities . This gives us opportunity to minimize metal absorption loss by placing metal contacts only at these spots. Our second modification optimizes the locations of these metal contacts. Figure 3(b) shows the beam propagation simulation result for TE mode at 1550 nm with the assumption of no metal absorption and no DBR. The green curve shows the power minima in the Ge layer, which tells us where to place metal contacts; the red curve shows the un-absorbed power propagating along the waveguide. With 15-μm-long Ge, about 90% optical power can be absorbed in a single trip, thus the addition of a DBR can improve the responsivity by at most 10%. However, if the Ge length is cut to 10 μm to reduce capacitance, only 75% optical power will be absorbed in a single trip, and the DBR can improve the responsivity by up to 25%.
Recognizing that the 1st metal layer (M1) can also cause absorption loss due to its close vicinity to Ge layer leads to our third improvement. The use of fingered M1 electrodes as shown in Fig. 3(a), in contrast to the continuous M1 electrodes in Fig. 1, can significantly reduce the overlap between the optical mode and the M1 metal, thereby reducing absorption loss and improving the PD responsivity.
3. Test results
To verify the effect of each design improvement, we have made Ge PDs with varied designs on the same wafer. The baseline device structure before these improvements can be found in [3, 4, 13]. The distributed Bragg reflector (DBR) is made by etching 220-nm-deep trenches on the 300 nm thick SOI, with a period of 310 nm and a duty cycle of 50%. Both simulation and test results indicated that this DBR grating has almost 100% reflection over the C-band. Figure 4 shows the measured responsivity at 0.5V reverse bias for four different PDs, all with 15 μm Ge length. The PD of the green curve has no DBR; its metal contacts on Ge are placed uniformly (with spacing cs1) starting from the Ge edge; and its M1 electrode is continuous. The pink curve shows the effect of adding a DBR at the end of the PD. The observed responsivity improvement is only a few percent at 1550 nm wavelength, much less than the 10% predicted by simulation. This may be improved by optimizing Ge length so that most of the residual optical power is in the Si layer when it exits the PD, which will ensure that it can be reflected back by the DBR. The PD of the blue curve further uses fingered M1 electrodes, and we see clear improvement over the pink curve. The PD of the red curve is similar to the PD of the blue curve, but with a different contact spacing of cs2. This contact spacing is close to the simulated optimum, which varies with the PD layer structure, and it does produce higher responsivity. Figure 5 shows the measured responsivity of a 10 μm Ge PD having incorporated all the above design improvements, and it has achieved >0.8 A/W over the entire C-band (up to 1565 nm). The dark current is measured 0.3-0.5 μA at 0.5 V reverse bias for all these devices, and the measured I-V curves are very similar to the ones published in [3, 4].
As mentioned earlier, PD capacitance is an important metric that impacts both receiver speed and power consumption. A PD capacitance of a few fF is generally considered difficult to be accurately measured; therefore it is often estimated using a simplified calculation or static modeling. Very low PD capacitances of ~1 fF have been reported using such analytic methods [5, 11]. Our 10 μm Ge PD would, similarly, have a calculated capacitance of 0.6 fF. However, using a method of combined RF testing and circuit model fitting , we were able to accurately characterize the capacitance to be ~9 fF for the 15 μm PDs and ~6.7 fF for the 10 μm PDs, all at a reverse bias of 0.5V. The extracted series resistances were around 350 Ω and 530 Ω for the 15 μm and 10 μm devices, respectively. The resulted RC bandwidth limit was around 40 GHz, much higher than the actual PD bandwidth of 14-19 GHz measured for multiple samples at 0.5V bias, indicating that our PD bandwidth was mainly limited by the carrier transit time (estimated to be <21 GHz). The measured capacitance is much larger than the calculated value, indicating that the simple plate-capacitor approximation is not valid for such a device structure. Various physical effects may have contributed to the PD capacitance. The fringing capacitance  is expected to be very significant in our PDs, since the P-N separation is larger than the Ge film thickness. Dopant diffusion, which reduces the P-N separation, and material defects, which change the electric filed distribution, can also contribute to the PD capacitance significantly.
We have demonstrated design improvements for CMOS-compatible Ge PDs employing evanescent coupling with low-temperature-grown Ge film. With an integrated DBR, fingered M1 electrodes, and an optimized contact geometry, a 10-μm-long and 2-μm-wide Ge PD manufactured by a commercial CMOS process has achieved >0.8 A/W responsivity over the entire C-band. The PD has a calculated capacitance of 0.6 fF, with a measured capacitance of <7 fF (including fringing capacitance, dopant diffusion, and material defects). This places it as a leading candidate for compact, low-cost, and low-power silicon photonic links .
This work is supported, in part, by DARPA under Agreements HR0011-08-09-0001. The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government. Approved for public release, distribution unlimited.
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