In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10−7 and 10−12 for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W.
© 2012 OSA
Internet video and social media are changing our lives at a very fast pace. Given the anticipated growth of digital media in the world ($2.2 trillion over the next five years ), today’s demand for broadband connectivity is driven by necessity, not luxury. To achieve sustainable economical growth around the world it is important to make sure the cost of internet is as low as possible, both in price and energy. This can only be achieved through the development of a low cost energy efficient Terabit per second (Tbps) communication infrastructure. Only optical fiber technology can handle multi-Terabits per second of data. Hence, an increase in data rates to 400 Gbps - 1 Tbps in next-generation optical communication systems has become inevitable. In such systems, data integrity is stressed by physical layer impairments, i.e. chromatic dispersion, polarization mode dispersion and nonlinearity in the optical fiber . There is a consensus that deploying advanced forward error-correction (FEC) technologies in optical links is one of the most cost-effective methods to combat system impairments, increase the data rate, and extend its reach . Therefore, it is extremely important to investigate technologies that will enable the development of power efficient FEC decoders.
Current optical networks employ error-correction approach based on classical hard decision error-correcting codes such as Reed-Solomon (RS) or Bose-Chaudhuri-Hocquenghem BCH codes . Since the discovery of powerful decoding algorithms in the 1990’s [3–5], wireless communications has been realigned to use a new class of codes called low density parity check (LDPC) codes . LDPC is a linear block code characterized by a sparse parity check matrix, i.e. the parity check matrix of the code has a low number of ones enabling simpler decoder architecture while providing high coding gain . LDPC codes have already been embraced by the optical community because of its near Shannon limit performance [2, 7]. Promising research work is looking into simplified structure towards fully parallel implementation, high throughput and low complexity [8–11]. Recent simulation results showed that a low complexity energy efficient delayed stochastic decoder in 90 nm CMOS technology could occupy 56.5 mm2 of area with a core throughput of 477.7 Gb/s . In theory, LDPC codes can be very powerful [2, 7, 11], but their practical implementation for optical communications links at ultra-high data rates remains a challenge since the decoding of the code requires soft-decision bits or multiple level of information about the received bits. Conventionally, optical communication systems rely on a hard-decision approach where the information about the received bits consist of only one bit, either a digital “1” or “0” was received. On the other hand, a 2-bit soft decision decoder requires 22-1 = 3-decision levels where the middle level is a bit corresponding to the hard-decision digit and the other two levels indicate the probability or confidence regarding the hard-decision (e.g. the received bit is certainly a “0” or maybe a “0” based on noise level or other physical layer impairments). This concept was recently demonstrated as a 32 GS/s 2-bit soft-decision circuit for LDPC decoders [12, 13]. A net coding gain (NCG) of 9.3 dB was achieved at 126.4 Gb/s by combining four soft-decision circuits .
Recently, Sakib, et al. demonstrated a low complexity and energy efficient optical front-end for soft-decision decoders . The proposed front-end operating at 12.5 Gb/s consumes 5 W of power with NCG of 2.75 and 6.73 dB at BER of 10−4 and 10−9, respectively. In this paper, a similar approach is used to demonstrate a 45 Gb/s optical front-end. The proposed optical receiver design is implemented by tapping the incoming optical signal prior to the photodetector and using an exclusive-nor (XNOR) gate. The receiver architecture in  is simplified using a passive power divider instead of an active electrical fanout buffers enabling the bit rate to be pushed to 45 Gb/s. It is also shown that the soft-decision front-end can be used as a 2-bit flash analog-to-digital converter (ADC) to use with digital equalizers, making it a good candidate for systems requiring digital post-processing. For erbium doped fiber amplifier (EDFA) based optical systems, the noise distribution is Chi-Squared and symmetric Gaussian for direct detection and coherent receivers, respectively [12, 14]. In this paper, the terminology “flash ADC” is used in the context of multimode links. Multimode links can be modeled as systems with additive Gaussian noise and symmetric Gaussian amplitude distribution such that the received optical signal can be equalized with digital equalizers. A flash ADC is a simple form of an ADC in which the input voltage to the ADC is divided into multiple levels to several comparators or limiting amplifiers enabling higher speed by parallelizing the digitization process. The outputs of these comparators are fed to a binary encoder that gives the digitized bits. The soft-decision front-end presented in this paper is essentially a flash ADC.
The paper is organized in five sections. In Section II and III an overview of the soft-decision circuit and the proposed architecture is described. In Section IV the experimental setup and details of the hardware implementation is presented. In Section V, the operation of a 45 Gb/s soft-decision circuit and 32 GS/s 2-bit flash ADC are shown. The performance of the proposed scheme is then evaluated for the decoding of long block (high coding gain higher complexity decoder for long haul single mode systems) and short block length (moderate coding gain low complexity decoder for short haul multimode systems) LDPC codes. Results are presented in terms of post-FEC bit error rate (BER) versus pre-FEC Q-factor and received optical power which is a figure of merit for long haul and short haul links, respectively. The electrical power budget is calculated both for 32 GS/s and 45 GS/s 2-bit flash ADCs. Finally, we draw our conclusion in Section VI.
2. Optical vs. electrical soft-decision and applications
For soft-decision based front-end, a linear response is required to enable the optimization of the multiple threshold levels. Optical receivers for communication conventionally use limiting amplifiers with nonlinear response since hard-decision uses only one single threshold set approximately in the middle of the dynamic range. The proposed optical front-end provides a number of advantages in terms of linearity, bandwidth, optoelectronic integration, power consumption and cost when compared to existing soft-decision front-ends [12, 13]. The soft-decision LDPC decoders use the logarithm of the signal-to-noise ratio (SNR) for error correction. The nonlinearity limit of the front-end will impact the signal probability distribution, and thus the relationship between SNR and the bits in error processed by the decoder which relies on a linear relationship. In such case, the noise distribution can no longer be modeled by simple equations upon which the decoder operates . It will adversely affect the decoder’s performance requiring complex nonlinear equalization of LDPC codes . Since the photodetectors can have a linear response even for input optical power levels as high as 10 dBm, fanning out optically will satisfy the linearity requirements . The optical fannout approach also offers a larger front-end bandwidth for opto-electronic integration as optical devices have a larger bandwidth than the electronic counterpart. For example in , the 130 µm CMOS compatible silicon on insulator (SOI) technology uses electronics with bandwidth of 7-10 GHz compared to 18-25 GHz for the photodetectors . In addition, photodetectors exhibits a smooth roll off characteristics near their 3-dB cutoff region such that the received signal can be equalized using finite impulse response (FIR) filters after the front-end. The front-end requires fewer active devices as the fannout is performed using passive optical devices (i.e. one optical splitter) instead of an electrical buffer leading to potentially less power consumption and lower cost.
3. Soft-decision optical front-end architecture
In this section, the proposed architecture for implementing soft-decision circuit for LDPC decoders at 45 Gb/s is described. Conventional direct-detection receivers provide only one bit of information corresponding to a hard decision. Such receiver consists of a photodiode followed by a transimpedance amplifier and a nonlinear limiting amplifier. The limiting amplifier digitizes the analog signal. Certain advanced error correction codes such as LDPC require soft decision decoding which involves more than one bit of information. The additional bits provide a confidence level of the digitized hard decision. In , we proposed a novel approach to tap out some optical power from a conventional optical system and use it for determining the confidence levels in the LDPC decoder as shown in Fig. 1 . From Table 1 it can be shown that the functionality of the 3-to-2 encoder can be simplified and implemented using a single high speed exclusive-nor (XNOR) gate () . The proposed scheme requires no modification of the current direct detection optical infrastructure (VH = VHard) and provides possibility for using it as a flash type ADC in systems requiring digital equalizers.
The soft-decision circuit is implemented for operating at 45 Gb/s. The signal from the optical system is optically splitted between the soft-decision and hard-decision segments. As shown in Fig. 1, the main building blocks include a power splitter (Anritsu 240C), three high speed linear limiting amplifiers (HMC866) with tunable threshold, and one XNOR gate (HMC-C064). The photodetector from Discovery Semiconductors (DSC-10H) has an RF bandwidth of 46 GHz and responsivity of 0.8 A/W. In the soft-decision segment, the electrical signal from the power splitter is fed into two threshold amplifiers. The limiting amplifiers provide the upper and lower confidence levels, respectively. The threshold values VTh1 and VTh0 are tuned with precision power supplies with a tuning resolution in the order of 1 mV. Threshold levels VTh1 and VTh0 are respectively placed at the lower tail of distribution of the “ones” and upper tail of the “zeros” as shown in Table 1. The outputs of the limiting amplifiers are fed to the XNOR gate which provides the confidence level by encoding the 2-bit binary vector to a single bit indicating the confidence of the received bit (i.e. high or low). The output eye of the soft-decision circuit at 45 Gb/s is presented in Fig. 1. A good eye opening of 341 mVp-p is measured for a 24 mVp-p (point A in Fig. 1) input signal to the front-end and output level of 690 mVp-p (point B in Fig. 1). The soft decision circuit has a sensitivity of 10 mVp-p and gain of 29 dB.
The propagation delay difference between the hard-decision and the confidence bit at the processing device is compensated using a tunable electrical delay line. This can also be achieved using delay lines . Each branch of the soft-decision circuit operates up to 45 Gb/s. A high-speed demultiplexer or an 1:n selector can be used to de-serialize the high speed signals for real time data processing at lower clock rate by an FPGA used for the decoder implementation . In our single-mode optical link setup, the hard-decision and confidence bits are captured by a dual channel sampling oscilloscope for the long block code. The maximum data rate in our multimode optical link setup is 15 Gb/s and a 32 Gb/s 1:2 full rate selector (HMC955) is used to sample the signal for the short block length code. Changing the clock rate controls the number of samples per bit (up to 2.1 samples/bit at 15 Gb/s). The data is then processed by a four channel real-time oscilloscope which was controlled through a GPIB interface to capture the desired sample.
4. Experimental evaluation of the front-end
In this section, the experimental setup for performance evaluation of the low complexity soft-decision circuit is described. For performance analysis, two types of LDPC codes will be used. The long block length codes have a high coding gain and usually more suitable for single mode fiber based long haul optical links because of hardware complexity. Whereas, the short block length codes have moderate coding gain, but more suitable for multimode fiber based short haul optical data center links where low latency and power consumption are more important requirements.
The high coding gain LDPC(32768,26803) long block length code is adopted from . This long block is suitable for a high throughput, energy efficient implementation using low complexity stochastic decoders . Due to the structure of its parity check matrix, LDPC codes may exhibit “error floor” phenomena in the post-decoder BER leading to no further improvement in post-FEC BER after a certain signal-to-noise ratio . It is observed from simulation that LDPC(32768,26803) has a very low error floor (<10−12).
We also investigate the performance of short block length LDPC originally adopted from the recent IEEE 802.15.3.c standard for ultra wideband (UWB) wireless communication applications [17, 18]. The receivers for the UWB communication have stringent requirements in terms of cost (less than 2 dollars) and decoder latency. As such, these codes are good candidate for short haul and access network link applications. The BER performances of short block length LDPC (672, 336), (672, 504), (672, 588) and (1440, 1344) codes with a 32 GS/s 2-bit flash ADC and a 6-tap FIR filter equalizer is evaluated for a multimode optical link. The LDPC code is decoded by a sum-product algorithm (SPA) [19, 20]. The number of iterations is set to 50. In simulation, the log likelihood ratios (LLR) required for FEC decoding are calculated based on the received signal’s probability density function . The n-bit soft decision is implemented by quantizing the pre-calculated LLR according to a lookup table.
For error correction coding analysis, Q–factor is used as a figure of merit to correlate the results in the narrow waterfall region. The Q-factor is defined as , where and are the mean and standard deviation of the received mark-bit (), and space-bit () . Though the Q-factor intrinsically assumes a Gaussian distribution, it gives an accurate estimation of the system performance for non-Gaussian Chi-Squared distribution when measured at the optimum decision threshold . The Q-factor measurement is done with optimized threshold level for maximum eye opening on both the captured signal by the oscilloscope and in simulation. Hence, the measurement methodology is equivalent to finding the minimum BER of a non-central Chi-Squared distribution correlating simulation and experimental results.
Experimental test bed for 45 Gb/s single-mode transmission link
The considered system setup for the performance evaluation of LDPC(32768,26803) at 45 Gb/s with optical fiber transmission is shown in Fig. 2 . Three DFB laser sources emitting at wavelengths of 1533.47, 1534.25, 1535.04 nm and with an output power of ~13 dBm/channel (point A in Fig. 2) are used. The three optical channels are combined using a 1:4 optical multiplexer from JDSU with an insertion loss of 6.7 dB. The optical power after the multiplexer is approximately 11 dBm (point B in Fig. 2) or 6.2 dBm per channel. The CW light is then injected into an x-cut zero chirp Mach-Zehnder modulator (MZM), driven by the baseband signal from the output of the programmable pulse pattern generator (PPG). The MZM has an insertion loss of 7 dB, an extinction ratio of ~17 dB (@ DC), and Vπ of 5.2V. The average total optical power after modulation before being launched into the fiber is 0.77 dBm per channel (point C in Fig. 2).
For single-mode long-haul transmission, the long block length LDPC code contains 32768 bits. Each block is preceded by 56 unique preamble bits to identify each frame in the received sequence using cross-correlation. Four large frames and their respective preambles form a super frame of about 132,000 bits captured by the oscilloscope. The size of the frame for LDPC(32768,26803) is shown in Fig. 3 . The super frames of the LDPC code are first loaded into the PPG using a MATLAB interface and will be used for transmission over the optical channel. We use four PPG cards followed by a 4:1 multiplexer (MUX, Anritsu) to generate the desired signal at 45 Gb/s. The PPG module is clocked at 45 GHz by using an Anritsu continuous wave (CW) generator. The baseband signal from the multiplexer is sent to a modulator driver from SHF (810) with gain of 29 dB which amplifies input signals to > + 5.2 V(p-p) drive levels of MZM.
The modulated NRZ-OOK optical channels are first sent through 59.24 km of single mode fiber (SMF), with fiber loss of and chromatic dispersion of 17 ps/ (nm.km) at 1550 nm. The modulated signal is then sent through a spool of dispersion compensating fiber (DCF). The DCF from Suhner has a total loss of ~1.2 dB and return loss of 52 dB at 1550 nm. The DCF has a chromatic dispersion of −1035 ps/nm to perform dispersion compensation for 60 km of SMF–28. After the fiber transmission, the signal is optically amplified by an erbium doped fiber amplifier (EDFA) from INO (FAW CL) with a noise figure (NF) of 5 dB. This EDFA roughly compensates all the losses associated to the SMF-28 fiber, DCF fiber and connectors. The output signal from the amplifier is launched into a 50/50 optical coupler. The other input of the 50/50 coupler is connected to an ASE source (PriTel FA22) to degrade the optical signal to noise ratio (OSNR) and the eye opening of the received signal, i.e. degrade pre-FEC Q-factor. Then a tunable grating filter with bandwidth of 0.8 nm and an insertion loss of 6 dB is used to filter out the middle optical channel (centered at 1534.25 nm) and remove out of band amplified spontaneous emission (ASE) noise. The output of the filter is eventually fed to the soft-decision circuit shown in Fig. 1 via a 20/80 optical coupler. The coupling ratio of 20/80 is a good compromise between degrading performance due to operating near the receiver sensitivity of the soft decision segment and consuming too much power in the soft decision segment at the expense of the hard decision segment . The optical power after the filter (point D in Fig. 2) is approximately 4 dBm. The optical power to the photodetector of the soft and hard-decision segments is −4 and 2.6 dBm, respectively.
The effect of residual chromatic dispersion results in a slight increase of the threshold levels . The optimum input power can vary depending on the system. The optical soft-decision front suffers from a power penalty for the same received optical power due to the power loss from the hard-decision branch when compared to all electrical front-end . However, considering the bandwidth, linearity and simplicity, the optical front-end is an interesting approach.
Experimental test bed for 32 GS/s multimode optical link
The considered system setup for the performance evaluation of error correction codes and equalization with 500 meters of multimode optical fiber transmission is shown in Fig. 4 . The actual binary bits of the different codes are first generated in MATLAB and loaded into the PPG as described before. The baseband signal from the PPG is used to directly modulate a VCSEL-based 10 Gb/s SFP + evaluation board from Finisar emitting at 850 nm. The evaluation board is designed to transfer 10 Gb/s over 300 m of multimode OM-3 type fiber with the sensitivity of −9 dBm and has an electronic bandwidth of 7 GHz. At the receiving end, a 25 GHz multimode photodetector DSC-R409 is used .
The legacy 10 Gb/s transmitter/receiver pair is measured to support a maximum achievable bit rate of 15 Gb/s with a receiver sensitivity of −2 dBm at BER of 10−7 for a back-to-back connection without any equalization or error correction. The optical power output of the transceiver at point A in Fig. 4 is 0 dBm. The modulated optical signal is sent through 500 m of OM-3 type multimode fiber (MMF), with a total fiber loss of 1.5 dB at 850 nm. In this setup, a 28-72% multimode coupler (x = 28) is used instead of a 20-80% which was not available in our laboratory. The back-to-back optical power transferred to the soft and hard-decision segments is −6.2 and −2 dBm, respectively.
Block code measurement methodology
For each measurement, a minimum of 3301 frames (each frame contains ~1.3 × 105 bits) are captured. In total, the number of captured bits is close to 4.4 × 108 bits. For efficient frame capturing and post processing, multiple blocks of coded data are added to form a large frame of about 33,000 bits as mentioned earlier. Similarly, the 56 preamble bits identify each frame in the received sequence using cross-correlation, but are also used as a training sequence for the FIR equalization. The equalization is used to enhance the data rate of the multimode transmission link. The initial tap weights of the equalizer are set using this unique preamble. The tap values were dynamically adjusted using the least-mean squared (LMS) adaptive algorithm throughout the equalization stage .
After capturing the frames, offline processing is done in MATLAB as follow. We first synchronize the frames using cross correlation of the received data with predefined unique preamble. Then we remove the DC offset added by the oscilloscope to the signal. For 45 Gb/s long single mode fiber based system, the signal is down sampled to 1 sample per bit since no equalization is required. The optimum sample on the bits is found by performing a hard-decision error counting on the received bits for different time sampling position. For the equalized multimode fiber based system, two samples per bit are passed to the FIR equalizer for equalization. From the samples of the signal, we decode the signals by soft-decision algorithm for LDPC decoding.
Forward error correction codes add a certain percentage of overhead to the original signal. For example, a LDPC(32768,26803) code has a code rate of 81.8% of the system’s bit rate (R = 26,803/32,768) such that 0.87 dB (10log(0.818) = 0.87 dB) of the optical power is wasted for transmitting the overhead bits and not the actual data of information. We assume that the maximum bit rate is limited by the optoelectronics such that the bit rate can be the same for an uncoded system. Hence, the spectral efficiency with respect to the bit rate remains the same for either a coded and uncoded system while it is worsen for the case of the spectral efficiency with respect to the code rate taking into account the overhead. For system generality, the power penalty due to the overhead is taken into account instead. The Q value corresponding to the measured BER is adjusted by a correcting factor of −10log(R) where R is the code rate defined as the ratio of bit rate without FEC to bit rate with FEC . The correction factor is useful in expressing the results in terms of net coding gain (NCG) which includes the loss due to the code .
5. Results and discussion
Using the setup as shown in Fig. 2, we first experimentally characterize the impact of optical modulation and fiber transmission using measured Post-FEC BER. The BER performance of the long block LDPC code is analyzed with the 45 Gb/s optical front-end. In the second part the performance of the short block length codes with an FIR equalizer is evaluated using setup in Fig. 4 configured as a 32 GS/s ADC. In the last section the power consumed by the soft-decision front-end under different scenarios is presented.
Performance of the 45 Gb/s soft-decision front-end
The experimental and simulated results for 45 Gb/s NRZ OOK signal are shown in Fig. 5 . The pre-FEC Q-factor in the horizontal axis represents the signal quality calculated from the hard decision segment of the optical front-end before soft-decision error correction. The post-FEC BER indicates the bit error ratio after error correction using the confidence information from the soft decision branch. The solid line shows the simulated results for LDPC(32768,26803) using 2-bit soft decision. The squares show the measured values from the experiment.
The net coding gain (NCG) achieved in Fig. 5, are 7.06, 8.25 and 9.62 dB for post-FEC BER of 10−7, 10−9 and 10−12(extrapolated), respectively. Coding gain is 1.9 dB when compared to hard-decision decoding. In addition, the coding gain over conventional RS(255,239) code is 2.96 and 4 dB for post-FEC BER of 10−7 and 10−12 (extrapolated), respectively. Hence, the proposed 2-bit soft-decision front-end is an interesting low power solution for the LDPC decoders.
In this paper, the decoding performance is presented for on-off-keying (OOK) system. The frontend for processing binary phase shift keying (BPSK) would be the same, i.e. the hard decision threshold is chosen midway between the two points in the constellation. If the probability density function (PDF) for + 1 and −1 are symmetrical, 0 can be chosen as the hard decision threshold and the other thresholds are placed on both sides of the hard-decision threshold with no change in the front-end architecture. In the case of an unsymmetrical PDF the thresholds must be tuned for optimum decoding performance. For the soft-decision decoder any higher constellation or modulation format can be broken in to a system in which the threshold resides between two points of the constellation. For example a quadrature phase shift keying (QPSK) or 4-quadrature amplitude modulation (QAM) constellation can be broken into two BPSK systems and processed by the front-end. In such cases the expected NCG will remain the same since the Q-factor is measured for the signal just before the decoder.
Performance of the 32 GS/s 2-bit flash ADC
The proposed 2-bit flash ADC in Fig. 1 is quite suitable for optoelectronic integration using CMOS photonics  because of its linear, wide bandwidth and simpler operation. Very low complexity adaptive FIR equalizers can also be implemented and integrated with the front-end  which will help to increase bandwidth and compensate for the link response. The adaptive equalizer in this paper uses a least mean square algorithm for setting tap coefficients dynamically and is implemented in MATLAB [23,24]. In this section the equalized post-FEC performance for 50% (672,336), 75% (672, 504), 87.5% (672, 588) and 93.3% (1440, 1344) rate codes are presented.
Measured receiver sensitivities at the BER of 10−7 (~50 independent trials over 107 bits) is presented in Fig. 6 as a function of bit rate ranging from 10 to 15 Gb/s. The horizontal axis in Fig. 6 includes the losses due to the overhead. The transmission distance was fixed at 500 m. The FIR equalizer provides 2 dB improvements in the receiver power sensitivity. Figure 6 also shows that the receiver sensitivity is quite sensitive to bit rate and has a big impact on overall FEC performance especially at low received optical powers. It is observed that beyond −15 dBm, stronger error correction codes will not necessarily improve performance. Indeed, at lower optical power the performance is limited by the OSNR of the received signal such that the power penalty from the coding overhead (-10log(R)) exceeds the improvement obtained by coding. However, at higher optical power above the receiver sensitivity level LDPC codes prove to be quite useful. At the bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) with FIR equalizer will result in optical power saving of 3, 5, 7, 9.5 and 10.5 dB, respectively when compared to the uncoded-unequalized system. LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) also show received optical improvement of 7.5, 6.5, 4 and 2 dB over RS(255,239) code for 500 m of multimode optical fiber transmission.
The experimental results at 15 Gb/s over 500 m of multimode fiber using the setup in Fig. 4 are shown in Fig. 7 where the x- and y-axes represent the received optical power in the hard decision branch and post-FEC BER using the confidence information from the soft decision branch, respectively. Results from Fig. 7 show that if either LDPC(672, 336) or (672, 504) is used, error free transmission (<2 × 10−9) is observed when the received optical power is higher than −10 and −9 dBm, respectively. For LDPC (672, 588) and LDPC(1440, 1344) the best performance achieved is around BER of 10−7 at the received optical power of −6.7 and −5.1 dBm, respectively. Beyond this point no errors are found in the frames captured. Another conclusion derived from Fig. 7 is that RS(255,239) fails to deliver desired performance with BER of 8 × 10−5 at received optical power of −5 dBm and the performance is worse than the original BER of the uncoded received signal below −6 dBm of received optical power. This is a clear indication of the suitability of the 2-bit flash ADC for decoding LDPC codes and equalization. Beyond received optical power of −11.5 dBm the performance degrades for all the coding schemes due to the loss of receiver sensitivity and low optical signal to noise ratio (OSNR) at the photodetector. These performance improvement enables a 10 Gb/s Ethernet SFP + module specified for 300 m at −9 dBm to operate at 15 Gb/s over 500 m at −10.7 dBm of received power with LDPC and equalization.
From Fig. 6 and 7 it is evident the LDPC(672,336) performs better than all other LDPC codes LDPC codes presented in this paper. However, the code has very low rate (50%) and high overhead. The short block codes presented in this paper tend to show error floor around BER of 10-10 and not quite suitable for long haul systems requiring BER of 10-12. But they are a very good choice for short links for their low complexity.
Power dissipation by the soft-decision circuit
The power consumed by the components is given in Table 2 . The overall power consumption for 45 Gb/s soft and hard-decision branches is approximately 1.39 W. For 32 GS/s flash type ADC operation the total power consumption is 2.71 W (with 49% of the power consumed by the 1:2 selector). The power consumption is low compared to previous work by  and [12, 13] which consumed 5 W at 12.5 GS/s and 14 W at 32 GS/s (with additional phase-locked clock recovery circuit), respectively.
The soft-decision circuit can be scaled to 45 GSamples/s by replacing the 32 GS/s 1:2 selector with higher bandwidth ones, i.e. 45 Gb/s 1:4 DEMUX HMC848 from Hittite Microwave Corporation . The power consumed by the off-the-shelf components at 45 GS/s is also shown in Table 2. The overall power consumption at 45 GS/s is 4.95 W (72% power consumed by the DEMUX). With the help of an 1:2 interleaver  and two sets of the soft-decision circuit, the proposed front-end can be operated at 90 GS/s with power consumption of 14.9 W. The 90 GS/s ADC can be used for a 4x45 Gb/s coherent optical receiver to deliver two samples per bit to the digital equalizer and phase recovery circuit.
In this paper, a low complexity implementation of a 45 Gb/s soft-decision circuit is proposed for the decoding of low density parity check (LDPC) codes. The soft-decision circuit from off-the-shelf components is experimentally demonstrated and performance is evaluated in terms of post forward error correction (FEC) bit error rate (BER) versus pre-FEC Q-factor. It is found that the net coding gain at 45 Gb/s 7.06 and 9.62 dB for post-FEC BER of 10−7 and 10−12, respectively, for long block length LDPC(32768,26803) code suitable for single-mode transmission links. It is also shown that at a lower bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344), an optical power saving of 3, 5,7, 9.5 and 10.5 dB, respectively, is achieved for a multimode link with a 6-tap finite impulse response (FIR) equalizer. In the proposed front-end, fewer components are required as compared to other soft-decision front-end solution, and potentially consumes less power. The optical front-end consumes 2.71 and 4.95 W at 32 GS/s and 45 GS/s, respectively.
This work was supported in part by the Vanier Canada Graduate Scholarship (CGS), Society of Photographic Instrumentation Engineers (SPIE) Graduate Scholarship in Optics and Photonics and Canada Research Chair (CRC) in Photonic Interconnects programs. The authors would like to thank Hittite Microwave Corporation, Discovery Semiconductors, and CMC Microsystems for their kind contributions to this project.
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