## Abstract

With the evolving technology in CMOS integration, new classes of 2D-imaging detectors have recently become available. In particular, single photon avalanche diode (SPAD) arrays allow detection of single photons at high acquisition rates (≥ 100kfps), which is about two orders of magnitude higher than with currently available cameras. Here we demonstrate the use of a SPAD array for imaging fluorescence correlation spectroscopy (imFCS), a tool to create 2D maps of the dynamics of fluorescent molecules inside living cells. Time-dependent fluorescence fluctuations, due to fluorophores entering and leaving the observed pixels, are evaluated by means of autocorrelation analysis. The multi-*τ* correlation algorithm is an appropriate choice, as it does not rely on the full data set to be held in memory. Thus, this algorithm can be efficiently implemented in custom logic. We describe a new implementation for massively parallel multi-*τ* correlation hardware. Our current implementation can calculate 1024 correlation functions at a resolution of 10*μ*s in real-time and therefore correlate real-time image streams from high speed single photon cameras with thousands of pixels.

© 2012 Optical Society of America

## 1. Introduction

Fluorescence correlation spectroscopy (FCS) [1, 2] is a powerful experimental technique for measuring the dynamics of fluorescently labeled molecules in solution and also inside living cells. It allows one to determine the particle number, the diffusion coefficient, flow speeds and also photophysical and chemical reaction rates (for an overview, see Ref. [3]). In FCS the time trace of the fluorescence intensity fluctuations *I*(*t*) inside a small observation volume (usually around 10^{−15} l = 1*μ*m^{3}) is monitored. The fluctuations originate from particles entering and leaving the focus, or transitions between states having different quantum yields. Faster dynamics of the fluorescing particles also lead to faster fluctuations, which can be quantified by means of a temporal first-order autocorrelation function (ACF):

*T*̃ being the runtime of the entire measurement.

The standard FCS setup uses a confocal microscope in combination with single-photon sensitive detectors to acquire the fluorescence time trace *I*(*t*) from one focal volume. Then the data is fed into a “correlator” (hardware or software component), which estimates the ACF over a certain dynamic range.

Several hard- and software implementations for correlators (especially for the application in confocal FCS and dynamic light scattering) have been proposed. On the one hand, there are custom hardware based approaches (e.g. [4–6]). On the other hand, highly optimized software algorithms have been invented which mostly rely on photon arrival times [7–9], or commercial event counter cards [10,11]. Parallelized implementations of the multi-*τ* algorithm are available also [12,13]. More and more reconfigurable logic chip (FPGA – field programmable gate array) based approaches have been developed [14–19] lately. Most of them can only deal with a limited number of up to 32 input channels. Particularly, the software implementations achieve good (near-realtime) performance only for a very limited number of input channels, if implemented on a standard PC.

In recent years, the availability of fast cameras has triggered the development of different spacially resolved modalities for FCS: these modalities are based on single-spot confocal microscopy [20], multi-spot confocal microscopy [21, 22], line-confocal microscopy [23, 24], spinning-disk microscopy [25], total internal reflection microscopy [26] and selective plane illumination microscopy [27,28]. All these techniques map the diffusion coefficients and other dynamic properties by calculating an ACF for each of potentially many pixels in software. Also the commercially available fast cameras are limited in frame rate to about 1kfps if a substantial number of pixels needs to be measured, although they can achieve frame rates up to 25kfps for single lines (see e.g. [28]).

Here we describe a hardware-based correlation system that can process the data stream from all pixels of an imaging device in real time. We extend the idea of hardware reuse, as presented in Refs. [14, 19], for imaging FCS applications with hundreds of input signals. Our FPGA-based hardware correlator system can calculate 1024 autocorrelation functions in parallel and in real time. The dynamic range of the ACFs is *τ*_{min} ...*τ*_{max} = 10*μ*s...1s. The design could easily be adapted to different kinds of image sensors such as single photon avalanche diode (SPAD) arrays, customized scientific complementary metal oxide semiconductor (sCMOS) or electron multiplying charge-coupled device (EMCCD) cameras.

To overcome the limited temporal resolution of currently available cameras, we use the 32× 32 pixel SPAD array detector *Radhard2* as image sensor, which can be read at frame rates of 100kfps and above (for a detailed description of this sensor, please refer to section 2 and Ref. [29]). Smaller SPAD arrays have already been used for parallelized FCS on multi-focus confocal microscopes [30, 31]. Also a subregion of a SPAD array with the same size, but with very different pixel architecture has been used for FCS [22]. In all those cases the readout was done either using commercial correlator cards for up to four inputs or FPGA-based time-tagged readout of the photon streams that were subsequently processed by software correlators. There are also larger arrays available, for example [32], but with additional circuitry per pixel and a smaller fill factor.

## 2. Radhard2 SPAD array detector

We use a *Radhard2* single photon avalanche diode array with 32 × 32 pixels as detector for our experiments [29]. The pixels are 30 × 30*μ*m^{2} of which only about 1.4% is active area (circular SPAD with 4*μ*m diameter). The photon detection probability is ≈ 30% at a wavelength of 500nm. At room temperature the dark count rate is approximately 140Hz. After-pulsing probability is negligible at the used integration time of Δ*t*_{frame} = 10*μ*s [33]. The pixels are row addressable and the readout of an entire frame can be done in 2.66*μ*s. The design of the detector also allows the readout of subregions at higher speeds, e.g. a single line every 2.66*μ*s/32 = 83ns. Frames read from the sensor contain 1bit of information per pixel (no photon or at least one photon in the last Δ*t*_{frame}).

## 3. Multi-*τ* hardware correlators

A hardware correlator estimates the ACF in Eq. (1) from a finite sequence of intensity measurements

*T*and the integration time

*τ*

_{min}for one sample. When discretizing Eq. (1) with this intensity sequence, care has to be taken not to bias the normalization $1/{\u3008I\u3009}_{t}^{2}$. A viable choice is the “symmetric normalization” introduced in Ref. [34]:

*τ*∈ ℕ (in units of

_{k}*τ*

_{min}, so

*τ*=

*τ*·

_{k}*τ*

_{min}). When the full sequence {

*I*}

_{n}

_{n}_{=0...}

_{T}_{−1}is available after the measurement, Eq. (3) may be evaluated directly for an arbitrary (also logarithmically spaced) set of lags

*τ*in software. This gives an unbiased estimation of the ACF (“direct correlation”). To implement our hardware correlator, we use the multi-

_{k}*τ*scheme introduced in Reference [35], which is also illustrated and compared to a linear implementation in Fig. 1. For the special case of linearly spaced lags

*τ*=

_{k}*k*, a simple hardware implementation exists, which is shown in Fig. 1(a). Each of the Δ

*τ*-blocks represents a delay of Δ

*τ*=

*τ*

_{min}, which can be implemented using a flip-flop [5] clocked with a frequency of 1/

*τ*

_{min}. Thus, in the final design the series of delay elements are structured as a shift register. After

*n*time-steps the input

*I*

_{n}_{−}

*has propagated to the*

_{k}*k*-th delay element (signal ${J}_{n-k}^{l}$ in Fig. 1(a)), whereas the “undelayed signal” or “global signal” ( ${J}_{n}^{g}$ in Fig. 1(a)) carries the current input

*I*. So the

_{n}*k*-th channel accumulates ${J}_{n-k}^{l}\cdot {J}_{n}^{g}={I}_{n-k}\cdot {I}_{n}$ which is

*G*(see Eq. (3)). For the normalization additional components that accumulate the input signal

_{k}*I*and

_{n}*I*

_{n}_{−}

*at different lags*

_{k}*k*(usually called monitor channels,

*M*

_{0}and

*M*in Eq. (3)) are implemented.

_{k}The multi-*τ* scheme uses a set of *S* of these linear correlator blocks (Fig. 1(b,c)), with *s* = 0,...,*S* − 1. The input samples *I _{s,n}* (

*n*is the same index as in Eq. (2)) are summed over increasingly long periods Δ

*n*=

*m*, with

^{s}*m*= 2 being the factor between the delay times of two subsequent blocks:

*I*

_{0}

*=*

_{,n}*I*.

_{n}Each of the linear correlators estimates the ACF at *P* linearly spaced lags

*p*= 0...

*P*− 1.

In summary, this results in a quasi-logarithmic spacing of estimates *ĝ*_{sym,multi-}* _{τ}* (

*τ*). The advantage of this multi-

_{s,p}*τ*scheme is its simple implementation in hardware and a large dynamic time range with a reasonable number of channels. Its disadvantage is a systematic error introduced by averaging: As shown in Ref. [36] the estimator

*ĝ*

_{sym,multi-}

*(*

_{τ}*τ*) equals the ideal correlation function

_{s,p}*g*(

*τ*·

_{s,p}*τ*

_{min}) (see Eq. (3)) convolved with a triangular kernel with width

*m*:

^{s}*τ*, Δ

*τ*) = Δ

*τ*−

*|τ|*for |

*τ*| < Δ

*τ*and Λ(

*τ*, Δ

*τ*) = 0 for |

*τ*| ≥ Δ

*τ*, is the triangular shaped kernel.

## 4. Hardware design

Here we describe a scheme to reuse the available hardware efficiently to accommodate up to 1024 input channels. We employed a low-level hardware description language (VHDL – very high speed hardware description language) to gain speed and flexibility. This enables us to fine-tune many parameters of the final design, e.g. operational speed, memory usage, logic resource consumption and routing between logic cells.

#### 4.1. Single-pixel correlator

As shown in Fig. 1, a typical correlator is made up from channels, each corresponding to a certain lag time, and consists of a multiplier, an accumulator and a delay element.

The idea of our implementation is to use one single channel circuit to calculate all channels within one multi-*τ* correlator. This is possible by serial processing of the lag time channels, since the hardware in each channel is identical.

The basic arithmetic operation of one channel is to multiply and accumulate (MAC). Therefore we can map its functionality onto a MAC unit which can be found on most FPGA architectures and which is considerably faster than using generic FPGA logic cells. Only about 100 of these can be found on typical FPGAs, precluding any approach with blocks consisting of several lag channels.

As only one circuit is used to process all channels, we use an internal memory block (block random access memory, BRAM) to store their state (i.e., the content of the accumulator and the delayed signal). We implement this circuit by decomposing it into five steps:

accumulator and delayed value of a channel from memory**L**oadfor memory access to complete**W**aitdelayed with global signal**M**ultiplymultiplication result to channel’s accumulator**A**ddcounter and new delayed value to memory**S**tore

From one block to the next the delay time is doubled (*m* = 2) in the multi-*τ* scheme, making the input data rate of block *s*+1 half that of block *s*. Hence we need to execute each block only half as often as its predecessor. Thus, a complete multi-*τ* correlator can be executed in only twice the run-time Δ*t*_{lin} of a single linear correlator block:

*t*

_{lin}is at most half the integration time

*τ*

_{min}of the input signal

*I*.

_{n}A scheduler guarantees that a linear correlator block *s* is only executed after its predecessor *s* − 1 has been executed twice. A counter *c* = 0, 1,... is incremented with every execution of any linear correlator block. The scheduler uses the following relations to determine which linear correlator block *s* has to be executed at a given counter value *c* (details see appendix):

*c*values from 0 to 31. In the binary representation of

*c*for a linear correlator block

*s*patterns are evident that can be used to implement the scheduler efficiently. As shown in Table 2 (for

*S*= 8 linear correlators), correlator block

*s*= 0 is executed whenever the last bit of

*c*is 0

_{b}, correlator

*s*= 1 is executed when the last two bits are 11

_{b}and so forth. This scheme uses only simple comparison operations.

Between two consecutive blocks *s* − 1 and *s*, adder circuitry is inserted to sum up two subsequent input signal values *I _{s}*

_{−1,}

_{n}_{−1}and

*I*

_{s}_{−1,}

*. This is done for both the delayed/local as well as the undelayed/global signal, while they are processed in the pipeline.*

_{n}The linear correlator as implemented here, together with its scheduler and the summation logic, is called correlation processing element (CorrPE). All channel data and intermediate summation results, the so-called pixel context, are stored in a dual-port BRAM which is associated with the CorrPE.

#### 4.2. Multi-pixel correlator

The CorrPE described above is much faster than required to calculate the ACF for a single pixel in the SPAD array. Hence, we can reuse a single CorrPE for multiple pixels by switching between pixel contexts. This “pixel scheduler” uses a double-buffering strategy. While a CorrPE operates on the current context, the previous context is exchanged with the next context to be processed. The pixel contexts are stored in external background memory (SRAM), because they exceed the capacity of the internal memory. In Fig. 3 we illustrate how we reuse one CorrPE for several pixels in comparison to a naïve implementation using one CorrPE per pixel.

In addition to the channel data, the cycle counter *c* and an accumulator for the local and the global input signals have to be saved. The latter are used for normalization and cross-correlation.

A single CorrPE is used to process an entire column (ACFs of *n _{y}* = 32 pixels) of our SPAD array. To handle the full

*n*×

_{x}*n*array of pixels, we instantiate

_{y}*n*= 32 CorrPEs in parallel. An overview of this scheme is shown in Fig. 4. A “data acquisition” circuit communicates with the SPAD array and provides the image data for the correlators. As the image data is streamed out row by row, and each of the

_{x}*n*CorrPEs is only processing data from one specific context (i.e. a specific row), the remaining pixels have to be buffered row wise in 32 FIFOs (first-in first-out memory buffer) localized in external RAM.

_{x}In addition, our design contains two USB 2.0 interfaces. One is used to send the raw data stream from the SPAD array to the computer, which allows further data processing. We also use these raw data to verify our correlator design. Via the second interface, intermediate and final results from the correlators are transferred to the host computer. The intermediate results allow implementing a live view of the ongoing calculation of the ACFs.

#### 4.3. ACF normalization

The intensity values in the denominator of Eq. (3) are typically obtained from *monitor channels M*_{τk}, which accumulate the total photon count at a given lag time *τ _{k}*. In contrast to other implementations, we use only one monitor

*M*

_{0}(input signal accumulator) per multi-

*τ*correlator. Symmetric normalization (see also Eq. (3)) yields the following:

*T*samples, the number of samples that have propagated through the correlator to a distinct channel (

*s*,

*p*) is

*T*−

*τ*. Under the assumption that

_{s,p}*I*is a stationary random process and that

_{n}*T*>

*τ*, the per-channel monitors

_{s,p}*M*

_{τs,p}can be estimated in the following manner: This normalization and model fitting is done on the host computer, since floating-point arithmetic cannot be implemented efficiently on an FPGA. Although the correlation on the FPGA and the normalization on the host computer can easily be done in real time, the fits in most cases cannot. Usually a single curve fit takes tens of milliseconds, thus fitting all 1024 ACFs would amount to ≥ 10s additional computing time; but this still allows to display fit parameter maps (images) within an acceptably short delay. In current imaging FCS software systems [37] the data is loaded and correlated on the host computer, which for a measurement of typically 10s takes a couple of minutes for 1024 pixels at the frame rate of our sensor.

To show that the estimation in Eq. (10) yields good results, we simulated different correlator types in software. The results for a direct estimation of the ACF using Eq. (3) (green), a multi-*τ* correlator with a monitor channel per lag (blue) and our estimation (magenta) can be seen in Fig. 5, where the data in (a) and (b) were obtained by correlating the input signal *I*(*t*) = 1 + sin(2*πt*/(1.51 · 10^{−4})) for which the exact ACF is known to be *g*^{(theoretical)}(*τ*) = 1 + cos(2*πτ*/(1.51·10^{−4})) (time *t* and lags *τ* are unit free). The data in Fig. 5(c) was created by simulating a *T*_{sim} = 1s long FCS experiment with one diffusing species [38]. It was computed with our FCS simulation software described in Ref. [39]. Further details on the simulation code are shown in the appendix.

For short lags the estimated ACFs resemble the theoretical curves quite well. Multi-*τ* correlators have an increased absolute error for longer lags, which is due to the averaging described in Eq. (6). This can be seen especially in the case of the sine wave signal. The multi-*τ* estimates can still be used for FCS experiments, as here the ACFs usually decay to 1 (white noise) for large lag times, and thus the systematic error drops to zero again (for a detailed discussion of this, see e.g. Ref. [36]). For *τ* ≳ *T*_{sim}/10, multi-*τ* correlators show additional systematic deviations from the theoretical curve and from the direct estimation, because the channels are not averaged over sufficiently many samples to yield reliable results. Here the multi-*τ* implementation with multiple monitor channels performs better due to the better estimation of the normalization factor *M*_{τs,p}.

#### 4.4. Crosscorrelation (CCF)

Our design can also calculate cross-correlation:

*I*

^{(}

^{x}^{)}(

*t*) and

*I*

^{(}

^{y}^{)}(

*t*) at the local

*J*

^{(l)}and global

*J*

^{(g)}inputs of the CorrPE (see Fig. 1 where both signals are tied to

*I*(

*t*) for ACF calculation). This changes the multi-

*τ*estimator Eq. (9) to:

*M*

_{0}=

*M*

^{(}

^{g}^{)}=

*M*

^{(}

^{l}^{)}.

## 5. Performance & implementation details

The complete design is implemented in two Virtex-II Pro FPGAs (XC2VP40, Xilinx, http://www.xilinx.com/, San Jose, USA), on a LASP development board [40]. The first FPGA is used for data acquisition and line reordering, while the other one is used to implement the correlators. The total resource consumption within the second FPGA is around 40%. Using this hardware platform, there are currently *P* = 8 channels within each of the *S* = 14 linear correlator blocks.

In Eq. (7) we showed that the complete multi-*τ* correlator can be executed within twice the time needed for the first linear correlator block, so we devote half of the execution time to the first linear correlator and the rest to the remaining blocks. Therefore a new input sample can be accepted only once every 2Δ*t*_{lin}. Here Δ*t*_{lin} = 2*P* + 3cycles is the time needed to process a new input sample *I _{n}* in the first linear correlator block. The 3 additional cycles are used for data hand over to the next block.

The CorrPEs run with a clock frequency of 144MHz, which corresponds to an execution time of 264ns = 2Δ*t*_{lin} for a single input signal. This is the minimum timespan between two subsequent samples, if no pixel multiplexing is used. Hence, our current FPGA platform can calculate 32 different ACFs or CCFs with a minimum lag time of 264ns, which is comparable to the 100ns designs presented in Ref. [14] and more recently in Ref. [19]. Trading time resolution for more correlation functions, we can process all 1024 pixels of the SPAD array at a frame rate of 100kfps in real time or regions of interest with < 32 lines with even higher frame rates.

To estimate the memory consumption of our design, we first look at the pixel context, which consists of 128 words of 64 bits each. Table 3 shows a detailed memory layout. Sixteen of the upper 32bits of the raw accumulators store the current value of the delay registers
${J}_{s,p}^{(l)}$. The lower 32bits contain the accumulator *G*_{τs,p}. The monitor channels are 32bits each. Data handover between consecutive blocks (accumulated local and global signals) is done via 16bit-wide memory areas, which is sufficient for *S* ≤ 16. Since in the later linear correlators the accumulated input signals *I _{s,n}* are multiplied, the sums

*G*

_{τs,p}and also the

*I*can get relatively large and may not fit in the 32bit memory locations available. However, due to constant streaming of intermediate results to the host computer, counter overflows can be detected and corrected.

_{s,n}For our 32 × 32 pixel SPAD array the pixel contexts are stored in 32 · 32 · 128 · 64bits = 512KBytes of external SRAM. A second SRAM stores the 256KBytes used for the FIFOs (2048 entries each) that hold the pixel data until they are processed.

The correlator design is implemented in VHDL (very high speed integrated circuit hardware description language). It can be configured via generics (a VHDL feature). Thus we can reuse our design for different needs (e.g. for different sensor sizes and frame rates). We expect our design to show a significant increase in performance when implemented on newer FPGA generations (e.g. Virtex 5 or Virtex 6 from Xilinx).

## 6. Benchmark experiments

To ensure the functional correctness of the designed correlator, a simulation of the hardware was tested using random input data. The outcome was compared to the results of a software implementation of the multi-*τ* correlator using the same data set. Both yielded exactly the same results. The comparison was also done using real experimental data from the SPAD array. Again, both results were identical.

To demonstrate the functionality of the whole system, we tested the design using the SPAD array to record an LED connected to a sine wave generator set to 2.5kHz. Figure 6 shows the results of this measurement. A fit to the data recovered the chosen frequency.

Finally we tested our system in a custom selective plane illumination microscope (SPIM), comparable to the setup described in [41]. A 491nm beam from a DPSS laser (Calypso, Cobolt AB, Solna, Sweden) is formed into a light sheet of 1.25*μ*m width (1/*e*^{2} half-width) by a Nikon Plan Fluor 10x/NA0.3 microscope objective and cylindrical lens of focal length *f* = 100mm (CKX18-C, Newport Spectra-Physics GmbH, Darmstadt). A Nikon CFI Apo-W NIR 60x/NA1.0 water dipping objective and an achromatic lens with *f* = 100mm (AC254-100-A-ML, Thorlabs GmbH, Dachau, Germany) are used to image the acquired fluorescence onto the SPAD array *Radhard2*, with a 30× magnification. A 500nm long-pass filter (Edge Basic 488LP, Semrock, Rochester, USA) suppresses scattered light by about a factor of 10^{−6} at 491nm. Figure 7 shows the results of an experiment with fluorescent microspheres of diameter 40nm (Invitrogen FluoSpheres YG carboxyl-modified, Life Technologies GmbH, Darmstadt). According to the manufacturer, each bead has a brightness which is equivalent to 350 fluorescein molecules. They were dissolved in water (1 : 1000 dilution from stock concentration *c*_{stock} ≈ 2.4*μ*M) and were mounted in a small sample bag made from 25*μ*m thin transparent foil matching the refractive index of water (LUMOX FOLIE 25 M, SARSTEDT AG & Co, Nümbrecht). The sample was illuminated with a laser power of about 2.33mW, as measured behind the projection objective. This power is distributed over the light sheet of height 4mm and center 1/*e*^{2}-width of 2.5*μ*m, which amounts to an intensity in the focus of about 23.3W/cm^{2}.

For each ACF a fit to the standard FCS model function for 3-dimensional free diffusion was perfromed:

*N*is the average particle number inside the focus and

*τ*is the diffusion decay time. The parameter

_{D}*γ*describes the aspect ratio of the Gaussian focus. The (unweighted) fits were performed using a Levenberg-Marquardt least squares fitting routine (lmfit [42], implemented in our FCS data evaluation package QuickFit 3.0. [43]). The model Eq. (12) is justified for a SPAD array and the described SPIM setup, as each SPAD effectively operates as a single pinhole. The longitudinal and lateral size of the point-spread function were measured by scanning beads, embedded in a clear and low-scattering, but stiff gel (0.5% Phytagel, Sigma-Aldrich, Seelze, Germany), through the image plane in respective directions. From this measurement we obtained a lateral 1/

*e*

^{2}half-width of

*w*= (0.5 ± 0.2)

_{xy}*μ*m and longitudinal half-width of

*w*= (0.8 ± 0.1)

_{z}*μ*m and therefore an aspect ratio of about

*γ*= (1.60 ± 0.72), which was fixed in the fits. The lateral and longitudinal widths fit the theoretically expected values for the setup, if the depth-selection due to the pinhole is taken into account. Also we assume a Gaussian detection probability distribution, as usually done in SPIM-FCS [27, 28].

The average diffusion time was estimated from the median of the distribution of all diffusion times (see Fig. 7(e)) to be *τ*_{D} = 10.2ms. From this we can calculate a diffusion coefficient of
$D={w}_{xy}^{2}/\left(4{\tau}_{\text{D}}\right)=\left(6.1\pm 2.5\right)\mu {\text{m}}^{2}/\text{s}$, which compares well to the value of (5.9 ± 1.5)*μ*m^{2}/s measured with confocal FCS for the same sample. Due to the Gaussian nature of the light sheet, its width increases with the distance to the focal line. This leads to an increased number of detected particles *N* at the edges of the field of view (see Fig. 7(f)). The average count rate during the measurement was 〈*I*〉 = 2400Hz (see also Fig. 7(b) and (c)), which is well above the dark count rate (DCR) of the *Radhard2* sensor of about 140Hz [29]. The overall background countrate (including the DCR) was *I*_{background} ≈ 300Hz during the measurement, which leads to a correction of the measured particle number (as shown in Fig. 7) of *N*_{real} = *N*_{measured}/(1 + *I*_{background}/ 〈*I*〉)^{2} = 0.79·*N*_{measured} [44]. Thus from the corrected median particle number of median(*N*_{real}) = 13.0 we get a molecular brightness of about 184Hz/particle, which is about a factor of 530 less than in the measurement on our confocal setup (*NA* = 1.2), where the average excitation intensity in the focus was about a factor of 250 higher than in our SPIM setup. The difference can be explained by the higher NA, quantum efficiency and larger pinhole size of the confocal setup.

In Fig. 8 we compare measurements for particles of different sizes (Invitrogen FluoSpheres YG carboxyl-modified, 40nm and 100nm diameter, also diluted in water). These examples were selected to show the functionality of our correlator and readout system. A more detailed characterization of SPAD arrays for SPIM-FCS applications will be the topic of a follow up publication. Our current SPAD array is limited in its applicability to high intensity samples, due to its small fill factor. We will address this problem with next generation sensors that are equipped with microlenses.

## 7. Conclusion

In this paper we presented the implementation of an FPGA-based multi-*τ* correlator design that can calculate 1024 correlation functions in real time at a minimum lag time of 10*μ*s. To our knowledge this is the largest number of real time multi-*τ* correlators implemented so far in a single device. The minimum lag time of 10*μ*s in our design is longer than that of currently available hardware correlators (e.g. from ALV GmbH, Langen, Germany or correlator.com, Bridgewater, USA and Reference [11]), but those are limited to at most 32 auto-correlators.

Recently, Mocsár et. al. proposed a hardware correlator implementation with four input channels, comparable to commercially available multi-channel correlators (e.g. from ALV GmbH, Langen, Germany) using an FPGA card from National Instruments, with a minimal sampling time of 400ns [19]. That approach reuses a single linear correlator core for different blocks within the multi-*τ* correlation scheme and for the multiplexed processing of all four input signals. Due to the utilization of a high level description of the hardware using the well established LabView software (National Instruments), their system is easy to adapt to different experimental requirements even for non-experts. But this approach also limits the overall performance in terms of resource consumption and speed of execution. Jakob et. al. proposed to use a single multiply-accumulate cell (MAC), to calculate all correlation channels in serial manner [14], the so called “virtual correlator architecture”. Our design further extends and optimizes both of these hardware reuse schemes: Only a single MAC per correlator is used, which allows us to implement 32 parallel correlators within a single Virtex-2 FPGA. These can then process up to 1024 pixels or input signals, using an advanced multiplexing scheme.

We use our design to correlate the output of a single-photon avalanche diode (SPAD) array used as image sensor in a selective plane illumination microscope (SPIM). This combination allows us to perform imaging fluorescence correlation spectroscopy at the 10*μ*s time scale, which covers the range of motion of small molecules in solution and living cells. We presented several benchmark experiments that show the applicability and functionality of our correlator system. The low photon detection probability due to the small fill factor of our SPAD array will be addressed with next-generation sensors equipped with microlenses.

Our correlator design is flexible and extensible: besides estimating temporal autocorrelation functions, also cross-correlation functions between different pixels or multiple colors (using spectrally resolved detectors) can be calculated. To achieve a larger dynamic range (e.g. for long measurements of *T*̃ ≫ 1s) it is possible to output the accumulated global and delayed values after the last block. As the data rate is reduced by a factor of 2^{14}, then the correlation can easily be processed on the host computer.

The entire hardware correlator is limited to process input values at a rate of 1024·100kHz = 102.4MHz. Hence, if the whole array is read, we can achieve a minimal lag time of 10*μ*s. For a region of interest containing 64 pixels (2 lines), a frame rate of 102.4MHz/64 = 1.6MHz and therefore a minimal lag time of *τ*_{min} = 0.625*μ*s can be achieved. As our current implementation accepts up to 16bit wide inputs, we can overcome the clipping due to the one bit counters within our sensor: The data acquisition logic will be extended to accumulate consecutive frames. A valid choice are 2bit counters, that allow the sum of three subsequent images. This results in a possible full frame integration time of 3.33*μ*s, which is slightly above the sensor’s limit of (2.66*μ*s). Newer FPGAs in combination with next-generation sensors, will allow us to increase the processing speed even further.

## Acknowledgments

The project was supported by a NUS-BW (National University of Singapore / Baden-Württemberg) joint grant to J.L., a doctoral fellowship of the Helmholtz International Graduate School for Cancer Research to J.B., a doctoral fellowship of the Heidelberg Graduate School of Mathematical and Computational Methods for the Sciences to J.W.K. We thank Xilinx, San Jose, USA for donating the FPGAs on the LASP development board. G.V. receives support by the German-Hungarian program for the exchange of researchers by the German Academic Exchange Service and the Hungarian Scholarship Board (MÖB-47-1/2010) OTKA K77600 and TAMOP 4.2.1/B-09/1/KONV-2010-007.

## References and links

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**43. **QuickFit 3.0 can be downloaded free of charge from http://www.dkfz.de/Macromol/quickfit/. In addition to the fitting capabilities, it also contains software implementations of the correlators described in here.

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