We study the electro optical properties of a Metal-Nitride-Oxide-Silicon (MNOS) stack for a use in CMOS compatible plasmonic active devices. We show that the insertion of an ultrathin stoichiometric Si3N4 layer in a MOS stack lead to an increase in the electrical reliability of a copper gate MNOS capacitance from 50 to 95% thanks to a diffusion barrier effect, while preserving the low optical losses brought by the use of copper as the plasmon supporting metal. An experimental investigation is undertaken at a wafer scale using some CMOS standard processes of the LETI foundry. Optical transmission measurments conducted in a MNOS channel waveguide configuration coupled to standard silicon photonics circuitry confirms the very low optical losses (0.39 dB.μm−1), in good agreement with predictions using ellipsometric optical constants of Cu.
© 2012 Optical Society of America
The Metal-Oxide-Semiconductor (MOS) structure is a ubiquitous key building block in the Si-based VLSI electronics industry. Until recently, its lower dimension limit has scaled down according to Moore’s law, leading to an increase in both the power dissipation and the circuit delay of electrical interconnections. Using optical technology could offer a higher bandwidth and reduced power consumption, provided that it can be integrated within a CMOS environment . However, due to the diffraction limit of light at telecommunication wavelengths and the low electro-optical effects of silicon, optical components are generally much larger than their electronic counterparts. This could limit the impact of a chip scale integration of optics. One route to fill the size mismatch is to use metals to support optical modes in optical components. Indeed, surface plasmon (SP) modes, which exist at metal surfaces, allow light confinement below the diffraction limit .
The MOS structure has attractive plasmonic properties, as the incorporation of the oxide close to the metal interface creates a reduced dimension channel for guiding plasmons , whose electric field is greatly enhanced. Amongst numerous possible plasmonic components, the use of MOS plasmon waveguide (PWG) geometry, where the metal layer is also used as electrodes, has been proposed by several teams to achieve an efficient and compact electro-optical control of optical signal [4–6]. It is well recognized that plasmon device performance critically depends on the control over the optical losses of the plasmon modes. This is determined by the choice of metal(which is often chosen amongst noble metals), the fabrication procedure [7–9], and the nature of nearby materials. Although active plasmonic devices have been improved from the optical viewpoint, no data have been reported on the issue of their electrical reliability, despite the fact that noble metals are well known contaminants which affect the operation of MOS based devices.
In this article, we validate a plasmonic MNOS (Metal-Nitride-Oxide-Silicon) waveguide from both the low optical loss and electrical reliability point of view, in the perspective of integrated fabrication within a CMOS foundry. The careful choice of materials for the plasmonic metal (Cu) and the interfacial layers is discussed. An electrical reliability issue raised by this metal choice is solved by the insertion of an ultrathin nitride diffusion barrier layer between the gate metal and the oxide. An experimental investigation of this MNOS stack is performed by monitoring both electrical breakdown under voltage stress of that capacitance, and optical transmission experiments through CMOS integrated MNOS PWGs.
2. PWG metal choice
Plasmonic losses are highly dependent on the electric field penetration in the metal, therefore the nature and crystalline quality of the latter are critical technological issues. For this reason, several proposed active and passive plasmonic devices [4, 10–12] use metals such as Ag and Au. However, these materials are not a good choice for a fabrication on a silicon CMOS platform, as they are well known contaminants of MOS devices. Conversely, metals such as Al and Cu are widely used in CMOS foundries, but have been much less studied for plasmon devices [6, 9, 13]. Figure 1 shows the propagation losses of a plasmon propagating at a metal-air interface, as a function of free space wavelength, for both Al and Cu. It was calculated by using the formula , where αSP is the propagation loss (in dB/μm), LSP the propagation length of the plasmon mode, ε the dielectric constant of the metal, and λ0 the free space wavelength. For the calculation, we used the dielectric constant of copper which we measured by ellipsometry , or the dielectric constant of aluminium given by Palik . It has recently been demonstrated  that the optical losses of plasmon propagating at the surface of Cu layers prepared in CMOS foundries was low and in agreement with the ellispometry results. From this simple comparison, we conclude that copper is the best choice for plasmonic devices in terms of optical losses. It is also technologically relevant, as Al has been progressively replaced by Cu in nowadays electrical interconnects . Cu is therefore the most promising metal for the integration of plasmon devices in a CMOS environment, and will be considered below as a metallization of the MOS waveguide.
3. Diffusion barrier choice
The use of Cu for CMOS interconnects has led to the development of efficient diffusion barriers, so that electronics devices can be connected without detrimental effects on the fabrication yield, and they will not suffer from Cu defect related minority carrier generation in neighboring Si regions (low noise current), or from a high leakage current through the MOS insulating barrier or electrostatic breakdown during operation (high reliability) . Due to the optical loss issue, integration of Cu within a MOS plasmonic waveguide requires a diffusion barrier that is transparent to photons. We discuss in this section the choice of such a barrier with the help of a calculations of the complex propagation index of the fundamental plasmonic mode in the canonical case of a MOS stack consisting of Cu/diffusion barrier (5 nm)/SiO2 (10 nm)/Si (180 nm)/SiO2 (substrate) in planar geometry (Table 1). We used Lumerical mode solver and optical constants from Palik  at 1.55 μm, except for those of copper . The most widespread Cu diffusion barriers used for electrical interconnects are currently made of the following materials: Ti, TiN, Ta, TaN, W, Pd [17–19]. These highly conductive and low thickness diffusion barriers fulfill the needs of electronics applications. However they are optically very lossy, and are therefore, not suited for CMOS plasmonic devices. We calculated (Table 1) that the plasmonic mode losses increase up to 15 times compared to the barrierless case. Ta induces lower optical losses than the other materials, the plasmonic mode losses are increased by a factor of only 5, but its barrier effect is lower than for the other materials, i.e requiring more thickness than considered in Table 1 to reach the same level of reliability. The electrical interconnect literature also contains alternative insulating materials, including silicon nitrides ( [20–22]), as diffusion barriers. For example, T.C. Wang et al  investigated 50 nm thick SiN, SiCN and SiCO layers deposited by PECVD as a Cu diffusion barrier. In particular, SiN showed a good diffusion-barrier performance as well as good adhesion with copper. In those previous works, only non stoichiometric nitride are considered because of their limited thermal budget used for back end processes. Our motivation is different, as we need the thinnest possible dielectric diffusion barrier, which will be inserted at the core of a front end MOS device. We recall here that the operating voltage and the energy consumption scale with the thickness of the insulating barrier, at accumulation conditions . Therefore we propose to use stoichiometric Si3N4, which is available in front end CMOS processes. Note that Si3N4 should not be used alone as a gate dielectric as its interface with Si remains worse than the Si/SiO2 interface in terms of density of interface traps [24, 25]. We are therefore suggest a hybrid Metal Nitride-Oxide-Silicon (MNOS) stack for active CMOS plasmonics. This stack with highly doped silicon as a metal has already been extensively studied in microelectronics for highly reliable and aggressively scaled transistors . However, the reliability of such a stack was never investigated with Cu as the gate metal, as required for CMOS plasmonics devices.
4. Cu based MNOS capacitor electrical reliability
In order to validate the use of very thin Si3N4 as a diffusion barrier for copper, we fabricated copper gate MNOS and MOS capacitors on 200 mm silicon wafers on the Leti fabrication line. The silicon wafers are p-doped with boron at 4 × 1018 cm−3 (Fig. 4(a)). A damascene patterning technique  was used in order to fabricate the metal gate electrode of the capacitors. An 800 nm thick thermal oxide was first deposited on the silicon wafers (Fig. 4(b)). A cavity was subsequently drilled into the oxide layer by a lithography step followed by dry and wet etching steps (Fig. 4(c)). Wet etching allows cleaning of the Si interface before the fabrication of the gate dielectric stack. After etching, a 10 nm thermal oxide layer was formed by thermal annealing (Fig. 4(d)). Except for reference purposes, wafers were then submitted to a deposition via LPCVD of a stoichiometric Si3N4 layer on top of the oxide (Fig. 4(e)). A copper layer was then deposited by a combination of the PVD and Electro Chemical Deposition (ECD) and polished by Chemical Mechanical Polishing (CMP) . Finally, an Al contact was fabricated on top of copper electrode, followed by thermal stressing at 400 °C (Fig. 4(f)) to simulate the typical thermal budget of a backend process. An investigation of the electrical behavior of such capacitors allows the study of the influence of both the Cu and the silicon nitride on the device performance. C-V measurements were automatically performed using an HP4284 impedance analyser meter at room temperature and a frequency of 100 kHz with an AC voltage of 40 mV in addition to the DC biasing of the device in steps of 0.01 V. Figure 4 shows a typical example of the C-V characteristics of a MOS and a MNOS stack. Both the accumulation and the depletion regimes can be distinguished. The inversion regime is not observed at positive voltages because the voltage sweep frequency is too high to allow the diffusion of minority carriers. These C-V experimental curves were well fitted using an equilibrium capacitance model involving Poisson equation and quantum mechanical corrections , allowing the extraction of the equivalent oxide thickness (EOT) and flat band voltage Vfb (Table 2). Note that the inversion regime is observed in the simulation due to the assumption of equilibrium. The EOT for both gate stacks are in full agreement with the dielectric constant of the insulators used  and measured thicknesses, owning to the quantum corrections of the C-V model. No hysteresis of the C-V curve is observed, indicating that no slow trapping of charge occurs in the silicon nitride and/or in the oxide barrier. However a negative voltage shift of the flat band voltage is observed after the introduction of the nitride layer in the stack, which is commonly attributed to the increased negative fixed charge contained in the silicon nitride layer .
Copper impacts mainly the reliability of the MOS capacitance. This effect is conveniently assessed by the measurement of the electric field at breakdown, using a conventional Linear Ramp Voltage Stress (LRVS) technique with a voltage ramp rate of 0.5 V.s−1, the criterion of break down being chosen at a critical gate current of 0.1 A.cm−2. Figure 4(a) shows the Weibull plot of the fabricated capacitors (surface of 10000 μm2) versus the equivalent oxide field to break down ((Vg − Vfb)/EOT), where the EOT and Vfb are extracted from the C-V fit. MOS Capacitors exhibit extrinsic break down characteristics, with early failure behavior (E<1 MV.cm−1) occurring for 40% of the devices. Conversely, 95% of the MNOS capacitors using an additional thin stoichiometric Si3N4 layer have a breakdown field higher than 10 MV.cm−1, with no sign of extrinsic behavior. Extrinsic break down failure is commonly associated with point defects inside the insulator , which in our case can originate from the diffusion of Cu within the oxide [33, 34]. We therefore checked this assumption by performing Secondary Ion Mass Spectroscopy (SIMS) on both the oxide and the oxide/nitride barriers (Fig. 4(b)). Samples were prepared on pristine wafer by deposition of the MOS/MNOS stack in an identical way to the preparation of the capacitors. Measurements were performed from the rear side, by locally removing the silicon of the wafer with a TMAH solution. Analysis was performed using a 45 keV O-ion-beam bombardment at an angle of 45°, down to the underlying Cu layer. The Cu concentration profile in the MNOS stack exhibits a one order of magnitude lower Cu concentration in the oxide than in the case of the MOS. This observation is consistent with previous observations from the literature of stoichiometric Si3N4 . The Si3N4 layer therefore leads to a lowering of the concentration of Cu in the barrier, therefore strengthening the resistance of the MOS stack to the electric field. Furthermore, we checked the conduction mechanism of a wide range of our devices by measuring the DC leakage current for low voltages below −5 V. For the investigated structures (MOS and MNOS) we observed an enhaced leakage current in 40% and 10% of the MOS and MNOS devices, respectively, which was attributed to Frenkel-Poole emission. These values are consistent with the population of devices experiencing extrinsic voltage break down failure characteristics (Fig. 4(a)), suggesting that devices with higher defect densities (and so enhanced conduction) are more susceptible to break down.
In conclusion, a MNOS stack can fulfill the requirement for highly electrically reliable structures, owing to efficient copper diffusion barrier induced by the thin Si3N4. This result is consistent with the demands of CMOS technology.
5. Cu based MNOS PWG integration
This MNOS stack is therefore a reliable platform for CMOS integrated fabrication of PWGs that is compatible with silicon photonics circuitry . In the following, we butt-coupled a MNOS PWG to standard channel Si waveguides of 220 nm × 500 nm cross section, in a way similar to . Light was coupled in and out of this Si waveguide using gratings . Fabrication was undertaken on an 8 inche silicon-on-insulator (SOI) platform. The initial wafer consists of a 220 nm Si layer on a 120 nm buried oxide (BOX) (Fig. 5(a)). Coupling gratings of 950 nm period, 70 nm depth and 50 % duty cycle were first dry etched into the top silicon layer, their dimensions being chosen so that the fundamental TM mode of the Si channel waveguide was efficiently coupled at 1.55 μm operation wavelength. The channel silicon waveguides were fabricated by photolithography and etching down to the silicon substrate (Fig. 5(b)). Planar encapsulation of this layer was performed with a conformal 60 nm thick Si3N4 layer and TEOS oxide followed by CMP step (5(c), (e)). The MNOS PWG was fabricated using damascene technique, meaning a cavity is first drilled in the encapsulation until the Si waveguide surface is reached, after which the silicon thickness of the MNOS stack was adjusted to 170 nm by dry etching. The MNOS stack was fabricated using the same fabrication process as the MNOS capacitor described in section 4. The damascene technique appears particularly well suited for high quality PWG fabrication as (i) the patterning of the metal is achieved thanks to well mastered and standard oxide/nitride etching steps, (ii) it prevents the formation of optically absorbing copper oxide at the interface where plasmon modes are propagating , and (iii) it uses a high temperature annealing of the metal which favors high material quality and extremely low optical loss SPP propagation. After encapsulation of the MNOS PWG by nitride and oxide deposition, the wafer was transferred onto a 2 μm oxidized Si carrier wafer by direct bonding, and the Si substrate of the initial SOI wafer was removed by mechanical grinding and chemical etching down to the BOX. In using this method, we anticipate the fabrication of a plasmostor  in a vertically integrated channel configuration. The final cross section of the MNOS PWG is shown in (Fig. 5(d), 5(f)).
6. Cu based MNOS PWG optical transmission
Transmission measurements through the MNOS PWG were performed using a fiber based 1.55 μm laser optical source, whose output was coupled to the TM-polarized mode of the photonic waveguide through grating couplers using monomode fiber. The optical axis of the monomode fiber was fixed at an angle 10° with respect to the surface of the wafer. A multimode fiber was positioned at the output grating and the optical transmission measured through the whole sample using an ANDO AQ2140 optical multimeter. A KARL SUSS automatic wafer probe station was used to switch between samples on the wafer. The data were normalized with the optical transmission of a reference 220 nm × 500 nm silicon waveguide (SiWG) placed close to every group of 34 PWG samples. Wafer scale fabrication allows a large number of devices to be tested. Figure 6(c) displays the normalized transmission of about 1000 PWGs whose silicon thickness is 170 nm and the length LPWG is varied between 2 and 7 μm. For each device length LPWG, the transmitted power is measured for 18 identical PWGs taken at various positions on the wafer.
One indeed observes a decay of the transmission as LPWG is increased. An exponential fit to the experimental data gives propagation losses of 0.39±0.02 dB.μm−1 and an insertion loss of 2.2 dB. These results are close to that of numerical calculations based on the picture of a direct butt coupling of the incoming fundamental mode of the SiWG to the fundamental mode of the PWG. Using the optical constants of copper given in  (0.3+10.8i at 1.55 μm), and Si, SiO2 and Si3N4 from palik, we found, using a modal analysis (Lumerical FDTD) that the fundamental plasmonic mode of the MNOS stack considered here has an effective index of nPWG= 2.5 and losses of 0.31 dB.μm−1. Following direct coupling theory , the expected power transmission between the fundamental SiWG mode of effective index nSiWG= 1.9 and the fundamental mode of the PWG is the product of Fresnel transmission coefficient multiplied by the overlap integral of the corresponding mode fields (Fig. 6(b)) which is calculated as 0.61. According to this simple calculation, we then expect an insertion loss of 4.3 dB. The discrepancies between the experimental and the theoretical results may be attributed to structural imperfections like slightly taperized PWG entrance due to some imperfectly etched edges, or metal surface roughness at the interface with oxide, and finally a possible difference in the optical indexes of the materials with respect to the values used in simulations.
We proposed a MNOS stack for applications in electro-optical plasmonic devices, so that a very low optical losses and reliable operation is achieved. This objective is met thanks to a careful choice of materials, copper as a plasmon supporting metal and stoechiometric silicon nitride as a ultrathin diffusion barrier to the latter, and the use of fully CMOS compatible processes to integrate the MNOS plasmonic waveguide within silicon photonics circuitry. Final reliability is above 95% for a 3 nm thick Si3N4 layer and optical losses as low as 0.4 dB.μm−1 for a 13 nm thick insulator barrier, in agreement with the Cu ellispometric data. These results open the way towards the high performance and low cost fabrication of plasmonic active devices within CMOS foundries.
This work has been supported by CEA internal Programme Transverse Nanoscience, the French National Agency (ANR) through LETI Carnot Funding. We acknowledge the Leti CMOS platform team for assistance in sample fabrication, David Fowler for his careful reading of the manuscript, K. Gilbert for technical contribution regarding the experiment and M. Veillerot and J.P. Barnes for assistance to SIMS measurement.
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