Horizontal metal/insulator/Si/insulator/metal nanoplasmonic slot waveguide (PWG), which is inserted in a conventional Si wire waveguide, is fabricated using the standard Si-CMOS technology. A thin insulator between the metal and the Si core plays a key role: it not only increases the propagation distance as the theoretical prediction, but also prevents metal diffusion and/or metal-Si reaction. Cu-PWGs with the Si core width of ~134–21 nm and ~12-nm-thick SiO2 on each side exhibit a relatively low propagation loss of ~0.37–0.63 dB/µm around the telecommunication wavelength of 1550 nm, which is ~2.6 times smaller than the Al-counterparts. A simple tapered coupler can provide an effective coupling between the PWG and the conventional Si wire waveguide. The coupling efficiency as high as ~0.1–0.4 dB per facet is measured. The PWG allows a sharp bending. The pure bending loss of a Cu-PWG direct 90° bend is measured to be ~0.6–1.0 dB. These results indicate the potential for seamless integration of various functional nanoplasmonic devices in existing Si electronic photonic integrated circuits (Si-EPICs).
©2011 Optical Society of America
Plasmonic devices allowing light confinement below the diffraction limit are expected to play an important role in bridging the dimension mismatch between photonics and electronics in current electronic photonic integrated circuits (EPICs) . Plasmonic waveguide (PWG) guiding the propagating surface plasmon polaritions (SPP) excited at the metal/dielectric interface is an essential component in most functional plasmonic devices. Among various PWG structures proposed and/or demonstrated so far, metal/dielectric/metal (MDM) structure is an attractive candidate because it supports a propagating SPP mode at wavelengths extending from DC to visible and its modal size is solely determined by the physical size of the dielectric slot [2–6]. However, due to the ohmic loss of metal, the propagation distance of the MDM PWGs is typically on the order of several micrometers at frequencies around the telecommunication wavelength of 1550 nm and it decreases with the slot width (hence, the modal size) shrinking . Actually, for all kinds of PWGs, there is a fundamental tradeoff between the light confinement and the propagation distance. To alleviate this tradeoff, on one hand, the propagation distance of PWGs needs to be improved as long as possible while keeping the modal size small enough; and on the other hand, an effective coupler between the PWG and the conventional dielectric or semiconductor-based waveguide needs to be developed so that the PWG will be used to address functional plasmonic devices while the conventional waveguides will be used to transfer the optical signal over a long distance [6, 7].
Theoretically, it was discussed recently that hybrid or metal/multi-insulator/metal PWGs could be superior in some aspects to the conventional MDM PWGs because the modal power is highly concentrated in the low-index dielectric region of the hybrid or metal/multi-insulator/metal PWGs [8–11]. Experimentally, Au or Ag, — which is not a Si complimentary metal-oxide-semiconductor (CMOS) compatible material, is commonly used as the metal and a special process such as electron beam lithography is usually required to fabricate the nanoplasmonic devices [6, 12–15]. However, in terms of practical implementation in the existing Si EPICs, it is highly desired to use the CMOS compatible metal and industry-standard lithographic process. Moreover, PWGs with a Si core (or so called Si-based PWGs) may realize active plasmonic devices (e.g., electro-optic modulator [16, 17]) because the refractive index of Si can be modified by an applied voltage through the free carrier dispersion effect. Considering the first issue for CMOS compatibility, Al or Cu has been used as the metal of PWGs recently [18, 19], however, the performances of Al- and Cu-PWGs have not been thoroughly compared. Considering the second issue for CMOS compatibility, a self-aligned approach was recently reported for the fabrication of nanoscale PWGs, but this approach is only capable of the fabrication of a vertical metal-insulator-Si hybrid photonic-plasmonic waveguide . Instead, a technology developed for the top-down fabrication of nanowire transistors can realize nanoscale Si beams using the industry-standard lithography . Using this technology, fully CMOS-compatible horizontal Al/SiO2/Si/SiO2/Al PWGs with the Si core width of ~136–43 nm were demonstrated on silicon-on-insulator (SOI) platform recently . However, the Al-PWGs exhibit a relatively large propagation loss of ~1.07–1.63 dB/µm (the propagation distance of ~4.1–2.7 µm), limiting their utility in resonators and other interferometric devices. Because the ohmic loss of metal is mainly determined by the imaginary part of metal permittivity  and the imaginary part of Cu permittivity (~-109 + 9.8i) at 1550 nm is much smaller than that of Al (~-232 + 47i) , it is expected that the propagation distance of the horizontal metal-PWGs could be substantially improved by replacing Al with Cu as the metal. The prediction is confirmed both theoretically and experimentally in this paper.
Figure 1 shows schematically the PWG structure studied in this work, similar to the previous report . The PWG with length of LP and width of WP is inserted in a conventional Si wire waveguide with width of WSi through two identical tapered couplers with length of LC. The devices are fabricated using the standard Si CMOS technology on silicon-on-insulator (SOI) substrates and are covered by a thick cladding SiO2 layer (not shown in the figure).
Cu or Al is used as the metal. In the standard Cu process, a thin TaN layer is typically used as the barrier layer between Cu and Si . However, the SPP penetration depth in the metal is only ~26 nm . It implies that the property of SPP excited at the metal/dielectric interface is mainly determined by the metal adjacent the interface. Therefore, the SPP property in the Cu/TaN/Si system will be mainly determined by TaN, rather than Cu. However, TaN is not a good metal for SPP applications because of its relatively large resistivity (hence large ohmic loss) . To avoid this problem, the TaN layer is skipped and Cu (or Al) is directly deposited on the Si or SiO2 surface in our nanoplasmonic waveguides.
The remainder of the paper is organized as follows. Section 2 describes the simulation result of the proposed structure briefly. Section 3 describes the fabrication details and measurement method. In Sections 4, 5, and 6, the measured propagation loss, coupling efficiency, and bending loss are presented and discussed with the simulation results, respectively. Finally, the conclusions are summarized in Section 7.
2. Modeling and simulation
Three-dimensional (3D) finite-difference time-domain (FDTD) from the commercial software FullWAVE/RSOFT  is exploited to simulate the structure shown in Fig. 1. The Si core height keeps 340 nm. An un-uniform grid is set as follows to accurately capture the field change around the thin insulators: x- and y-directions: 10 nm at the bulk and 1 nm near the material interface; z-direction: 20 nm at the bulk and 2 nm near the material interface. The minimum divisions between two interfaces are set to be 5 in all directions. Perfectly matched layer (PML) boundaries are used to attenuate the field without the back reflection. A fundamental transverse electric (TE) continuous-wave light (the electric field is parallel to the x-axis) is launched in the left Si waveguide. The build-in optical parameters of Si, SiO2, Cu, and Al in RSOFT are used. Figures 2(a) and (c) depict the top-view Ex-field distributions at y=0 (the middle of Si core height) in the Cu/Si(50 nm)/Cu and Cu/SiO2(12 nm)/Si(50 nm)/SiO2(12 nm)/Cu PWGs, showing 1550-nm TE light launched in the left 500-nm-wide Si-waveguide is gradually transferred through a 0.5-µm-long tapered coupler into the 2-µm-long PWG and then transferred out to the right 500-nm-wide Si-waveguide through another 0.5-µm-long tapered coupler. The corresponding modal profiles in the Cu/Si/Cu and Cu/SiO2/Cu/SiO2/Cu PWGs are shown in Figs. 2(b) and (d), respectively.
Figure 2 shows that the modal power in the Cu/Si/Cu PWG is concentrated in the Si core region, whereas the modal power in the Cu/SiO2/Cu/SiO2/Cu PWG is concentrated in the sidewall thin SiO2 layers due to the continuity of the electric displacement normal to the Cu/SiO2 and SiO2/Si interfaces. The Al-PWGs exhibit similar behaviors . The real effective modal index (neff) and the propagation loss extracted from the 3D FDTD simulation are 5.04 and 3.35 dB/µm for the Cu/Si(50 nm)/Cu PWG; 2.46 and 0.99 dB/µm for the Cu/SiO2(12 nm)/Si(50 nm)/SiO2(12 nm)/Cu PWG, 4.48 and 4.04 dB/µm for the Al/Si(50 nm)/Al PWG; and 2.24 and 1.53 dB/µm for the Al/SiO2(12 nm)/Si(50 nm)/SiO2(12 nm)/Al PWG, respectively. Firstly, we can see both neff and the propagation loss is significantly decreased by introducing a thin SiO2 layer in the slot of the horizontal PWG, in agreement with the other group’s reports [8–11]. Secondly, the Cu-PWGs exhibit a lower propagation loss than corresponding Al-PWGs, as expected. More simulation results will be discussed with the experimental results in the following sections.
3. Device fabrication and characterization
The devices were fabricated on SOI wafers with a 340-nm-thick top Si layer and a 2-µm-thick buried SiO2 layer. After a 50-nm-thick SiO2 deposition, — which will be used as the hard mask for the subsequent Si etching, the waveguide patterns were defined using 248-nm-DUV lithography. The Si core of PWG, which is inserted in a Si waveguide through two identical tapered couplers, has the length (LP) ranging from 1 to 50 µm and the width (WP) ranging from 160 to 250 nm. The Si waveguide has width (WSi) of 500 nm, total length of ~3 mm, and inverted tapered structures at both facets (for coupling with the fiber). The tapered coupler, which links the Si waveguide and the PWG, has the length (LC) ranging from 0.3 to 2 µm and the width changing linearly from 500 nm at the Si waveguide terminal to WP at the PWG terminal. An identical Si waveguide without the PWG structure is used as the reference waveguide.
A photoresist trimming process was carried out to shrink the critical dimension, as we previously developed for the top-down fabrication of Si nanowire devices . After dry etching the SiO2 hard mask, the photoresist was striped, followed by dipping in a diluted HF solution for a short time to further reduce the critical dimension of the SiO2 patterns. Then, Si was dry etched down to the buried SiO2 layer using the remaining ~40-nm-thick SiO2 layer as the hard mask. Figure 3(a) shows the scanning electron microcopy (SEM) image of the structure after this step. After removing the remaining SiO2 hard mask, a 50-nm-thick SiN layer and a 1-µm-thick SiO2 layer were deposited sequentially. Rectangular windows were then opened by dry etching the deposited SiO2 layer to expose the Si core in the region of PWG and the tapered couplers. The SiN layer is used as the etching stopping layer because of the high etching ratio (~1:20) between SiN and SiO2. Figure 3(b) shows the structure after this step. After wet etching the remaining SiN layer in the windows, the wafers were processed as one of the following four procedures:
- -(1) doing nothing;
- -(2) thermal oxidization in a furnace to grow a 10-nm-thick SiO2;
- -(3) thermal oxidization in a furnace to grow a 5-nm-thick SiO2; and
- -(4) deposition of a 20-nm-thick HfO2 layer in a PVD system.
The wafers were then processed as one of the following two procedures for Cu-PWGs and Al-PWGs, respectively:
- -(1) A 150-nm-thick Cu layer was deposition in a metal PVD system as a seed layer, followed by a 1-µm-thick Cu deposition using a Cu electroplating system. After annealing at 200°C for 30 min, a Cu chemical mechanical polishing (Cu-CMP) process is carried out to remove Cu outside the windows;
- -(2) A 700-nm-thick Al layer was deposited and then patterned to dry etch Al outside the window region, as described in the previous paper .
Finally, a 1-µm-thick upper cladding SiO2 was deposition on all wafers, followed by a deep trench etching (i.e., ~2 µm SiO2 + 50 nm SiN + 2µm SiO2 + ~120 nm Si) and wafer dicing along the deep trenches for the Si waveguide facet preparation, similar to those for the conventional Si waveguide chip fabrication [27, 28]. Figure 3(c) shows the cross sectional transmission electron microscopy (XTEM) image of the final Cu-PWG. The Al-PWG has similar cross section as Fig. 3(c) near the Si core except that Cu is replaced by Al, as shown in the previous paper . In this study, five wafers were fabricated. The fabrication parameters as well as the measured optical properties (see the following Sections 4-6) are summarized in Table 1 .
Figure 4 shows the enlarged XTEM images around the Si core of final Cu-PWGs. The Si core widths at the middle of the height are ~134, ~80, ~50, and ~21 nm, respectively. The height is ~340 nm except that of Fig. 3(d) where the top Si width is reduced to zero and the height is reduced to ~278 nm. The sidewall oxide thickness is ~12 nm at each side and the top oxide thickness is ~10 nm because oxidization rate on the Si (110) surface is faster than on the Si (100) surface . In the case of 5-nm SiO2 oxidization, the final sidewall SiO2 thickness at each side is ~7 nm, and in the case of 20-nm HfO2 deposition, the final sidewall HfO2 thickness at each side is ~7 nm, as observed from the XTEM images shown in the inset of Fig. 7 . Moreover, due to the consumption of Si during oxidation, in the case of 5-nm SiO2 oxidization, the corresponding Si core widths are ~136, ~82, ~52, and ~23 nm, respectively; and in the case of no oxidation, the corresponding Si core widths are ~139, ~85, ~55, and ~26 nm, respectively.
Since the PWG is inserted in a conventional Si waveguide, the waveguides can be measured as a conventional Si waveguide chip [27, 28]. A 1550-nm transverse electric (TE)-polarized light from a tunable laser is coupled into the input silicon waveguide through a lensed polarization maintaining (PM) fiber and the transmitted power coupling out from the output silicon waveguide through another fiber is measured by a power meter. A semi-auto XYZ micrometer piezo-stage was used for perfect alignment to search the maximum output power. To measure the wavelength dependence, an Expo broadband laser source was used as the input light and the output light was scanned by an AQ6317B optical spectrum analyzer.
4. Propagation loss
Figure 5 plots transmitted powers measured from one set of waveguides located on a chip as a function of the PWG length (LP). The coupler length (LC) keeps 1 µm. For the Cu/SiO2/Si/SiO2/Cu PWGs, the transmitted power (in the dBm unit) exhibits a good linearity with LP, from which the propagation loss can be extracted accurately. However, the Cu/Si/Cu PWGs exhibit much smaller transmitted power than that predicted from the FDTD simulation and the transmitted power does not depend on LP linearly. The ~-55-dBm power measured on the Cu/Si/Cu PWGs with LP larger than ~5 µm may come from the weak parasitic optical mode which transports through the bottom SiO2 layer, as we can see from Figs. 2(b) and (d) that there exists a weak Ex(x,y) distribution in the bottom SiO2 layer. The Al/Si/Al PWGs also exhibit much larger propagation loss than the theoretical prediction and it is attributed to the Al/Si alloying and/or reaction at the Al/Si interface, which may cause strong light absorption and/or scattering at the Al/Si interface . For the Cu-PWGs, it may be attributed to the significant Cu diffusion into the Si core during the subsequent SiO2 deposition at ~400°C. It was reported that a metal contamination in a Si waveguide can dramatically increase the propagation loss . This destructive effect will be more significant in meta/Si/metal PWGs because of the power concentration in the Si core, but will be less significant in the metal/SiO2/Si/SiO2/metal PWGs because of the power concentration in the sidewall SiO2 layers (hence less power density in the Si core). Therefore, we can see that the thin interfacial SiO2 layer between metal and Si core plays a key role in the horizontal PWGs because (1) it improves the propagation distance as the theoretical prediction; (2) it prevents the metal/Si reaction or metal diffusion into the Si core; and (3) even if the Si core is metal contaminated, the metal contamination exerts less influence on the propagation loss due to the power concentration in the sidewall SiO2 layers.
Figure 6 depicts the theoretical and experimental propagation losses of Cu/SiO2(12 nm)/Si(WP)/SiO2(12 nm)/Cu and Al/SiO2(12 nm)/Si(WP)/SiO2(12 nm)/Al PWGs as a function of the Si core width, WP. Four sets of Cu-PWGs from different chips were measured. The averaged propagation losses for Cu-PWGs with WP of 134, 80, 50, and 21 nm are 0.37±0.02, 0.48±0.02, 0.57±0.03, and 0.63±0.01 dB/µm, respectively. The corresponding Al-PWGs measured from one set of waveguides have the propagation losses of 0.95±0.01, 1.29±0.02, 1.42±0.05, and 1.72±0.07, respectively. For both Cu- and Al-PWGs, the propagation loss increases monotonically with the Si core width shrinking, in agreement with the well-known fact that a tighter light confinement in PWGs leads to a shorter propagation distance. As expected, the Cu-PWGs exhibit smaller propagation loss than the Al-counterparts both theoretically and experimentally.
For Al-PWGs, the measured propagation losses are close to those obtained from the 3D FDTD simulation, in agreement with the previous result . For Cu-PWGs, to our surprise, the measured propagation losses are much smaller than the theoretical predictions. A specious reason is the mismatch between the ideal rectangular device’s profile used in the simulation and the real device’s geometry as shown in Fig. 4. However, because the same simulation scheme is used and a good agreement between simulation and experiment is obtained for Al-PWGs, this reason may be ruled out. The other possible reason is that the complex permittivity of the deposited Cu in our experiments may differ from that used in simulation (i.e., the build-in Cu parameters in RSOFT) because the optical property of Cu may depend on the deposition details and the Cu permittivity in different database has a different value. However, we have no direct evidence on this. The direct measurement of the optical property of the deposited Cu is out of the scope of this paper. Nevertheless, the experimental low propagation loss of Cu-PWG (~2.6 times smaller than the Al counterparts) is essentially useful for its applications in nanoplasmonic devices, especially in resonators and other interferometric devices.
To reveal the influence of the thin dielectric layer between the metal and the Si core, the Al/SiO2(7 nm)/Si/SiO2(7 nm)/Al and Al/HfO2(7 nm)/Si/HfO2(7 nm)/Al PWGs are measured. For both kinds of PWGs, the measured transmitted power exhibits a good linearity with LP and the extracted propagation losses are close to those predicted from 3D FDTD simulations, as shown in Fig. 7. The experimental result confirms the theoretical prediction that (1) the propagation loss of PWG increases with the sidewall SiO2 width decreasing; and (2) the propagation loss of PWG increases with the refractive index of the sidewall dielectric increasing because HfO2 has a higher refractive index (~1.9) than SiO2 (~1.44).
Figure 8 (a) shows the transmitted power measured from Cu/SiO2(12 nm)/Si(50 nm)/SiO2(12 nm)/Cu PWGs with LP of 1, 5, 10, and 20 µm as a function of wavelength from 1520 to 1620 nm, from which the propagation loss is extracted as a function of wavelength. The results are shown in Fig. 8(b) for Cu-PWGs with WP = 21, 50, 80, and 134 nm, respectively. The simulation result of Cu/SiO2(12 nm)/Si(80 nm)/SiO2(12 nm)/Cu PWG is also shown for comparison. Both the experimental and theoretical propagation loss spectra depend very weakly on wavelength in the c-band (1520–1620 nm). As Fig. 6, the propagation loss of Cu-PWGs obtained from the 3D FDTD simulation is larger than the measured value at any wavelength. The theoretical propagation loss decreases smoothly for ~0.90 dB/µm at 1520 nm to ~0.86 dB/µm at 1620 nm because the real part of Cu permittivity varies from ~-104.5 to ~-119.5 and the imaginary part of Cu permittivity varies from ~9.3 to ~11.1 almost linearly with the wavelength varying from 1520 nm to 1620 nm . The apparent oscillations in the experimental propagation loss spectra are due to the measurement error associated with the experimental setup because the raw measured spectra, as shown in Fig. 8(a), exhibit similar irregular oscillations.
5. Coupling efficiency
Figure 9 depicts the theoretical and experimental coupling losses between the 500-nm-wide Si wire waveguide and the Cu/SiO2(12 nm)/Si(WP)/SiO2(12 nm)/Cu PWG as a function of the tapered coupler length, LC. It is well known that the coupling loss is mainly caused by two sources . One is the reflections both at the Si-waveguide/coupler interface and the coupler/PWG interface, and the other is the propagation loss along the tapered coupler. The reflection loss dominates for the shorter LC coupler and depends on WP. For the extreme case of LC = 0 (i.e., the direct coupling), the 3D FDTD simulation result indicates that the reflection ratio increases from ~20% to ~69% with WP decreasing from 200 nm to 20 nm. The coupling efficiency increases rapidly with LC increasing for various WPs, reaching a maximum of ~-0.2 dB at LC = ~0.3–0.5 µm, and then decreases slowly with LC further increasing due to the increase of the predominant propagation loss along the coupler. The damping of coupling loss with LC can be attributed to the weak Fabry-Perot resonances inside the tapered coupler . The total losses measured from a waveguide with PWG includes: (1) the two coupling losses between the fiber and the Si waveguide; (2) the propagation loss in the Si wire waveguide; (3) two coupling losses between the Si waveguide and the PWG; and (4) the propagation loss in the PWG. The first two contributions can be measured from a reference waveguide without the inserted PWG, and the fourth contribution can be read from Fig. 6. A set of waveguides with LP of 3 µm and LC of 0.3, 0.5, 0.7, 1, and 2 µm, as well as the reference Si waveguide without PWG were measured. The coupling loss per facet through a tapered coupler is experimentally determined as follows: Coupling loss per facet = (the measured transmitted power − propagation loss in dB/µm × 3 − the measured transmitted power of the reference waveguide) / 2
Due to the deviation of identical waveguide and measurement, the coupling loss determined by the above approach has a relatively large error. Therefore, four sets of waveguides are measured and their coupling losses are averaged. The results are shown in Fig. 9 as a function of LC for the Cu-PWGs with various Wps. The coupling loss is ~-0.1 − −0.4 dB/facet for the tapered coupler with LC = 0.5–1 µm and is ~-0.6 − −0.9 dB/facet for the coupler with LC = 0.3 µm, in agreement with the theoretical predictions. On the other hand, the 2-µm-long tapered coupler exhibits a much smaller coupling loss than that obtained from the 3D FDTD simulation, in consistent with the previous observation that the Cu-PWGs have much smaller propagation loss than that obtained from the simulation (Figs. 6 and 8(b)). The high coupling efficiency (91%–98%) and large length tolerance (~0.5–2 µm) of the tapered coupler are of great benefit to the implementation of PWGs in the integrated Si photonics.
Figure 10 shows the wavelength dependence of coupling loss between the 500-nm-wide Si waveguide and the Cu/SiO2(12 nm)/Si(WP)/SiO2(12 nm)/Cu through a 1-µm-long tapered coupler. The coupling loss spectra are extracted from one set of waveguides whereas the data points at 1550 nm are averaged from 4 sets of waveguides. The apparent oscillations in the coupling loss spectra are due to the measurement error, as that in Fig. 8(b). The apparent positive coupling loss at some wavelengths could also be attributed to the measurement error because the coupling loss (~-0.1– −0.4 dB) is smaller than the measurement variation (~1 dB). Despite the relatively large measurement error, we can see that the coupling loss exhibits a weak dependence on wavelength in the c-band, similar to the Al-PWGs . The weak wavelength dependence of both the propagation loss and the coupling efficiency makes the horizontal PWGs is very suitable for the wavelength multiplexing applications.
6. Bending loss
An attractive property of PWG is that it can achieve a sharp bending with low loss . To demonstrate this, a set of bent PWGs are fabricated with the layout shown schematically in Fig. 11(a) . The bent PWG has total length of 3 µm and contains two direct 90° bends. It is inserted in the 500-nm-wide Si wire waveguide through two 1-µm-long tapered couplers. The fabrication of the bent PWGs is exactly the same as the straight PWGs. Figure 11(b) shows the SEM image of one of the Si core of bent PWG structures, and Fig. 11(c) shows the SEM image after the SiO2 window opening (before the metal deposition). The Si core widths of the fabricated bent PWGs are 80, 50, and 21 nm, respectively.
Figure 12 depicts the electric field (Ex) and magnetic field (Hy) distributions obtained from the 3D FDTD simulation for the bent Cu/SiO2(12 nm)/Si(50 nm)/SiO2(12 nm)/Cu PWG launched by 1550 nm TE light at the left Si waveguide, showing the SPP signal can be transferred through the 90° direct bend with a relatively low bending loss of ~-0.4 dB, similar to the other kind of plasmonic waveguides .
The pure bending loss is experimentally deduced by comparing the transmitted powers measured from the bent PWG and the 3-µm-long straight PWG with the same LC as follows:
Bending loss = (transmitted power of the bent PWG − transmitted power of the 3-µm-long straight PWG) / 2.
Figure 13 depicts the measured pure bending loss per 90° direct bend as a function of wavelength for Cu/SiO2(12 nm)/Si(WP)/SiO2(12 nm)/Cu PWGs with WP of 80, 50, and 21 nm, respectively. Despite the relatively large measurement error, the pure bending loss of Cu-PWGs exhibits weak wavelength dependence in the c-band, similar to the Al-PWGs . The averaged pure bending loss of Cu-PWGs is in the range of ~-0.6 − −1.0 dB, slightly larger than that of Al-PWGs (~-0.2 − −0.4 dB ), which may be attributed to the smaller real part of Cu permittivity as compared to that of Al, thus the SPP field penetrates more deep in Cu than that in Al . However, the apparent difference in the Al- and Cu-bent PWGs is smaller than the measurement uncertainty. Measurement on the bent PWGs which contains more direct 90° bends are necessary to extract the pure bending loss accurately.
In summary, horizontal metal/insulator/Si/insulator/metal nanoplasmonic waveguides are fabricated using the standard Si-CMOS technology and are characterized around the telecommunication wavelength of 1550 nm, as listed in Table 1. The Cu-PWGs exhibit a ~2.6 × longer propagation distance and a higher coupling efficiency (~91%–98% per facet) with the Si waveguide than the Al-counterparts, indicating that Cu is superior to Al for the plasmonic applications. A thin insulator layer between the metal and the Si core is a key component in the horizontal PWGs. A thicker insulator or an insulator with a smaller refractive index provides a smaller propagation loss. The PWGs can achieve a sharp bend with low bending loss. A pure bending loss of ~-0.6 − −1.0 dB per direct 90° bend is measured for Cu-PWGs. The optical properties of the horizontal PWGs, namely the propagation loss, the coupling efficiency, and the pure bending loss, depend weakly on wavelength in the c-band. These results pave a way to seamless integration of various functional nanoplasmonic devices in the existing Si EPICs using fully Si-CMOS compatible materials and processes.
This work was supported by Singapore SERC/A*STAR Grant 092-154-0098.
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