A simple, digital signal processing-free, low-cost and robust synchronous clocking technique is proposed and experimentally demonstrated, for the first time, in a 64-QAM-encoded, 11.25Gb/s over 25km SSMF, real-time end-to-end optical OFDM (OOFDM) system using directly modulated DFB laser-based intensity-modulation and direct-detection (IMDD). Detailed experimental investigations show that, in comparison with the common clock approach utilised in previous experimental demonstrations, the proposed clocking technique can be implemented to achieve no system BER performance degradation or optical power budget penalty and more importantly to improve system stability. As a viable synchronous clocking solution for real-time OOFDM transmission, this work is a vital step towards the realisation of practical OOFDM transmission systems and has particular significance for synchronisation of OOFDM multiple access-based passive optical networks where highly accurate synchronisation of all network elements is essential.
©2011 Optical Society of America
It is widely accepted that there is a need to drastically increase the transmission capacity of existing networks to support the rapidly emerging bandwidth-hungry internet services. In particular, access networks are the main network bottlenecks, consequently this is driving the rapidly growing roll out of fiber to the home (FTTH). At present, conventional optical transmission techniques can support high bandwidths needed in the near future, however advanced optical transmission techniques are essential to support the demand for ultra-high bandwidths further into the future. Optical orthogonal frequency division multiplexing (OOFDM) is widely recognised as a strong candidate for a cost-effective, “future-proof” optical transmission technology to enable next generation ultra-high-speed optical networks. Evidence of this is the large number of research groups world-wide undertaking OOFDM research activities. However, most research is based on non-real-time, off-line digital signal processing (DSP). To date, several research groups have demonstrated OOFDM transmission involving real-time DSP in either the transmitter [1,2] or receiver [3,4]. These experiments, however, do not completely eliminate off-line DSP for true end-to-end real-time OOFDM transmission.
To our knowledge, we are the first and only group that has demonstrated a series of end-to-end real-time OOFDM transmission experiments implemented with field programmable gate array (FPGA)-based DSP in both the transmitter and receiver . Our key objectives so far have been to experimentally demonstrate that real-time, high-speed OOFDM transmission can be achieved over realistic transmission distances in both standard single-mode fibre (SSMF)-based access networks  and multi-mode fibre (MMF)-based local area networks , in a cost-effective manner, by utilising off-the-shelf, low-cost optical/electrical components. It has also been shown [5,6] that modern digital semiconductor electronics can perform the computationally intense algorithms, in particular, the fast Fourier transform (FFT) and inverse FFT (IFFT), in real-time with sufficient speed and accuracy required for end-to-end real-time OOFDM transmission, and also that intensity-modulation and direct-detection (IMDD) OOFDM systems can be implemented using low-cost directly-modulated DFB lasers (DMLs) [5,6], vertical cavity surface-emitting lasers (VCSELs)  and reflective semiconductor optical amplifiers (RSOAs) . Furthermore, our experimental results have also shown that, in simple DML/VCSEL-based IMDD transmission systems, digital-to-analogue converters (DACs) and analogue-to-digital converters (ADCs) operating at sampling rates as low as 4GS/s can support signal bit rates as high as 11.25Gb/s over 25km SSMF [5,7] and 500m MMF .
The transmitter and receiver in our previously reported real-time end-to-end OOFDM systems both derived their required clock signals from a common reference clock, as do the OOFDM receiver experiments [3,4]. It is obvious that, in a practical system, the receiver must independently generate a suitable clock. Generally speaking, for any transmission system, there are two distinct receiver clock generation methods: asynchronous and synchronous. In an asynchronously clocked system, the receiver operates with an independent oscillator, and uses the received signal to accurately detect the offset between the transmitter and receiver clocks, the offset effects are then compensated for in the receiver; while in a synchronously clocked system, the receiver extracts a synchronous clock signal from the received signal based on embedded timing information.
For asynchronously clocked OOFDM transmission, sampling clock offset (SCO) and symbol timing offset (STO) may occur, which, if not suitably compensated, degrade the system performance due to the ICI and ISI effects [9,10]. The necessary compensation of the SCO and STO effects inevitably requires additional DSP resources which add extra complexity to the receiver. In addition, depending on the transceiver implementation, individual SCO compensation may be needed for each subcarrier, therefore, DSP resources increase with the number of subcarriers. Real-time asynchronously clocked OOFDM transmission  has been experimentally demonstrated at 11.25Gb/s, which employs DSP to extract timing information directly from the OOFDM signal through detection of any drift in cyclic prefix position, OOFDM symbol realignment then compensates both the SCO and STO effects.
Synchronously clocked OOFDM is free from the SCO and STO effects, assuming fast tracking of any transmitter clock drift, sampling instance errors are only caused by residual jitter of the receiver’s sampling clock. However, extracting timing information directly from the noise-like, analogue, high-speed OOFDM signal is challenging and also requires additional DSP functionality in the receiver.
In [11,12], a simple, DSP-free synchronous clocking technique has been proposed and experimentally demonstrated in a real-time end-to-end IMDD OOFDM system at 11.25Gb/s over 25km SSMF using a DML. In this paper, in-depth investigations of the DSP-free synchronous clocking technique are undertaken in the aforementioned transmission systems in terms of: a) identification of optimum operating conditions for maximisation of the system transmission performance, and b) examination of system performance robustness. It is shown that a high quality receiver clock can be recovered from the received optical signal, and more importantly, that there is no BER degradation or optical power budget penalty compared to the common clock approach. It is also shown that the synchronous clocking technique leads to a significant improvement in system stability.
The work reported here is a vital milestone towards the realisation of practical OOFDM systems. This work also has particular significance for synchronisation of OOFDM multiple access-based passive optical networks (OOFDMA-PONs). An example OOFDMA-PON is illustrated in Fig. 1(a) . For operating the OOFDMA-PON, all network elements must be highly synchronised, this is because OOFDMA divides bandwidth between users using dimensions of both frequency and time : subcarriers provide bandwidth partitioning in the frequency domain and timeslots provide bandwidth partitioning in the time domain. Dynamic bandwidth allocation (DBA) can therefore be performed with a high granularity as represented by the individual “data blocks” in Figs. 1(b,1c). In downstream transmission, the timing for all users can be synchronised due to the common optical line terminal (OLT). Whilst in upstream transmission, clock offset between different optical network units (ONUs) can result in offsets in both the frequency and time domains, thus causing the “data blocks” to merge in both dimensions, as shown in Fig. 1(c). The offsets in the frequency domain destroy orthogonality between subcarriers, resulting in inter-subcarrier leakage; the offsets in the time domain lead to severe merging of timeslots/frames if no mechanism is employed to maintain timeslot/frame alignment. Therefore, it can be far more practical to implement OOFDMA-PONs using synchronously clocked ONUs, because of the following two key reasons: firstly, subcarrier orthogonality is preserved in the upstream, secondly, any timeslot/frame drifts between ONUs are eliminated thus avoiding the need for additional DSP to track and readjust timeslot offsets.
OOFDMA-PONs in Fig. 1(a) can also potentially support multiple time-division-multiplexed (TDM) PON standards , this coexistence of different standards has the advantage that subscribers can be gradually migrated to the higher speed next generation PON standards such as OOFDMA, without changes to the network infrastructure. Backwards compatibility of OOFDMA-PONs and its overlay with existing PON standards is only possible if the entire PON can be synchronised together with inter-timeslot allocation management. The OOFDM synchronisation technique presented in this paper therefore has great potential for drastically simplifying the implementation of OOFDMA-PONs.
2. Principle of synchronous OOFDM clocking technique
The proposed and implemented synchronous clocking technique [11,12], as illustrated in Fig. 2 , overcomes the difficulty of extracting timing information directly from the OOFDM data signal by combining a dedicated electrical timing signal, here referred to as the synchronisation clock, SCLK, with the generated electrical OFDM signal, SOOFDM. In the OOFDM transmitter, SCLK and SOOFDM are summed together electrically to produce a combined signal SCOMB, which is utilised to directly modulate the intensity of an optical laser source. The synchronisation clock is a sine wave at a frequency outside the OFDM signal band. The transmitter requires at least two top level clock signals namely CTXLOGIC and CDAC: CTXLOGIC clocks the transmitter’s digital logic and CDAC is used by the DAC to generate the sampling clock, either directly or indirectly. CTXLOGIC, CDAC and SCLK are all generated from a common reference clock, CREF, as all clocks must be synchronous.
In the transmitter, after being combined with an appropriate DC bias current, the SCOMB signal directly modulates the intensity of an optical laser source to generate an OOFDM signal for transmission. The total bandwidth of the signal SCOMB is much lower than bandwidths of any optical filters or WDM multiplexers/demultiplexers in the optical signal path such that it can pass transparently through the system from transmitter to receiver. After transmission through the optical system, the received intensity-modulated OOFDM signal is directly detected by a photo-detector in the receiver to produce an electrical signal S'COMB. This signal is then split to extract the received OFDM signal, S'OOFDM , by low-pass filtering, and also to extract the received synchronisation clock, S'CLK, by band-pass filtering. S'OOFDM is appropriately amplified and digitised for subsequent DSP to recover the transmitted data following a procedure detailed in . The received, jittered clock signal S'CLK is pre-scaled to reduce its frequency before driving a phase locked loop (PLL) which generates a receiver clock, from which all required receiver clocks can be produced. The PLL can convert the received clock frequency and also provides a high level of jitter suppression such that stable, low jittered clocks are produced to drive the receiver’s electronics. Similar to the transmitter, the receiver also requires two top level clocks CRXLOGIC and CADC: CRXLOGIC is the clock for the receiver’s digital logic and CADC is the clock for the receiver’s ADC. The ADC generates the sampling clock either directly or indirectly from CADC. It should be emphasized that all clocks in the transmitter and receiver, in particular the DAC and ADC sampling clocks, are synchronous and originate from CREF in the transmitter, thus the SCO effect is negligible.
The basic method of transmitting and recovering the synchronisation clock is relatively straightforward. However, applying it to a real-time OOFDM system provides an extremely effective, low complexity, low cost and robust clocking solution which avoids the need for any DSP for receiver clock generation. Although the basic clock transmission principle is relatively simple, the clock must be transmitted independently to the OFDM signal yet as the signals are transmitted simultaneously through the same optical system, careful system design is required to identify optimum operating conditions where the clock and data transmission functions can satisfactorily coexist.
It should be noted that the use of the proposed synchronous clocking technique for both upstream and downstream traffic in OOFDMA-PONs, does not require any additional clocks to be generated, as the additional transmitter and receiver can utilise the available clocks. The clock driving the digital logic can drive both the transmitter and receiver logic, which would most likely be in the same integrated circuit, likewise the DAC/ADC clock can be used to drive both DAC and ADC simultaneously.
2. Real-time OOFDM experimental system setup for synchronous clock recovery
Figure 3 shows the experimental setup for the synchronously clocked real-time OOFDM system. As implementation of the real-time OOFDM data generation/detection has been reported in detail in , this paper focuses particular attention on the implementation and optimisation of the synchronous clocking technique. In the FPGA-based real-time OOFDM transmitter and receiver, 64-QAM encoding/decoding is employed on all 15 subcarriers, giving a raw data rate of 11.25Gb/s. To achieve optimum system performance, the FPGA design uses the same channel estimation, adaptive power loading, live parameter control, symbol alignment and on-line performance analysis functions as described in . Table 1 summarises all the key system parameters and Fig. 3 also indicates all RF amplifier gains and RF filter cut-off frequencies. In comparison to , in the transmitter an RF amplifier is introduced to increase the OFDM signal power from the DAC to compensate the coupler loss and, in combination with electrical attenuators, to maximise the adjustment range of the signal power. In the receiver an RF amplifier is also used before the splitter to compensate its loss. Compared to  a higher gain amplifier is used to amplify S'CLK.
At the transmitter, a frequency synthesiser functions as the master clock source operating at 4GHz with an accuracy of ≤3ppm. This clock is also internally pre-scaled to provide a 100MHz clock for the transmitter FPGA (CTXLOGIC) (100MHz is the OOFDM symbol rate). One 4GHz output from the frequency synthesiser is divided by 2, band-pass filtered and amplified to generate a 2GHz sine wave signal for the 4GS/s DAC (CDAC). The DAC consists of four interleaved converters so the 2GHz clock is further subdivided to 1GHz internally in the DAC. A second 4GHz output is band-pass filtered and variably attenuated to provide the dedicated 4GHz synchronization clock signal (SCLK). The amplitude of SCLK can be adjusted directly with the synthesiser’s output level adjustment and the variable electrical attenuator is also used to extend the adjustment range. The electrical OFDM signal from the DAC (SOOFDM) is amplified, low-pass filtered and variably attenuated before combination with the synchronization clock via a resistive RF coupler. The signal from the coupler (SCOMB) is attenuated and combined via a bias-T with an optimised DC bias current to directly modulate a 10GHz, 1550nm DFB laser. After boosting the DFB output power with an EDFA and optical band-pass filtering to reduce ASE, the optical launch power is set at 6dBm. The 25km SSMF has an 18ps/nm/km chromatic dispersion parameter and a linear loss of 0.2dB/km at 1550 nm.
At the receiver a variable optical attenuator is used to control the received optical power prior to a 12.4GHz linear PIN detector. The electrically amplified output of the PIN (S'COMB) is split by a 2-way resistive RF splitter. One output that feeds the OOFDM receiver is low-pass filtered to remove the clock signal and provide anti-aliasing filtering. Having been amplified and suitably attenuated, the signal (S'OOMDM) is then fed to the differential input of the 4GS/s ADC via a balun. As the received optical power varies, S'OOMDM’s electrical gain is also adjusted accordingly to optimise the signal amplitude at the ADC input. Automatic gain control (AGC) can of course be implemented by measuring the received signal amplitude, and controlling a variable gain amplifier (VGA). The second output is amplified by a high gain amplifier (30dB) and band-pass filtered to extract only the 4GHz synchronisation clock signal (S'CLK). A pre-scaler reduces the clock frequency to 10MHz, which is then low-pass filtered and used as the external reference for a clock synthesizer generating the 2GHz clock for the receiver’s ADC (CADC), this clock is also pre-scaled to generate the 100MHz receiver FPGA clock (CRXLOGIC). In the present system setup, the clock synthesizer in the receiver effectively operates as a PLL, such clock synthesizer can, however, be easily replaced by a low-cost, fixed frequency PLL with a 1/20 prescaler.
To configure the system to also operate with the common clock method as used in [5–7], the 10MHz reference output from the transmitter’s clock synthesiser is directly connected to the external reference input of the receiver’s frequency synthesiser. This is illustrated in Fig. 3 where the external reference input is connected to point A to use the recovered clock and to point B to use the common clock. Changing between the recovered clock and the common clock in this way enables a direct comparison of the two clocking methods under exactly the same system setup and operating conditions. The optimum signal clipping ratio and adaptive subcarrier power loading profile  are obtained for the 25km IMDD SSMF system using the common clock configuration and employed for all measurements. This ensures any performance variations observed are only due to the two different clocking methods.
3. Experimental results
3.1 Operation of synchronously clocked real-time OOFDM
The DML-modulated 11.25Gb/s OOFDM signals with the 4GHz synchronisation clock are transmitted simultaneously over an IMDD 25km SSMF system with successful clock and data recovery in the receiver. Figure 4 shows electrical signal waveforms at various points in the system subject to optimum operating conditions identified in Section 3.2. It should be noted that all peak-to-peak signal levels in Fig. 4 include ~20mVpp of internal oscilloscope noise. At the selected operating conditions, the RF signal powers at the bias-T input are approximately −16dBm for the synchronisation clock and −9.6dBm for the OFDM signal, the synchronisation clock power is therefore 6.4dB lower than the power of the OFDM signal. In the optical domain this corresponds to a power difference of 3.2dB. For the previously reported, un-optimised operating conditions , the employed synchronisation clock power is 4dB higher than the OFDM signal. Here the clock signal power is significantly reduced and is now lower than the OFDM signal power as oppose to higher.
Figure 5 shows the electrical spectra of both the transmitted signal SCOMB and received signal S'COMB measured with the same resolution bandwidth (3MHz). The OFDM signal occupies the baseband frequency region of <2GHz, above which the residual OFDM signal image due to imperfect low-pass filtering in the transmitter is also observed. However, it is not necessary to insert a capacity-reducing guard band to permit the image signal to be completely removed by filtering. The synchronisation clock is clearly seen at 4GHz and it is evident that there is a frequency spacing of more than 1GHz below the clock to allow easy separation of the OFDM signal and the synchronisation signal by low order filters having a low pass-band width as wide as 1GHz. To reduce the total bandwidth of the signal and thus the bandwidths of required optical and electrical components, the frequency of SCLK can be reduced, this, however, increases the requirements of the band-pass filter in terms of narrower pass-band width and out-of-band blocking. The low-pass filtering used to extract the OFDM signal would similarly require higher performance to ensure any of the synchronisation clock signal remaining after filtering does not generate a significant aliasing product in the OFDM signal region as a result of under-sampling. More importantly, as the frequency spacing between the synchronisation clock and the OFDM signal band reduces, a threshold may be reached where unwanted interferences occur between the synchronisation clock and the OFDM signal band. Future research work is planned to investigate the dependence of the system performance on synchronisation clock frequency.
3.2 Optimisation of synchronously clocked real-time OOFDM system
To examine if any BER performance degradation occurs due to the presence of the synchronisation clock signal, the optimum electrical signal levels of the synchronisation clock and OFDM signals are investigated. Firstly, irrespective of the system BER, the allowed values of the SOOFDM signal level and the SCLK signal level under which synchronisation can be maintained is determined. Synchronisation is defined as the state where the receiver’s clock recovery circuit generates stable clocks locked to the transmitter’s clocks. To detect whether or not the system is synchronised, the 2GHz DAC and ADC clocks are simultaneously fed to an oscilloscope from the test points indicated in Fig. 3, it is then possible to observe when the receiver clocks are stable and locked to the transmitter clock, as shown in Fig. 4(h).
Figure 6 plots both the maximum and minimum clock levels for synchronisation as the OFDM signal level is varied. Both signal levels are measured at the input to the bias-T (50Ω). The effect of laser bias current on the synchronisation range is also illustrated in Fig. 6. As expected, if the bias current is too low (<38.5mA) the clock and OFDM signal ranges over which synchronisation can be achieved are reduced; whilst for a bias current at 40mA a large synchronisation range is achieved. Further increasing the bias currents beyond 40mA (42mA maximum) only has the effect of allowing a small increase in the maximum clock level at higher OFDM signal regions. At the 40mA bias current, the maximum permitted OFDM signal level to maintain synchronisation is approximately 600mVpp. It is worth pointing out that the DFB laser can be driven up to around 900mVpp.
To further explore the impact of the synchronisation clock on the system performance, for the cases of the synchronisation clock present and absent, the system BER is measured as the peak-to-peak (PTP) amplitude of the OFDM signal is varied for the system configuration using the common clock. The system set up and parameters considered are identical for both cases. The measured results are shown in Fig. 7 . In obtaining Fig. 7, the synchronisation clock amplitude is selected as 100mVpp, as this value provides a low clock amplitude sufficient to maintain synchronisation with a small margin above the minimum required clock level. A 40mA bias current is also used, as this provides the maximum range for the OFDM signal level where synchronisation can be achieved. It should also be noted that the above-mentioned bias current setting is also determined by the DML used.
Figure 7 shows that the OFDM signal level has an exploitable operating region from approximately 530mVpp to 760mVpp where the OFDM signal power-dependent BER variation is negligible. More importantly, it is also shown that the presence of the synchronisation clock at the selected level has almost negligible impacts on the system BER performance within the aforementioned exploitable operating region. Therefore, if an OFDM signal level of 600mVpp is selected, this is both within the exploitable operating region and the synchronisation region, so even though the OFDM signal level must be limited to ~600mVpp to allow receiver synchronisation, this is still adequate to achieve optimum system performance.
In all experimental results presented below, the operating point (point A in Fig. 7) is selected, which corresponds to an OFDM signal level of 600mVpp, a synchronisation clock level of 100mVpp and a bias current of 40mA. This point allows operation with synchronous clock recovery in the receiver without any BER degradation compared to the minimum BER achieved with the common clock configuration. In Fig. 7, the occurrence of the minimum BERs for both cases considered is a direct result of the driving signal-induced variations in signal distortion/clipping and extinction ratio of the intensity modulated signals: A high OFDM signal level leads to a large OOFDM signal extinction ratio. This increases the effective signal-to-noise ratio (SNR) in the receiver, thus decreasing the BER; whereas a high OFDM signal level also causes increased signal waveform distortions and severe signal clipping, leading to an increase in BER. The co-existence of these opposing effects results in the trough shaped curve shown in Fig. 7. It is contrary to the expectation that when the synchronisation clock is introduced this would lead to a degradation in system performance due to the higher driving signal-induced signal distortion, which is not accompanied by an improvement in the effective extinction ratio of the OOFDM signal. An increase in the peak DFB driving voltage, however, only occurs when the positive (negative) clock signal peaks coincide with the OOFDM positive (negative) signal peaks, these new peaks have higher frequency content so any increase in distortion/clipping mainly occurs to the high frequency clock rather than the lower frequency OOFDM signal. The clock signal can therefore be introduced to increase the DFB driving voltage without degrading the BER performance.
Having discussed the OFDM signal voltage dependent system BER performance, Fig. 8 is plotted to investigate the influence of the synchronisation clock power level on the system BER performance. In obtaining Fig. 8, the transmission system is configured for synchronous clocking subject to the optimum OFDM signal voltage identified in Fig. 7. It can be seen in Fig. 8 that the clock signal power can be varied over a range of at least 6dB without effecting the system BER. Such a wide dynamic range implies that the system is very robust to variations in the clock signal power. It should also be noted that, to maintain synchronisation, the tested clock signal power region is limited to the maximum output adjustment range of the frequency synthesiser employed in the experiments, the dynamic clock range may therefore exceed 6dB.
3.3 Performance of synchronously clocked real-time OOFDM
For 11.25Gb/s over 25km SSMF OOFDM signal transmission in the DML-based IMDD system under the identified optimum operating conditions, the system BER performance as a function of received optical power is plotted in Fig. 9 for both the common clock configuration and the synchronous clock configuration. The results clearly show that the BER performance of these two cases are identical, implying that the synchronous clocking technique allows a high quality clock to be recovered in the receiver, and more importantly, that the technique does not result in any BER or optical power budget degradation. The high quality of the recovered clock can also be seen in Fig. 4(h), where the 2GHz clock in the receiver (CADC) with a peak-to-peak jitter as small as 10ps is clearly locked to the 2GHz clock in the transmitter (CDAC). Furthermore, Fig. 10 presents comparisons of subcarrier constellations measured before equalisation in the receiver, between the common and recovered clock cases. The observed excellent resemblance between corresponding subcarrier constellations further verifies the high performance of the synchronous clocking technique.
The optical back-to-back BER performance is plotted in Fig. 9, which shows that there is an optical power penalty of <1dB at a widely adopted forward error correction (FEC) limit of 2.3x10−3. In addition, the minimum BER achieved for both clocking methods is ~1.5x10−3, which is slightly higher than that obtained in . Such a difference is due to the utilisation of extra electrical components including amplifiers, couplers and splitters, as illustrated in Fig. 3. These additional components give rise to increased noise and signal distortions. A main source of distortion is believed to originate from the RF component ports, which do not offer a sufficiently high and uniform return loss over the wide signal spectral range (0-4GHz).
Experimental measurements also indicate that the clock recovery can operate with a received optical power as low as −13.5dBm. This is also verified in Fig. 4(f), where the received 4GHz clock at a received optical power of −13.5dBm shows more jitter and noise compared to the received 4GHz clock at a received optical power of −6.5dBm, as presented in Fig. 4(e). The 7dB reduction in received optical power does not have an effect similar to a 14dB reduction in transmitter’s electrical power, as such an electrical power reduction destroys the system synchronisation. This implies that the intensity-modulated optical power does not affect the performance of the proposed technique, further demonstrating the robustness of the synchronous clocking technique.
3.4 System performance stability
The system performance stability over time is examined for both the common clock and synchronous clock methods. It is known that the DFB laser wavelength may drift slowly with small changes in laser temperature. When the common clock configuration is used, a drift in laser wavelength results in a wavelength-dependent differential time delay between the clock signal and the received OFDM signal. As manual symbol alignment is used, the change in the differential time delay effectively shifts the symbol alignment in the receiver, thus leading to the BER degradation. This is the physical mechanism underpinning the BER evolutions shown in Fig. 11(a) , where the first plot shows the BER increasing after initial symbol alignment as the symbol alignment deteriorates; whilst the second plot shows the BER reducing as the symbol alignment improves. When the BER drifts it is always possible to restore the system operation to the minimum BER by only readjusting the symbol alignment.
In sharp contrast, when BER stability is observed with the synchronous clocking technique, it is seen to be significantly more stable as shown in Fig. 11(b). The BER can remain stable for over one hour before symbol realignment is needed. The improved stability is due to the fact that the clock signal is transmitted with the OOFDM signal, therefore any change in the signal propagation time due to the laser wavelength drift is experienced by both the OFDM signal and the clock, therefore no significant differential time shift is produced within the experimental measurement period to significantly degrade the symbol alignment and hence the BER. However, the DFB wavelength drift with small changes in laser temperature can still result in very small BER deteriorations over a long period of time, as observed in Fig. 11(b). This is mainly due to the wavelength dependent chromatic dispersion-induced differential time delay between the OFDM signal and the clock signal. This BER drift effect is now due to the small differential wavelength variation as opposed to the absolute wavelength change in the common clock case, thus dramatically reducing the impact on the BER drift.
Synchronous clock recovery has been proposed, experimentally demonstrated and optimised in a real-time end-to-end DML-based 11.25Gb/s OOFDM IMDD system. The technique offers a low-cost, low-complexity, DSP-fee, robust solution with no BER performance or optical power budget penalty and achieves improved BER stability. The work presented here is a vital step towards the realisation of practical OOFDM transmission systems. Furthermore this work is also important as it potentially offers a simple and highly effective solution for network synchronisation in OOFDMA PONs. Extensive investigations are currently being undertaken in our research group to implement the proposed synchronisation technique in OOFDMA PONs with practical optical power budgets.
This work was partly supported by the European Community's Seventh Framework Programme (FP7/2007-2013) within the project ICT ALPHA under grant agreement n° 212 352, and in part by the Welsh Assembly Government and The European Regional Development Fund.
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