We select the optimum design parameters for real-time optical OFDM transceivers running at 25 Gb/s and analyze power consumption and ASIC footprint for a variety of configurations based on synthesis for a 65nm standard-cell library. Experiments quantify the effects of modulation format and the number of IFFT/FFT points used in transceivers.
© 2011 OSA
Optical orthogonal frequency division multiplexing (O-OFDM) is a potential solution for 100 Gigabit Ethernet (GbE) and beyond due to its high spectral efficiency and resilience towards chromatic and polarization mode dispersion . Recently many multi-gigabit real-time O-OFDM systems based on field programmable gate array (FPGA) implementations have been demonstrated [2–4], since FPGAs offer a high degree of flexibility and quick implementation of proof-of-concept systems. The next step in confirming the feasibility of O-OFDM involves the design and assessment of ASIC (application-specific integrated circuit) implementations. In , we designed and synthesized QPSK-based 21.8 Gb/s ASIC O-OFDM transceivers, determining their area and power. In this paper, we extend this work, synthesizing and performing post-synthesis simulations of O-OFDM transceivers operating at 25 Gb/s. Here, we focus on high-capacity short links that would be used in computer networks and data centers, where power is an especially important constraint. However, our methodology could easily be extended to include systems with higher levels of optical impairment.
First, we fix the (inverse) fast Fourier transform (I)FFT size at 128 points, and explore the effects of various modulation formats; we consider M-QAM modulation, for values of M ranging from 22 to 28. Next, we fix M to 4, and vary the IFFT/FFT size in the range of 64 to 1024 points. Based on our ASIC synthesis results, we determine the power consumption and required area of all digital signal processing (DSP) transceivers and examine how the various parameters affect their area and power. Lastly, we perform post-synthesis simulation to verify correct functionality.
2. System structure
Figure 1 shows the structure of O-OFDM transceivers, here with IFFT/FFT size fixed to 128. The transmitter (Fig. 1(a)) takes the incoming data bits and maps them to QAM symbols. A series of M-QAM modulation formats are investigated, for M = 2m, m = 2 to 8 inclusive. The symbols are then fed to a 128-point IFFT whose bit precision was varied from n = 6 to 20 bits (for each of the real and imaginary parts of the complex data). The output of the IFFT is clipped and scaled to be interfaced with a k-bit digital-to-analog converter (DAC). The resolution of the DAC, k, was varied from 3 to 12. The system uses the discrete multitone (DMT) modulation format with 50 data subcarriers (causing the FFT to produce purely real data).
The receiver side is shown in Fig. 1(b) where a k-bit analog-to-digital converter (ADC) first converts the signal into the digital domain. We keep the ADC resolution k the same as the DAC resolution. After serial-to-parallel conversion, the OFDM signal is scaled to p bits and fed to a 128-point FFT. The FFT precision, p, is also varied from 6 to 20 (independent of the IFFT precision n). The output of the FFT (128 complex words) is equalized with 1-tap equalizers then fed to a symbol de-mapping block to translate from QAM symbols back to the original binary data. Later we will consider the effects of changing the number of IFFT/FFT points.
3. System characterization
First, we use simulation to determine the optimum clipping ratio for each DAC resolution. Then, we use a fixed-point Matlab (I)FFT to study the effects of IFFT/FFT bit precision in a simulated electrical back-to-back configuration. At one stage, we vary the IFFT bit precision while using a double-precision floating FFT at the receiver. In the next stage, we vary the FFT bit precision while using a floating point IFFT at the transmitter. We repeat this process for all modulation formats considered above; the results for 16-QAM are plotted in Fig. 2 . Two regions can be identified in the plots: (1) an (I)FFT-precision-limited region in which increasing the bit precision of the IFFT/FFT results in about 6 dB improvement in error vector magnitude (EVM), and (2) a quantization-limited region in which increasing the data converter resolution improves EVM by 5 to 6 dB per bit while increasing IFFT/FFT bit precision does not have any effect on the signal quality.
Using the system characterization results and given a target bitrate and signal quality, an optimized design can be obtained by exploring the different combinations of modulation depth, signal converter resolution, sampling speed, and arithmetic precision. The optimum designs are those that use the lowest resolution in the data converters and the minimum bit precision of the IFFT and FFT, while meeting the required EVM with a necessary margin to account for the optical components.
In this work, we consider a system running at 25Gb/s over 300 m of single-mode fiber and a target bit error rate (BER) of 10−3. Following the procedure outlined above and considering the required EVM that corresponds to 10−3 BER for different modulation formats, we search for optimum design parameters. The results are listed in Table 1 . We then repeat the simulations within an optical link and calculate the resulting BER. If we were to target an optical system with greater levels of impairment, we would require greater precision in the signal converters as well as higher arithmetic precision within the IFFT and FFT.
4. ASIC design and synthesis
Given a configuration from Table 1, there are multiple hardware implementations capable of meeting the required sampling rate. Let w represent the number of samples produced or consumed each clock cycle by a given transmitter or receiver; w is thus a measure of parallelism within the transceiver. Let f be the system’s clock frequency. So, w × f must equal the required sampling rate. For example, to reach 8 GS/s, a transmitter could produce 128 samples per cycle at 62.5 MHz, or 64 samples per cycle at 125 MHz, and so on. Based on this idea, we have constructed a hardware generator that takes as input the parameters from Table 1 as well as values for w and f. The generator then produces synthesizable Verilog descriptions of the corresponding transmitters and receivers, using FFT and IFFT cores created by the Spiral hardware generation tool .
For each configuration listed in Table 1, we consider designs with w = 128, 64, 32 …, and decreasing until f reaches 800 MHz. Then, we synthesize each design using Synopsys Design Compiler, targeting a 65 nm standard cell library. Figure 3 shows the area and power of each synthesized design. Points closest to the lower-left corner are the most area- and power-efficient. The transmitter designs span a power range from 30 to 400 mW and an area range from 0.6 to 2 mm2. Receivers in general require more area and power due to the higher precision required for the FFT and the use of complex multipliers for equalization. However, we observe that at low modulation formats, the difference is very small or can be reversed.
For any particular modulation format, the leftmost instance corresponds to the highest frequency (and thus the lowest w), while the rightmost instance corresponds to the lowest frequency and largest w. So, as w increases, the power requirement decreases (due to lower frequencies) while area increases (due to increased parallelism within the implementation). This allows the designer to balance between these two cost metrics by choosing the value of w that gives the desired area/power tradeoff.
Another interesting observation is that although higher modulation formats require more precision within the digital system, they tend to provide better tradeoffs between area and power. That is, the power savings produced by using a lower clock frequency more than offsets the increased power required by the additional bits needed within the IFFT/FFT.
There is another non-obvious tradeoff here as well: higher modulation formats allow lower sampling rates within the signal converters, but require more precision. This effect merits further consideration in future work: how are the costs (power, area) of signal converters related to their precision and sampling rate?
Finally, we choose the 16-QAM transceiver with the lowest power consumption for post-synthesis simulation, including optical transmission simulation. These results are included in Section 6.
5. ASIC transceivers with different (I)FFT sizes
OFDM systems with large (I)FFT sizes have small cyclic prefix overhead; however, they require more arithmetic operations and therefore have higher implementation cost. The aim of this section is to analyze the cost of using large FFT sizes in terms of power consumption and chip area. Here, we examine 25 Gb/s transceivers with (I)FFT size ranging from 64 to 1024. We have fixed the modulation format to 4-QAM and the oversampling factor to 1.28 so that the signal bandwidth is the same for all transform sizes. Thus, each implementation must run at a sampling rate of 32 GS/s to reach a bit rate of 25 Gb/s. For each (I)FFT size, we generated three designs with different parallelism/frequency (parameters w and f as in Section 4). We considered w = 32, 64, and 128 samples per cycle, giving clock frequency f = 1000, 500, and 250 MHz (respectively). We performed bit precision simulations to determine the required precision for each transform, observing that for a QPSK system with BER of 10−3 or better, the IFFT/FFT precisions of 12/14 are still adequate for all considered transform sizes. We then synthesize each design targeting a commercial 65 nm standard-cell library and show the corresponding area and power consumption in Fig. 4 .
In each figure, the (I)FFT size n is indicated with data labels. Each value of n has three design points (the three w/f pairs as described above), with the highest values of w on the right. Both graphs closely follow an observable pattern except in the points where n ≤ w (the three lowest-power points in each graph). These points have lower relative cost because special optimizations can be applied to FFTs when this condition holds.
As in Section 4, we observe that increasing w produces larger designs that require less power. Then, by comparing one line to the others, we are able to observe the large effect of changing the (I)FFT size. For example, we see that the w = 32 transmitter design for n = 1,024 is 4.7 times larger and 3.6 times higher power than the corresponding design for n = 64. Comparing with Fig. 3 and 4, we see that the (I)FFT size can have a much larger effect on the power and area of the OFDM transceiver than the modulation format.
Note that at most (I)FFT sizes, the receiver’s cost is very close to the transmitter’s (and for a few design points, slightly less expensive). This matches our observation in Section 4 that as the modulation format increases, the cost of the receiver grows larger relative to the cost of the transmitter. At higher modulation formats, we expect all receivers here to become more expensive than their corresponding transmitters.
6. Post synthesis and optical link simulation
Next, we test and simulate one of the netlists produced by synthesis in order to ensure correct functionality. For this simulation, we choose the lowest-power 16-QAM transmitter and receiver as shown in Fig. 3. The data elements from the post-synthesis designs are interfaced with Matlab models for the DAC, optical link, and ADC, as shown in Fig. 5 . The simulation models the signal being amplified, low-pass filtered, and fed into a linear optical modulator. Then, the model simulates optical transmission over 300m of SMF and direct detection with a photodetector. The output of the photodetector is then fed into the netlist-level simulation of the digital portion of the receiver. The transmission simulation results, presented in Fig. 6 , show clear constellations with EVM values below −24 dB for all subcarriers which indicates that the transmission was error-free.
This paper considered the ASIC implementation of 25 Gb/s O-OFDM transceivers, first using modulation formats from 4-QAM to 256-QAM, then using varying (I)FFT sizes from 64 to 1024. For each modulation format and FFT size, the required system parameters were determined by simulation. Then, hardware implementations were generated for each design, and each was synthesized for 65 nm ASIC to determine its power and area requirements. Lastly, we performed post-synthesis simulation, verifying error-free transmission.
References and links
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