Engineers are currently facing some technical issues in support of the exponential performance growths in information industries. One of the most serious issues is a bottleneck of inter-chip interconnects. We propose a new “Photonics-Electronics Convergence System” concept. High density optical interconnects integrated with a 13-channel arrayed laser diode, silicon optical modulators, germanium photodetectors, and silicon optical waveguides on single silicon substrate were demonstrated for the first time using this system. A 5-Gbps error free data transmission and a 3.5-Tbps/cm2 transmission density were achieved. We believe that this technology will solve the bandwidth bottleneck problem among LSI chips in the future.
©2011 Optical Society of America
The CPU-CPU and CPU-memory inter-chip bandwidths in personal computers or servers are doubling every two years, and are estimated to reach the Tera-scale by the middle of the 2010s . Although the wiring pitches in logic circuits are expected to shrink exponentially based on Moore’s law, the LSI I/O pad pitches, such as flip-chip pad pitches, are presently expected to stay large . This is the reason why the line speed for inter-chip interconnects in the future needs to be much higher than that for the intra-chip ones. The required line speed is estimated to exceed 40 Gbps by the late 2010s, and currently there are no known manufacturable solutions with electrical interconnects .
An optical interconnect with silicon photonics has been expected to be used as a candidate for solving the bandwidth bottleneck problem among LSI chips and has been researched by many organizations [1, 3–6], because of the intrinsic properties of the optical signal, such as a wide bandwidth, low latency, low power consumption, and low mutual interference, and the industrial advantages of silicon for use as the resources in the electronics industry.
In this paper, we present high density optical interconnects with a silicon photonics integrating an arrayed laser diode, silicon optical modulators, and germanium photodetectors on a single silicon substrate for the first time. We believe that this results in an important milestone towards creating a “Photonics-Electronics Convergence System”, which is our proposed system to overcome the bottlenecks of inter-chip interconnects.
2. Concept of photonics-electronics convergence system for inter-chip interconnects
The concept of the Photonics-Electronics Convergence System for inter-chip interconnects is shown in Fig. 1 . A laser diode (LD), optical modulators, and photodetectors (PDs) are integrated on a single silicon substrate, and they are optically linked to each other by using silicon optical waveguides. LSI bare chips are mounted on the substrate and are electrically connected to the optical modulators and PDs on the substrate by using flip-chip bonding.
By using this system, the function of the conventional electronic wires on a printed circuit board (PCB) can be replaced by the optical interconnects on a silicon substrate, which will be one hundredth the size of a PCB. This silicon substrate has a wide bandwidth capability due to the optical signal properties. Since the silicon substrates can also be fabricated using a CMOS compatible process, they have quite a high density and low cost. Furthermore, because this system is an optically closed one without any optical inputs and outputs, the users don’t have to worry about any optical issues, such as optical coupling, optical reflection, or polarization dependence.
3. Configuration of optical components
Cross section diagrams of the optical components are shown in Fig. 2 . The silicon optical waveguides have rib-shaped cross section cores. The thickness of both the mesa and slab are 100 nm, respectively, and the width of the mesa is 600 nm. The silicon optical modulators are Mach-Zehnder interferometers composed of 340-μm interaction length phase shifters and multimode interference (MMI) couples. The phase shifters can change the refractive indices by using the carrier plasma effect in the lateral p-i-n diode structures . The germanium PDs have selectively grown epitaxial germanium mesa and vertical p-i-n diode structures . They are also placed at the terminals of the silicon optical waveguides.
The LD chip is a 13-channel arrayed InGaAsP LD with a 30-μm channel pitch. Each channel is a Fabry-Perot type with a spot-size converter. The LD chip also has a single pair of electrodes for all 13 channels emitting simultaneously.
The silicon substrates for the optical interconnects were fabricated from 4-inch silicon-on-insulator (SOI) wafers. The thickness of the buried oxide layer and the SOI layer were 3 μm and 200 nm, respectively. The fabrication processes for the silicon optical waveguides, silicon optical modulators, and germanium PDs were mainly performed by NTT Advanced Technology (NTT-AT). Electron beam lithography and dry etching were used to form the optical waveguides. Ultra-high vacuum chemical vapor deposition was used to selectively grow the epitaxial germanium mesas for the PDs on the silicon waveguides. The thickness of the mesa was 1 μm. Boron and phosphorous ion-implantations were used to form the lateral p-i-n structure for the modulators and the vertical one for the PDs. The waveguides, modulators, and PDs were covered with 1.2 μm SiO2 upper cladding layer using chemical vapor deposition. Contact holes for the modulator and PDs were formed by dry etching, and 1 μm aluminum was deposited and patterned for the electrodes. After the waveguide endfaces and the pedestals for the LD mount were formed by dry etching, the LD chips were hybridly integrated to the silicon substrates by using passive alignment technology by NEC .
A photograph of a fabricated silicon substrate used for the optical interconnects is shown in Fig. 3 . The substrate is 4.5 x 5 mm2. The 13-channel arrayed LD, optical modulator array, and PD array are integrated on a single silicon substrate, and they are optically linked to each other by the silicon optical waveguide array.
5. Experimental results
5.1 Characteristics of optical components
Before conducting the data transmission experiments, each optical component was evaluated separately. The near field pattern and output intensity of the 13-channel arrayed LD are shown in Fig. 4 . The output power uniformity across all the channels was better than 0.7 dB. The wavelength was 1530 nm.
The DC response of the optical modulator is shown in Fig. 5 . The modulator was driven in injection mode with forward bias voltage. The π-phase shift voltage (Vπ) was 0.36 V, and the Vπ*L was 0.012 Vcm. The extinction ratio (ER) was 14.6 dB.
The measured frequency response of the PD with a 50-Ω load impedance is shown in Fig. 6 . The 3-dB cutoff frequency was 3.2 GHz for a 1-V bias voltage, and 4.2 GHz for 5 V. The photo to dark current ratio of the PD was higher than 30 dB . And the responsivity was 1.0 A/W.
5.2 Data transmission experiments
The setup for the data transmission experiments is shown in Fig. 7 . The 13-channel arrayed LD was driven by a single DC current. The 13-channel CW lights from the LD array were launched into the optical modulators. The RF input signals from the PPG were pre-emphasized by the differentiator and input to the modulators. The voltage amplitude after the pre-emphasis was 3.9 V peak to peak. The modulated light signals propagated along the optical waveguides, then were input to the PD array and converted to electrical signals. All the experiments were carried out without temperature control.
The measured eye diagrams of electrical signals from PDs in channels 1, 2, and 3 at 5-Gbps NRZ with a 27-1 pseudo random binary sequence (PRBS) are shown in Fig. 8 . The clear open eyes suggest that the optical links are capable of a 5-Gbps data transmission. The measured bit error rate (BER) for a 5-Gbps PRBS is shown in Fig. 9 . We confirmed that the BER was smaller than 10−12 when the PD input power was larger than −9.5 dBm.
The footprints of the optical components per channel are listed in Table 1 . The total footprint was 0.144 mm2 per channel. Then, a 3.5-Tbps/cm2 transmission density with a 5-Gbps channel line rate was achieved. In order to easily drive and prove the optical components, about half of the total footprint was occupied by the electrode pads in this experiment. We also have already developed and reported on a faster optical modulator  and photodetector . Therefore, we expect to improve the transmission density by integrating smaller electrode pads, faster optical modulator, and photodetector in the near future.
The optical power budget per channel is roughly summarized in Table 2 . The second column in the table lists the budget when the modulator bias voltage was adjusted so that the optical output would be maximized. Then, the overall optical loss was about 20 dB. The third column in the table lists the budget when the modulator was driven at 5 Gbps. We estimated that the 7-dB loss increase for a 5-Gbps operation is caused by modulation loss and modulator excess loss due to the optical absorption by the free carrier injection. The LD to waveguide coupling loss and the modulator loss during RF operations are issues that need to be improved in terms of the optical power budget. We expect that the former loss can be drastically reduced by using a SiON SSC , and the later can be reduced by using an efficient optical modulator with side-wall grating  in the near future.
High density optical interconnects integrated with a 13-channel arrayed laser diode, silicon optical modulators, germanium photodetectors, and silicon optical waveguides on single silicon substrate were demonstrated for the first time. A 5-Gbps error free data transmission and a 3.5-Tbps/cm2 transmission density were achieved. We believe that this technology will solve the bandwidth bottleneck problem among LSI chips in the future.
This research is supported by the Japan Society for the Promotion of Science (JSPS) through its “Funding Program for World-Leading Innovative R&D on Science and Technology(FIRST Program).” Part of the fabrication was conducted at the Nano-Processing Facility, supported by IBEC Innovation Platform, AIST.
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