We demonstrate an ultracompact, chip-based, all-optical exclusive-OR (XOR) logic gate via slow-light enhanced four-wave mixing (FWM) in a silicon photonic crystal waveguide (PhCWG). We achieve error-free operation (<10−9) for 40 Gbit/s differential phase-shift keying (DPSK) signals with a 2.8 dB power penalty. Slowing the light to vg = c/32 enables a FWM conversion efficiency, η, of −30 dB for a 396 μm device. The nonlinear FWM process is enhanced by 20 dB compared to a relatively fast mode of vg = c/5. The XOR operation requires ≈ 41 mW, corresponding to a switching energy of 1 pJ/bit. We compare the slow-light PhCWG device performance with experimentally demonstrated XOR DPSK logic gates in other platforms and discuss scaling the device operation to higher bit-rates. The ultracompact structure suggests the potential for device integration.
© 2011 OSA
All-optical nonlinear signal processing is advancing rapidly, with recent demonstrations of functionalities such as all-optical signal regeneration , THz bandwidth multi-impairment monitoring , and 1.28 Terabit/s demultiplexing . All-optical logic functions are one of the components expected to compose such a system . To this end, a variety of all-optical logic gates have been demonstrated at speeds up to 640 Gb/s . Research efforts into advanced modulation formats involving phase-encoded signals, such as differential phase-shift keying (DPSK), have received significant attention due to their tolerance to system impairments and nonlinearities [1, 6]. On the device side, all-optical logic functions employing DPSK have been demonstrated in a variety of platforms: highly nonlinear silica fiber (HNLF) , semiconductor optical amplifiers (SOAs) [8, 9], and periodically poled lithium niobate (PPLN) . These platforms, however, experience different limitations, including stimulated Brillouin scattering in HNLF, free-carrier patterning effects and a bias current that adds to the energy requirements of SOA, and, in the case of PPLN, temperature control, though a route forward has been suggested .
This past year, an all-optical DPSK XOR logic gate up to 160 Gb/s was demonstrated in a 5 cm integrated chalcogenide glass waveguide . The increased nonlinear parameter, γ of integrated waveguides, ∼10 (W-m)−1 for chalcogenide and 300 (W-m)−1 in silicon nanowires , allows for reduced power thresholds to observe a given nonlinear process. Silicon all-optical on-off keying (OOK) logic devices based on micro-ring resonators , two-photon absorption [15, 16], or Raman gain  phenomena are also capable of low power thresholds, though these devices are limited to bit rates less than 1 Gb/s due to the inherent bandwidth of the resonant structures. This is not an intrinsic limit of silicon, as all-optical functions at much faster rates (> 1 Tb/s) have been demonstrated [3, 13, 18, 19].
The periodic lattice of the photonic crystal waveguide (PhCWG) gives rise to so-called slow-light effects in which the light travels at a decreased group velocity, vg, allowing for high intensity light inside the photonic crystal even though small energies are injected. Enhancement of third-order χ(3) optical processes have been shown to scale as S2, where S = ng/n0 is the ‘slow-down’ factor of the light in the slow medium with group index ng, and the phase index n0 [20, 21]. This scaling results from: (i) the increased effective path length of light in the medium, and (ii) the spatial compression of the pulse intensity in the slow medium, each contributing a factor of S [21–24]. This slow light effect can give rise to nonlinear parameters near γ ∼ 104 , more than an order of magnitude larger than nanowires made of the same material γ ∼ 102. Slow-light enhanced nonlinear processes such as soliton generation , self-phase modulation [25,27,28], and third-harmonic generation  have been demonstrated in photonic crystal waveguides.
Most recently, four-wave mixing (FWM) in photonic crystals was realized by several groups [30–34], including all-optical demultiplexing of a 160 Gbaud signal in a Si PhCWG . In contrast to the single beam interactions above, slow-light enhances the FWM process as S4, though the change in mode area with slow-light must also be taken into account [30, 36]. The development of dispersion engineering in photonic crystals over the past few years has opened the possibility to generate a flat dispersion band of greater than >THz bandwidth, while simultaneously maintaining slow group velocities [37, 38]. In brief, the slow-light enhancement of optical signals in PhCWGs, combined with broader bandwidth operation provides the means to generate FWM, and therefore all-optical signal processing, over compact ≈ 100 μm length scales.
In this paper we demonstrate for the first time, to our knowledge, an all-optical exclusive-OR (XOR) logic gate in photonic crystal waveguides. Our approach employs four-wave mixing (FWM) to perform the logic operation at 40 Gbit/s with return-to-zero (RZ) differential phase-shift keying (DPSK) signals. Slow-light enhancement (vg=c/30) of the optical signal in the photonic crystal waveguide (PhCWG) [9, 12] allows for an ultracompact device (396 μm) and suggests potential for integration in future all-optical communication systems.
2. All-optical XOR gate operating principal, sample description, and slow-light four-wave mixing
A schematic of the all-optical XOR logic gate is shown in Fig. 1(a). The all-optical XOR operation arises from non-degenerate four-wave mixing of two phase encoded data signals at λ1 and λ2 with a CW probe at λp. This generates an XOR output at the idler wavelength λi inside the PhCWG. There are in fact three idlers that carry the XOR product . Here we focus on the idler generated by the product of ωi = ω2 + ωp – ω1. The associated phases of the data channels therefore mix according to: ϕi = ϕ2 + ϕp –ϕ1, with the CW signal ϕp contributing a constant phase offset between the two data signals. In contrast to the intensity modulation OOK format, the optical signals of DPSK data are encoded with a differential phase of ‘0’ or ‘π’. Thus the phase of the generated idler contains the differential ‘0’ or ‘π’ states at the output of the XOR gate, with a difference of ‘0’ and ‘2π’ being equivalent. Fig. 1(b) indicates the full truth table of the device, including the output after demodulation in a one-bit-delay interferometer.
The device is a 396 μm long dispersion engineered silicon PhCWG air-suspended structure with a slab thickness of 220 nm, lattice period of 404 nm, hole radii of 115 nm, and first hole lattice shift s1 = −50 nm, similar to that in Ref. . The device includes mode converters to enhance power injection into the device. The adapters include short (100 μm) Si channel waveguide sections, which contribute negligibly to the nonlinear process [30,31]. The photonic crystal region exhibits slow-light enhancement, inducing large intensity in the waveguide allowing for efficient four-wave mixing on a short lengthscale. Fig. 2 shows the measured group index ng ∼30 covers a 12 nm range centered around 1540 nm, sufficient bandwidth to accommodate the two 40 Gb/s data channels, CW pump signal, and the generated idler. The linear propagation loss in the slow light region was estimated from cutback measurements to be 65 dB/cm  with a total insertion loss of −11.8 dB. From the mode area (Aeff ∼0.5μm2) and the Kerr coefficient n2 = 5×1018 m2/W of silicon, we estimate the effective nonlinear parameter γeff ∼ γS2 ∼ [2πn2/λAeff]S2 ∼3000 (W/m)−1 for the slow light PhC waveguide . The small change in group-velocity dispersion (GVD), β2= −0.6 ×10−21 s2/m, over the device bandwidth ensures efficient phase matching of the four-wave mixing process over the device length . The slow-light region is sufficiently flat such that walk-off of the two-pulsed data signals is negligible for this device length. The FWM conversion efficiency, η, in the presence of slow-light and in the undepleted pump approximation, is defined as :31]. A recent theoretical work derived the effective nonlinear parameters for FWM in photonic crystal waveguides, concluding that the process scales as S4 ∼ ngData1 × ngData2 × ngCW × ngidler , extending prior work on single beam interactions . Though alluded to for some time in the literature, only this past year was the S4 scaling experimentally confirmed taking into account the change in mode shape Aeff with group index ng in a single study . In the present device, we thus expect an increase of ng from 5 to 30 to decrease the device length substantially. A quantitative analysis of the FWM enhancement due to slow light, critical to the short device length in this demonstration, is carried out below in the discussion section.
3. Description of experimental setup
Fig. 3 shows the experimental setup. Two 40 Gbit/s RZ-DPSK signals were generated from two CW sources at λ1=1538.1 nm and λ2=1539.5 nm (Pave ∼39 mW, or ∼13mW coupled in the waveguide for each data signal) and a pair of Mach-Zender modulators (MZ). The first MZ carves out the 40 GHz RZ pulses with 33% duty cycle, while the second encodes a 40 Gbit/s pseudorandom bit sequence (PRBS) of 27−1 pattern length. The two DPSK signals were amplified, then demultiplexed spectrally in a pulse shaper , with one of the branches passing through an optical delay line (ΔT) to separate the signals temporally. These signals are then mixed with the CW pump (λp = 1541.7 nm, Pave ∼15 mW coupled) via a coupler before being sent to the chip. The three signals combined for a total of 41 mW coupled to the waveguide. We measured negligible two-photon absorption in the Si PhCWG at this power level, consistent with our prior measurements [30, 31]. Each channel had a polarization controller to ensure proper alignment to the device transverse-electric mode (TE), e.g. transmission in the plane of the slab. The collected signal is amplified, with the XOR idler then extracted by a 1 nm filter before being demodulated, filtered again to improve the optical signal-to-noise ratio (OSNR), and detected by a 40 Gbit/s receiver.
4. Experimental results
4.1. Role of slow-light enhanced four-wave mixing
Fig. 4 shows the measured output spectrum at the output of the Si PhCWG. The two input 40 Gbit/s DPSK data channels, CW probe signal and the XOR idler generated at λi = 1543.0 nm (shaded region), are indicated. We tuned the CW pump signal over a spectral range of approximately 4.5 nm with flattop FWM conversion efficiency, Fig. 4 (inset). Including the separation bandwidth of the two data signals here (1.6 nm), this range is in relative agreement with our prior degenerate FWM measurements . The conversion bandwidth offers the potential for wavelength multicasting of the XOR gate . From our experimental parameters, ϕ ≈ 1 and γeffPpumpLeff ≈ 0.05. According to Eqn. 1, the estimated FWM efficiency is ηtheory = −30 dB. As the CW is the largest signal, it acts as the pump in this scheme, and we take the data signals as the probe. This yields a measured FWM efficiency of ηexp = −30 to −32 dB, depending on whether Data 1 or Data 2 is the reference signal. The converted idler exhibits some of the structure of the PhCWG transmission, deviating from a smooth curve, due to structural disorder induced during fabrication. Additional discussion of this topic is detailed below.
While γeff scales as S2, it is known that the modal area also increases with group index [27, 31,36,40]. In Table 1, we quantify the benefits of slow-light in enhancing the FWM process. We compare the cases of a mode away from the PhC band-edge ng = 5, the sample investigated here ng = 30, and a typical silicon nanowire. While we expect an enhancement of S4 ∼ 1100 (30 dB) by going from ng = 5 to 30, the increased mode area reduces the enhancement by about 8 dB, with loss accounting for an additional 2 dB. The result is a 20 dB enhancement of the FWM process employing a slow-light mode (ng = 30) versus a relatively fast mode (ng = 5). The FWM conversion efficiency, η, is the critical parameter to achieve the logic operation. If we desire a conversion efficiency of η = −30 dB at a fixed input power of Po = 40 mW, we observe the photonic crystal achieves the desired operation at 7.5 times shorter device compared to a silicon nanowire, demonstrating the ability of slow-light to greatly enhance nonlinear interactions.
4.2. DPSK XOR logic gate results
Figure 5(a) shows the demodulated temporal waveforms captured on a sampling oscilloscope of the two input data and output XOR channels. One can see the FWM idler is the XOR output from the two input DPSK channels, confirming the all-optical logic gate functionality. The eye diagrams of the 40 Gbit/s signals after the chip and demodulation are seen in Fig. 5(b). While the eyes of the data signals are relatively crisp, the XOR product is noisier due to the small energy of the idler coming from the photonic chip. The 396 μm device achieves the XOR operation at estimated energy of ∼1 pJ/bit, including all signal beams.
We next performed bit-error-rate (BER) measurements, Fig. 5(c), observing ‘error-free’ (BER< 10−9) operation for the all-optical XOR logic gate. The generated XOR product experienced a power penalty of ∼ 2.8 dB compared to the back-to-back case, which included a single amplification stage. Though the origin of the power penalty is unclear, there are a few possible processes that could contribute. First, the amplification of the small signal required to generate the idler in our nanophotonic device is a possible source of power penalty. As collecting the light off chip is the largest source of loss, one can presume a smaller power penalty if the output were employed directly in other on-chip functions, as envisioned in future photonic integrated circuits. Second, some disorder in the regular photonic lattice could also contribute phase differences as the light propagates along the waveguide. A third solution is to generate additional idler (XOR) signal in the FWM process. This could be achieved by injecting more power, or improving the device fabrication to reduce scattering losses. Improved photonic crystal fabrication is an extremely active area of research that would help with the second and third points. In addition to technological improvements in lithography and etching techniques, newly proposed approaches to reduce loss via precise control of hole-hole scattering coherence and mode shape have only recently been explored . The ‘loss engineering’ of Ref.  is expected to improve PhC devices even with current fabrication technologies. We now compare the slow-light photonic crystal XOR DPSK logic gate performance to other demonstrations.
All-optical XOR gates have been demonstrated in a variety of platforms. We focus here on DPSK results for the reasons we mentioned in the introduction, namely robustness against system impairments. The key parameters of the devices are listed in Table 2. These include: length, experimental bit rate, energy per bit (Pavg / bit-rate), bit-error rate results (if provided), and the nonlinear conversion efficiency. For this section we use the instantaneous FWM efficiency, , since the input power values of several systems are not readily available. The output optical spectrum is presented, however, and allows direct comparison. We ignore external amplifiers in all cases and focus solely on the FWM process in the energy calculation. Note that the electrical power required for SOAs is not taken into consideration in this estimate . All of the demonstrations thus far have been based on four-wave mixing, with the exception of PPLN  which is based on sum-frequency generation, where we define the conversion efficiency as η1.
The Si PhCWG XOR operation presented here compares favorably well across a broad range of categories, the most salient advantage being nearly an order of magnitude shorter device length (∼ 400 μm) and the most notable drawback being bandwidth (∼ 1 THz). This tradeoff is well-documented in the PhC literature [20, 21, 38]. This bandwidth however, is capable of performing the 40 Gb/s XOR logic operation here, and other all-optical signal operations, such as optical signal to noise ratio (OSNR) monitoring, up to 640 Gb/s . The energy consumption of the device is close to its integrated counterparts (Si and ChG), with expected parity due to improved fabrication . Though XOR logic gates have been demonstrated qualitatively in a number of platforms, relatively few have measured the bit-error rate (BER) of the operation. The best reported BER results are in ChG waveguides and SOAs, though the latter was at 10 Gb/s. The measured power penalty of the PhCWG in this work could be improved as noted in the BER measurements above. The ChG experiment also included a demonstration at 160 Gb/s, though no BER was measured in that case. We note that 640 Gb/s XOR logic has been demonstrated with OOK .
We conclude with a few statements on scaling the device to higher baud-rates (>100 Gb/s). Photonic crystal waveguides exhibit a well known tradeoff between the group index and bandwidth, commonly called the group index-bandwidth product (GBP) . The broader bandwidth of a 160 Gb/s XOR logic gate would thus require a device with a smaller group index, e.g. ng = 24. Taking into account the smaller mode size and decreased linear scattering loss at this faster group velocity, we estimate a device length of 600 μm would be required to achieve the same FWM efficiency, η= −30 dB. All-optical XOR operation at even higher bit-rates is possible with dispersion management of shorter temporal signals and careful design of the group index-bandwidth properties.
We have demonstrated an ultra-compact all-optical XOR gate using non-degenerate four-wave mixing in a dispersion-engineered photonic crystal waveguide for 40 Gbit/s DPSK signals. Error-free XOR operation was achieved with a 2.8 dB power penalty. Slowing the optical signals to velocities of ∼ c/30 enhance the nonlinear process by 20 dB, allowing for the operation in a 396 μm long device, approximately an order of magnitude shorter than prior demonstrations. Compact device operation suggests the potential for integration on an integrated photonic chip. The device operation is scalable to increased baud rates in slow light structures with increased bandwidth.
This research was supported by the Australian Research Council (ARC) Centres of Excellence (COE) and Federation Fellowship programs. J. Li was supported by FP7 Marie Curie IIF “Osiris” and UK Silicon Photonics.
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