Abstract

We experimentally demonstrate a spatially non-blocking five-port optical router, which is based on microring resonators tuned through the thermo-optic effect. The characteristics of the microring-resonator-based switching element are investigated to achieve balanced performances in its two output ports. The optical router is fabricated on the SOI platform using standard CMOS processing. The effective footprint of the device is about 440×660 μm2. The microring resonators have 3-dB bandwidths of larger than 0.31 nm (38 GHz), and extinction ratios of better than 21 dB for through ports and 16 dB for drop ports. Finally, 12.5 Gbps high-speed signal transmission experiments verify the routing functionality of the optical router.

©2011 Optical Society of America

1. Introduction

The improvement in performance gained by the use of a multi-core processor depends on how efficiently the cores collaborate with each other and communicate with the local and remote memories. Therefore, on-chip interconnects in the chip multiprocessor (CMP) gradually move from traditional bus interconnects to more sophisticated networks-on-chip (NoC). However, CMP applications continuously require more on- and off-chip communications as transistors continue to shrink in size, and metallic-interconnect-based NoC gradually becomes the bottleneck of CMP performance because of their high power consumption, limited bandwidth, and long latency [1,2]. Studies have demonstrated that photonic NoC has become a potential solution to overcome the limitations of traditional metallic-interconnect-based NoC [3,4]. The implementation of photonic NoC needs compact optical devices that can be integrated with microelectronic circuits on chip. Silicon nanophotonics has made great progress in recent years, which provides a prospect on its potential application in intra- and inter-chip interconnection for CMP.

Compact optical routers or switching fabrics are essential components for photonic NoC. Several silicon on-chip optical routers have been demonstrated [57]. However, all of them are four-port routers, which are inappropriate for practical application in photonic NoC. Generally, on-chip optical interconnects employ a two dimensional (2D) network architecture, such as mesh and torus, which requires a five-port routing function. Group of four-port routers are adopted to resolve the problem of lack of five-port router at the expense of more complicated network architecture and routing algorithms [8]. Several five-port optical routers have been proposed [4,9], but none of them has been experimentally demonstrated yet. Previously we have reported a four-port non-blocking optical router based cascaded microring resonators (MRRs) with compact footprint and low power consumption [7]. Here, we propose a new configuration of a five-port non-blocking optical router based on our previous work. Moreover, we experimentally verified the routing functionality and signal integrity of the router.

This paper is arranged as follows. Section 2.1 reviews the photonic network architectures and presents two basic network topologies (mesh and torus). Section 2.2 presents the layout and operation principle of the proposed spatially non-blocking five-port optical router. Section 3 presents the design and fabrication of the optical router. In section 3.1, a first-order microring resonator is investigated using the scattering matrix method, which guides the design of a MRR with balanced performances in its two output ports. In section 3.2, the structure design and fabrication of the optical router are described in detail. In sections 4.1 and 4.2, the response spectra and 12.5 Gbps high-speed signal transmission experiments are presented, and the possible challenges and optimization methods for the router are discussed. In section 5, the paper is summarized.

2. Photonic network architectures and routers

2.1 Photonic network architectures

Several network architectures, such as mesh [4], torus [8], crossbar [10], fat tree [11] and clos [12], have been analyzed to construct efficient photonic networks-on-chip. According to the configurability of the routing patterns, they can be divided into two categories. One is wavelength-selective passive network which has the fixed routing pattern defined at the design of the network and the path between the source and the destination is established through the dynamic selection of specific wavelength at the source or the destination [10,12], and the other is switching network which dynamically set the routing pattern through an electronic controlled network [4,8,11]. It is claimed that the former can exhibit low latency since the routing network is passive [10], which suggests that the time of selecting specific wavelength is shorter than that of configuring the optical switching network. In contrast with the wavelength-selective passive network, the switching network can offer higher aggregate bandwidth by employing wavelength division multiplexing (WDM) technology. In addition, the switching network has more compact footprint and better scalability.

It is natural that photonic network for CMP employs a two-dimensional regular topology, such as mesh [4] and torus [8], since CMP consists of a 2D grid of homogeneous general-purpose processors [13,14]. In Fig. 1(a) and 1(b), we show the block diagrams of a 16-core CMP with a 4-ary 2-cube mesh and torus network connecting different cores. Because there is no practical on-chip optical circulator, each link of the network has two unidirectional waveguides to guarantee the bidirectional communication on the same link. One of the elementary components for such a communication network is a five-port optical router (see Fig. 1(c)), which connects five directions: East, South, West, North and a local processor (through the EO/OE interfaces). This is a photonic circuit-switched network since no practical optical buffers are available. In contrast with wavelength-routing networks, the routing path of the data from a source to a destination is reconfigurable, which is configured dynamically by the electronic circuits since it is difficult to control the signal in optical domain.

 figure: Fig. 1

Fig. 1 Schematics of 2D photonic mesh (a) and torus (b) networks for 16-core CMPs. (c) A five-port bidirectional optical router. Blue square indicates processing core, yellow dot indicates optical router, and line with arrow indicates optical waveguide.

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2.2 Router topology

Figure 2 shows the proposed five-port optical router based on cascaded MRRs. The ports of the optical router have to be bidirectional since it is designed for on-chip application, including Center (connecting with a local electronic block through the OE/EO interfaces), East, South, West and North ports (connecting with other routers to form a 2D photonic NoC). The optical router is controlled by an electronic circuit integrated on the same chip. Since the MRRs of the router are identical, they have the same structural parameters. The MRRs have the same initial resonances without considering the process nonuniformity. The optical router can operate on not only a single-wavelength signal but also a WDM signal with channel spacing equal to the free spectrum range (FSR) of the MRR. Non-blocking property of the router is achieved by providing the specific physical link for each input-output combination. As shown in Table 1 , there are 20 possible optical links since the communication between input and output of the same port is forbidden. Each of the twenty optical links is established by a specific resonant MRR (labeled as “Rn”) or a waveguide directly (labeled as “none”). The five-port optical router has forty-four routing states, and each of them involves five parallel input to output optical links. Note that the previously proposed four-port optical router has nine routing states.

 figure: Fig. 2

Fig. 2 Schematic layout of the five-port non-blocking on-chip optical router.

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Tables Icon

Table 1. Twenty Optical Links of the Five-Port Non-Blocking Optical Router

Different from the metallic wires, optical waveguide crossings can be employed in photonic circuits, and due to this property complex routing can be completed in a 2D layer. However, waveguide crossings bring additional transmission loss, reflection loss and crosstalk. Therefore, the topology of the router should be designed to minimize the number of crossings. The proposed five-port optical router has 16 MRRs and 14 crossings. Compared with the five-port optical router proposed in [9], our router comprises less number of MRRs and crossings. Reduction of the number of crossings means lower insertion loss and lower crosstalk, which significantly limits the scalability of photonic NoC [15,16]. Reduction of the number of MRRs can offer the benefits in terms of device area and power consumption (containing the optical links established by the waveguide, such as East→South, which needs no power consumption). In addition, the alignment of five ports is carefully designed for practical interconnection in 2-D photonic NoC (see Fig. 2).

3. Design and fabrication

3.1 Microring resonator-based switching elements

Figures 3(a) and 3(b) show two states of the microring resonator-based switching element. When the switching element is in OFF state, an input optical signal with the wavelength of λ0 propagates from the input port to the through port. On the other hand, when the switching element is in ON state it is resonant at the wavelength of λ0, and the input signal is coupled into the MRR and transferred to the drop port. The switching element can be characterized by insertion loss ILOFF and ILON, crosstalk CTOFF and CTON in OFF and ON states respectively (see Figs. 3(a) and 3(b)), as well as extinction ratios ERd and ERt for drop port and through port respectively. Using scatter matrix method, we analyze the performance of the MRR with two symmetric couplers. When the switching element changes from OFF state to ON state, the resonance should be red-shifted from the initial position to a position half an FSR away from it (see Fig. 3(c)) Generally, ILON is slightly larger than ILOFF, and crosstalk is determined by the extinction ratios and insertion losses (CTOFF=ILON/(ILOFFERd), CTON=ILOFF/(ILONERt)), seeing Fig. 3(c).

 figure: Fig. 3

Fig. 3 (a) and (b) Configurations of microring-resonator-based switching element at OFF state and On state. (c) Normalized transmissions at the through and drop ports. The black dashed line indicates the operation wavelength. Here, the MRR has a radius of 10 μm, loss of 10 dB/cm and coupling coefficient of 0.35. (d) The variation of extinction ratios for through and drop ports with the coupling coefficient.

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Here, we assume that the thermo-optic effect only leads to the resonance shift without changing the original shapes of the transmission spectra of the though and drop ports. Note that bandwidths for two paths of the switching element are asymmetric because the bandwidth for the through path (input to through) is much larger than that for the drop path (input to drop). Thus the single-microring-based switching element shows an asymmetric behavior, but a balanced design is still helpful. From Fig. 3(d), we find that the same extinction ratios of drop port and through port can be achieved by choosing proper coupling coefficient for the MRR. Since the difference between ILOFF and ILON is relatively small, we assume that ILOFF≈ILON, then CTOFF and CTON are equal to the minus of ERd and ERt respectively. As shown in Fig. 2, single-ring MRRs coupled with waveguide grid and coupled with two parallel waveguides are both used in our structure. Analysis in this section can also be applied to the MRR coupled with waveguide cross-grid.

3.2 Fabrication

We fabricate the optical router on a 200-mm silicon-on-insulator (SOI) wafer with 220-nm top silicon layer and 2-μm buried oxide layer. Waveguide layer is defined using the 248-nm deep ultraviolet lithography and inductively coupled plasma etching. Spot size converters are used on the input and output terminals of the waveguides in order to enhance the coupling efficiency between the waveguides and the lensed fibers. TiN with a thickness of 150 nm is used to create the Ω-shaped heaters. Aluminum wires and pads are formed for wire bonding, seeing the white areas in Fig. 4 . More details on the fabrication process can be found in [17].

 figure: Fig. 4

Fig. 4 Micrograph of the five-port optical router based on cascaded MRRs.

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The optical router employs the rib waveguides with a height of 220 nm, a width of 400 nm, and a slab height of 70 nm, which only supports quasi-TE fundamental mode. In order to achieve a balanced performance between the extinction ratios of the drop and through ports, the MRR has a radius of 10 μm and the symmetric gaps are selected to be 300 nm. To reduce transmission loss and crosstalk of the waveguide crossings, elliptical crossings (long axis and short axis are 6.25 μm and 1.5 μm respectively) are used in our device [18]. The micrograph of the router is shown in Fig. 4. The efficient footprint of the device is 440 × 640 μm2, which is mainly limited by the thermo-optic tuning structures since thermal isolation is required to minimize the thermal crosstalk between adjacent heaters. In addition, input/output waveguides are specially arranged in the layout to guarantee the characterization of all optical links between West port and other four ports.

4. Experiments and discussion

4.1 Transmission spectra

We test the transmission spectra of the MRRs using an amplified spontaneous emission source and an optical spectral analyzer. Figure 5 shows the spectrum responses of R11, R1, R7, R6, R5 and R4, which control the optical links between West port and other four ports (see Table 1). Results show that the balanced design has been achieved through reasonable selection of the structural parameters for the MRR. All of the measured MRRs have 3-dB bandwidth of larger than 0.31 nm (38 GHz) at the 1551 nm operation wavelength. The extinction ratio of through port is larger than 21 dB for all of measured MRRs. We find that the transmission spectra of drop ports are asymmetric, which is mainly induced by other MRRs coupled with the input and output waveguides of the MRR under the test. Without considering the effect of the unexpected transmission from other MRRs, the extinction ratio of drop port for all of the measured MRRs is still larger than 16 dB. Note that the asymmetric property of transmission for drop port does not affect the transmission of the high-rate optical signal in this paper (~12.5 Gbps), because the bandwidth of the MRR is large enough. From the Fig. 5, total insertion loss of MRR is ~8 dB, which involves propagation loss, crossing loss and coupling loss between silicon waveguide and input/output lensed fibers. Thus, it is difficult to give the exact loss like that analyzed in section 3.1. However, it can be seen that the insertion-loss difference between through port and drop port is relatively small, which can lead to the conclusion that the approximately symmetric crosstalk of both through and drop ports has been obtained.

 figure: Fig. 5

Fig. 5 Spectrum responses of the MRRs labeled as R11, R1, R7, R6, R5 and R4 respectively.

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We also find that the transmission spectra of R1 and R5 have obvious interference fringes around the peaks (see Figs. 5(b) and 5(e)). By analyzing the layout of the optical router (see Fig. 2), we find that it is induced by grating effect between R1 and R16, as well as between R5 and R13 [19], and they form a parallel coupled double ring resonators. In fact, there is the same effect between R6 and R2, as well as between R11 and R14. But no obvious fringes appear in Figs. 5(a) or 5(d), which is because of the different lengths for the waveguides connecting the two MRRs. When the above mentioned pairs of the MRRs work in ON state at the same time, more optical power can be dropped for the two corresponding optical links, meaning lower drop-port loss ILON can be done. Additionally, tested results show that the elliptic crossing has transmission loss of about 0.5 dB and crosstalk of less than −30 dB.

Figure 6 shows the transmission spectra of drop ports for R11, R1, R7, R6, R5 and R4 in ON state. The tested spectra include four groups of resonant peaks from 1530 nm to 1563 nm. FSR of the MRR slightly increases with increasing wavelength, which is induced by the dispersion of silicon sub-wavelength waveguide. We find that resonances with the same order for different MRRs can match well, meaning that WDM signal can be operated by our device. Spacing of channel is determined by the FSR of MRR once it is fabricated. It is difficult to design the MRR with FSR matching well with the ITU standard. But using WDM technology can enhance the aggregate bandwidth and make full use of the tuning power consumption of the optical router. Tuning efficiency of the heater is ~5.4 mW/nm [7], and we can evaluate that the total tuning power consumption varies from 51.84 mW to 129.6 mW, with the assumption that the average wavelength shift is 4.8 nm for the MRRs from OFF state to ON state.

 figure: Fig. 6

Fig. 6 Transmission spectra involving four resonance peaks of drop ports for MRRs labeled as R11, R1, R7, R6, R5 and R4 in ON state.

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The optical router employs the thermo-optic effect because we focus on the demonstration of its routing functionality in this paper. However, more advanced modulating schemes are preferred in practical application, such as plasma dispersion effect. The following analysis discusses the possibility and challenges. The response spectra are obtained at West output port and North output port with light launched from North input port and West input port respectively. The transmission spectra in the wavelength range from 1542.5 nm to 1549 nm are shown in Fig. 7 . Due to the manufacturing nonuniormity, the maximum difference of the initial resonances for the measured MRRs is 1.25 nm, which is beyond the tuning ability of carrier injection. Thus, to realize the electro-optical tuning MRR-based optical router requires more precise fabrication process, otherwise thermo-optic effect is required to compensate the uncertainty of the initial resonance. Unlike the thermo-optic tuning, carrier injection brings the MRR additional insertion loss, which significantly affects the filtering behavior of the MRR when relatively large wavelength shift is required. Additionally, the change of chip temperature would significantly affect the resonances of MRRs. Some feedback process or temperature control circuits should be involved in such a system based on MRRs.

 figure: Fig. 7

Fig. 7 Response spectra from the North input port to West output port (black line) and from West input port to North output port (red line).

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4.2 High-speed signal transmission experiments

In order to verify the routing functionality of the five-port optical router, 12.5 Gbps high-speed signal transmission experiments are carried out. An MZ intensity modulator is used to externally modulate the continuous wave at the wavelength of 1551 nm. Driven RF signal is a 12.5 Gbps 231-1 pseudo-random bit sequence generated by a pulse-pattern generator. Optical signal is amplified by an erbium-doped fiber amplifier (EDFA) after outputting from the output waveguide of the router. A tunable filter is used to compress the noise induced by the EDFA. Finally, the optical signal is sent to a digital communication analyzer to get eye diagrams. Figure 8 shows the eye diagrams of signals at the output ports for optical links between West port and other four ports. Because the bandwidth of the MRR is enough for 12.5 Gbps signal, we find that no difference exists between the eye diagrams of the signal passing through resonant MRR and that not passing through resonant MRR. Figure 9 shows the bit-error rate (BER) curves in back-to-back mode and for the setups with the signal transmitted in eight optical paths between West port and other three ports. The results of the BER tests show that the maximum power penalty is 1.75 dB at the BER of 10−9.

 figure: Fig. 8

Fig. 8 The 12.5 Gbps eye diagrams for an optical signal at the output ports for eight optical paths between West port and other four ports.

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 figure: Fig. 9

Fig. 9 The 12.5 Gbps BER curves for the signals transmitted between West port and other three ports. A PRBS pattern with a length of 231-1 is used for the BER tests. The back-to-back BER curve is measured by replacing the chip with a variable optical attenuator mimicking the insertion loss induced by the chip.

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5. Conclusion

In conclusion, a spatially non-blocking five-port optical router has been demonstrated for the first time to the best of our knowledge. The optical router is based on microring resonators tuned through the thermo-optic effect. A balanced design is presented to achieve the MRR-based switching element with an approximately symmetric performance in terms of insertion loss, extinction ratio and crosstalk. The optical router is compact in size and has an efficient footprint of 440×660 μm2, which is suitable for photonic NoC. The optical router has a 3-dB bandwidth of larger than 0.31 nm (38 GHz), an extinction ratio of larger than 21 dB for through port, and an extinction ratio of larger than 16 dB for drop port at the 1551 nm operation wavelength. Finally, 12.5 Gbps high-speed signal transmission experiments are carried out to verify the routing functionality of the optical router. Due to the tolerances of the fabrication process, some challenges exist to demonstrate such a device using electro-optic tuning scheme. However, the electro-optic switching scheme is a trend in the future, which can offer more compact structure in size, higher switching speed and lower power consumption.

Acknowledgments

This work has been supported by the National Natural Science Foundation of China (NSFC) under grant 60977037, and by the National High Technology Research and Development Program of China under grant 2009AA03Z416.

References and links

1. R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008). [CrossRef]  

2. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]  

3. T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007). [CrossRef]  

4. H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009).

5. N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008). [CrossRef]   [PubMed]  

6. M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011). [CrossRef]   [PubMed]  

7. R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011). [CrossRef]  

8. A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008). [CrossRef]  

9. A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009). [CrossRef]  

10. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008.

11. H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” Design, Automation & Test in Europe Conference & Exhibition, 3–8 (2009).

12. A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009).

13. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008). [CrossRef]  

14. D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown III, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007). [CrossRef]  

15. A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010). [CrossRef]  

16. Y. Xie, N. Mahdi, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk noise and bit error rate analysis for optical network-on-chip,” 47th ACM/EDAC/IEEE Design Automation Conference, 657–660 (2010).

17. L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010). [CrossRef]   [PubMed]  

18. T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004). [CrossRef]  

19. L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett. 33(21), 2512–2514 (2008). [CrossRef]   [PubMed]  

References

  • View by:

  1. R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
    [Crossref]
  2. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
    [Crossref]
  3. T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
    [Crossref]
  4. H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009).
  5. N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
    [Crossref] [PubMed]
  6. M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
    [Crossref] [PubMed]
  7. R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
    [Crossref]
  8. A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
    [Crossref]
  9. A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
    [Crossref]
  10. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008.
  11. H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” Design, Automation & Test in Europe Conference & Exhibition, 3–8 (2009).
  12. A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009).
  13. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
    [Crossref]
  14. D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
    [Crossref]
  15. A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
    [Crossref]
  16. Y. Xie, N. Mahdi, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk noise and bit error rate analysis for optical network-on-chip,” 47th ACM/EDAC/IEEE Design Automation Conference, 657–660 (2010).
  17. L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
    [Crossref] [PubMed]
  18. T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
    [Crossref]
  19. L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett. 33(21), 2512–2514 (2008).
    [Crossref] [PubMed]

2011 (2)

2010 (2)

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]

L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref] [PubMed]

2009 (2)

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[Crossref]

2008 (5)

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[Crossref] [PubMed]

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]

L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett. 33(21), 2512–2514 (2008).
[Crossref] [PubMed]

2007 (2)

2004 (1)

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]

Agarwal, A.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Assefa, S.

Baba, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]

Baets, R.

Bao, L. W.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Barwicz, T.

Beausoleil, R. G.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]

Bergman, K.

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[Crossref] [PubMed]

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]

Bianco, A.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]

Biberman, A.

Borkar, N.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Borkar, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Brown, J. F.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Byun, H.

Carloni, L. P.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]

Chen, H.

R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]

Chen, L.

Chen, P.

Chin, M. K.

Cuda, D.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]

Dighe, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Ding, J.

Doany, F. E.

Dumon, P.

Edwards, B.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Erraguntla, V.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Fang, Q.

Finan, D.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Fukazawa, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]

Gan, F.

Gaudino, R.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]

Gavilanes, G.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]

Geis, M.

Green, W. M. J.

Grein, M.

Griffin, P.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Hirano, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]

Hoffmann, H.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Holzwarth, C. W.

Hoskote, Y.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Howard, J.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Hoyt, J. L.

Ippen, E. P.

Jacob, T.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Jahnes, C. V.

Jain, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Ji, R.

Ji, R. Q.

Jia, L. X.

Jiang, Z. Y.

Kartner, F. X.

Kash, J. A.

Kuekes, P. J.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]

Lee, B. G.

Lipson, M.

Liu, Y. L.

Lu, Y.

Lu, Y. Y.

Luo, X.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]

Lyszczarz, T.

Mattina, M.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Miao, C. C.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[Crossref]

Neri, F.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]

Ohno, F.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]

Olubuyide, O. O.

Orcutt, J. S.

Petracca, M.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]

Poon, A. W.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]

Popovic, M. A.

Rakich, P. T.

Ram, R. J.

Ramey, C.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Roberts, C.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Ruhl, G.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Schow, C. L.

Shacham, A.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]

Sherwood-Droz, N.

Singh, A.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Smith, H. I.

Snider, G. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]

Spector, S.

Stojanovic, V.

Tian, Y.

Tian, Y. H.

Tobing, L. Y. M.

Tschanz, J.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Van Campenhout, J.

Vangal, S. R.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Vlasov, Y. A.

Wang, H.

Wang, S.-Y.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]

Watts, M. R.

Wentzlaff, D.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

Williams, R. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]

Wilson, H.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

Xu, F.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]

Yang, L.

Yang, M.

Yoon, J. U.

Yu, M. B.

Zhang, L.

Zhou, P.

Zhu, W.

IEEE J. Solid-state Circuits (1)

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]

IEEE Micro (1)

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]

IEEE Photon. Technol. Lett. (1)

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]

IEEE Trans. Comput. (1)

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]

J. Opt. Netw. (1)

Jpn. J. Appl. Phys. (1)

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]

Opt. Express (3)

Opt. Lett. (2)

Proc. IEEE (3)

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[Crossref]

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]

Other (5)

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008.

H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” Design, Automation & Test in Europe Conference & Exhibition, 3–8 (2009).

A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009).

H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009).

Y. Xie, N. Mahdi, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk noise and bit error rate analysis for optical network-on-chip,” 47th ACM/EDAC/IEEE Design Automation Conference, 657–660 (2010).

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Figures (9)

Fig. 1
Fig. 1 Schematics of 2D photonic mesh (a) and torus (b) networks for 16-core CMPs. (c) A five-port bidirectional optical router. Blue square indicates processing core, yellow dot indicates optical router, and line with arrow indicates optical waveguide.
Fig. 2
Fig. 2 Schematic layout of the five-port non-blocking on-chip optical router.
Fig. 3
Fig. 3 (a) and (b) Configurations of microring-resonator-based switching element at OFF state and On state. (c) Normalized transmissions at the through and drop ports. The black dashed line indicates the operation wavelength. Here, the MRR has a radius of 10 μm, loss of 10 dB/cm and coupling coefficient of 0.35. (d) The variation of extinction ratios for through and drop ports with the coupling coefficient.
Fig. 4
Fig. 4 Micrograph of the five-port optical router based on cascaded MRRs.
Fig. 5
Fig. 5 Spectrum responses of the MRRs labeled as R11, R1, R7, R6, R5 and R4 respectively.
Fig. 6
Fig. 6 Transmission spectra involving four resonance peaks of drop ports for MRRs labeled as R11, R1, R7, R6, R5 and R4 in ON state.
Fig. 7
Fig. 7 Response spectra from the North input port to West output port (black line) and from West input port to North output port (red line).
Fig. 8
Fig. 8 The 12.5 Gbps eye diagrams for an optical signal at the output ports for eight optical paths between West port and other four ports.
Fig. 9
Fig. 9 The 12.5 Gbps BER curves for the signals transmitted between West port and other three ports. A PRBS pattern with a length of 231-1 is used for the BER tests. The back-to-back BER curve is measured by replacing the chip with a variable optical attenuator mimicking the insertion loss induced by the chip.

Tables (1)

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Table 1 Twenty Optical Links of the Five-Port Non-Blocking Optical Router

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