In this paper we present a detailed analysis of the carrier lifetime for a p-i-n junction on silicon nano-rib waveguides. Several factors determining efficiency of carriers removal from the waveguiding region will be discussed. We compare different structure geometries and spacings between p and n doped regions to show the way to optimize electrons and holes sweeping for CW nonlinear optical devices.
©2011 Optical Society of America
Recently, silicon has grown as a platform for nonlinear photonic applications. Following effects have been studied by various groups: four-wave mixing (FWM) [1,2], self- and cross- phase modulation (SPM, XPM) [1,3–7], stimulated Raman scattering (SRS) [8–10], two photon absorption (TPA)  and TPA introduced free carrier absorption (FCA) [11–14]. The high interest in silicon stems from the fact that silicon offers a well established technology base for electronics, high index contrast waveguides that enable a large scale of photonic-electronic integration. However, application of nonlinear effects has been hampered by high waveguide losses and free carrier effects. High waveguide losses used to be a pronounced problem of nano-waveguides. Recently, Selvaraya et al.  presented record low linear loss (~0.3 dB/cm) nano-waveguides based on shallow etched rib waveguide geometry. Such waveguides are very promising candidates for advancing nonlinear photonics on silicon. However, so far these waveguides have not been deployed in this area.
Another important issue for nonlinear application of silicon waveguides is high free carrier lifetime in silicon. This is detrimental since it leads to free carrier absorption (FCA). Free carrier lifetime can be reduced by p-i-n structures in waveguides (Fig. 1 ). Free carriers generated by two photon absorption (TPA) are effectively removed from the waveguide due to the high electric field across the intrinsic region of the p-i-n structure.
In this paper we study decreasing FCA in the new type of shallow etched SOI nano-rib waveguides  introduced by Selvaraya et al. We shall deploy well-established electronic device modeling techniques to analyze lifetime reduction in wavguide-integrated p-i-n structures. Our analysis will cover waveguide geometry dependence, junction width, and carrier screening effects. As we shall see, these shallow etched waveguides exhibits several advantages over state-of-the-art deep etched nano-waveguides with regard to free carrier lifetime reduction.
2. Simulation method
Electronic device modeling using commercial software was already applied to carrier lifetime studies in p-i-n waveguide structures . However, the previous electrical studies were focused on larger waveguide structures (down to 0.5 micrometer silicon thickness). The dependence of free-carrier lifetime on etch depth of the rib was not considered. We shall show that rib etch depth is important for the performance improvement of the new type of nano-rib waveguides. Later on, Intel confirmed experimentally the effectiveness of p-i-n structures for reduction of carrier lifetime in silicon waveguides by demonstration of CW Raman laser on SOI . Carrier lifetime in smaller waveguides (295 nm x 660 nm) was studied experimentally later in another work . However , still used deep etched waveguides of single etch depth with comparatively high linear loss ~2 dB/cm. Other work focused on the modeling of longitudinal carrier transport . Our work will provide results of a 2D analysis of the transverse carrier transport components.
Numerical analysis based on the finite element method for carrier recombination and carrier transport in silicon is performed to obtain information about carrier density and velocity. Sentaurus Device semiconductor structures simulation software from Synopsys  is used for simulations. As an input of the simulations we defined waveguide geometry, doping regions and doping levels (Fig. 2(a) ). Due to software constraints modeling we proceed in the following way: Starting point of the simulations is free carrier generation in the waveguide. For two photon absorption, the generation rate is related to intensity ():Eq. (1) unfortunately cannot be directly implemented in the Sentaurus Device program version that we use. Therefore it is separately calculated and entered in the program. Furthermore, instead of the real mode field distribution of the light in the waveguide cross-section we place rectangular window inside the waveguide cross-section, in which the carriers are generated with constant generation rate. The size of the window equals the effective area of the fundamental mode of the waveguide (Fig. 2(b)).
These simplifications lead to some deviation from the situation of the real waveguide. However, the lifetimes we obtain this way correspond well with what has been reported in literature . Also, we may identify trends by relative comparison of obtained lifetimes. When operating waveguide p-i-n structures carrier transport is the dominant lifetime limiting mechanism. From the simulations we obtain electron and hole velocities that we used to calculate effective carriers lifetime and average lifetime according to formulas :12]:
3. Structure geometry and simulation parameters
In our simulations we examine several geometries of SOI nano-rib-waveguides and of p-i-n junctions. The basic structure is presented on the Fig. 2. Three types of waveguides are considered, differing in waveguide etch depth H-s. We also change the distance between p and n regions (intrinsic region width wi) and their respective doping levels. All variations in the geometry have been listed in the Table 1 . For TPA carrier generation we use wavelength of 1455 nm and βTPA equal 0.5 cm/GW. Simulations are performed for an intensity range for I0 from 0 to 1.65 x 109 W/cm2. Reverse bias voltage applied to p-i-n structure varies from 0 to 20 V. This range of voltage allows us to show change in carrier sweeping efficiency in these structures.
4. Simulation results
In this paragraph we present the results of carrier dynamic simulations for nano-rib-waveguide structures. Results were obtained using finite element modeling tool described above. We present the influence of following parameters on carrier removal: width of the intrinsic region of the p-i-n diode, doping level of p and n region, bias voltage, intensity of the incident light and the etch depth of the waveguide.
On the Fig. 3 we present the dependence of carrier lifetime on etch depth and intrinsic region width. For that, we set intensity to 5.22·108 W/cm2 (@1455nm), using a waveguide geometry of 500 x 220 x 50 width, rib height and slab height, respectively (in nanometer). Characteristics of carrier lifetime and FCA vs. light intensity are plotted for different bias voltages and intrinsic region width. We can clearly see that the closer we place p and n region to the waveguide the shorter carrier lifetime we can obtain. Around 108 W/cm2 we observe the onset of carrier density effects. It is important to keep in mind that placing p and n regions too close to the waveguide increases the waveguide propagation loss.
On the other hand, increasing doping levels of p and n contact regions has not much impact on carrier lifetime in our waveguides. That is illustrated in Fig. 4 . The plot shows carrier average lifetime as a function of the bias voltage for two different slab heights and two doping levels in the contact region. The light intensity was set to 5.22 x 108 W/cm2, intrinsic region width was 1.2 µm. This is not surprising because the drift field in the intrinsic region depends very weakly on the doping of the heavily doped areas. We would expect lifetime to depend on the doping of the intrinsic region, which is usually an SOI substrate parameter. We used 1015 cm−3 for the intrinsic level.
Increasing intensity in the waveguide the amount of generated carriers increases. At a certain carrier density (or light intensity, respectively) free carriers start to screen the applied field in the waveguide region. This effect is shown on the Fig. 5 .
After reaching a certain threshold, the carrier screening effect grows rapidly with intensity. We observe a threshold level of about 1x108 W/cm2. In the following graph (Fig. 6 ) we plot the electric field distribution in a waveguide p-i-n structure of 50 and 150 nm slab thickness for a light intensity of 5.22 x 108 W/cm2, and 20 V reverse bias voltage. Carrier screening effect results in a decrease of the electrical field in the waveguide. Since carriers are swept away less efficiently this causes the accumulation of carriers in the waveguide region. The graph also shows the higher field penetration in the shallow etched waveguide structure.
To obtain a better quantitative understanding, we present simulations results regarding etch depth dependence in Fig. 7 . We studied three different slab heights s = 50 nm, 100 nm and 150 nm. Other parameters were waveguide width and height 500 nm and 220 nm respectively and the width of the intrinsic p-i-n diode region of 1200 nm. The results were obtained for intensity of 5.22·108 W/cm2. The bias voltage induces higher fields in the shallow etched structures. Thus, carriers are subject to higher acceleration in the case of shallow etched waveguides and that is why we can use lower voltage to remove the free carriers. Deploying 70 nm etched (slab 150 nm) waveguides provides a clear advantage over their deeper etched counterparts.
As the Next we would like to show how the screening effect can be pushed to the higher intensity with the proper engineering of the waveguide. For that purpose we plot carrier lifetime vs. intensity for different bias voltages, etch depths and intrinsic regions width in Fig. 8 .
The onset of screening can be pushed by increasing bias voltage and by decreasing waveguide etch depth. Comparing the 20V curves in Fig. 8, we see that the threshold intensity for carrier screening can be increased by a factor of 5 if we use the new type of shallow etched waveguides.
The positive effect of shallow-etched waveguides becomes also apparent if we study the figure-of-merit (FOM) for nonlinear optical effects introduced by Turner-Foster et al. . The following formula for the FOM had been presented :Fig. 9 we present the FOM dependence on the bias voltage for deep etched waveguides with 50 nm slab and shallow etched waveguides with 150 nm slab. Both waveguides have width of 500 nm and ridge heights of 220 nm. Characteristics have been calculated for an intensity of 5.22·108 W/cm2, doping levels in the doped regions of 1018 cm−3 and intrinsic region width 1.2 µm.
We observe a clear improvement in the FOM comparing deep and shallow etched waveguides. This is due to the lower propagation loss of shallow etched nano-rib waveguides AND higher carrier removal efficiency.
In his paper we studied the influence of different parameters that appear in the design process of the p-i-n diode on the free carrier removal from silicon waveguides. Impact of parameters such as intrinsic region width, doping level and etch depth of the waveguide, has been examined for different light intensity and bias voltage. We could show that using a recently experimentally demonstrated type of low-loss shallow etched waveguides  will also increase the efficiency of carriers removal from the waveguide region. Thanks to the higher efficiency we can lower voltage maintaining the same effect like in deep etched waveguides. In addition, the shallow etched waveguides proved advantageous from the point of carrier screening in the p-i-n structure. The threshold of carrier screening can be pushed to higher intensities of shallow etched waveguides are deployed. Combination of low linear loss and high efficiency of carrier removal from the waveguide region makes shallow etched waveguides a promising component for realization of nonlinear optical devices on SOI.
This work has been supported by Deutsche Forschung Gemeinschaft (DFG) in the frame of the Forschergruppe FOR 653.
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