We demonstrate a bulk silicon alternative to the conventional silicon-on-insulator photonics platform, using common CMOS process-based Si3N4 masking and oxidation techniques. We show waveguide losses as low as 2.92 dB/cm with a technique that can be implemented on the front-end of a typical CMOS fabrication line.
©2010 Optical Society of America
The case for silicon photonics has been made many times over. Sub-wavelength optical wires fabricated using CMOS (Complementary Metal–Oxide–Semiconductor) materials and techniques will lead the way to feasible and economic integration of optics and electronics. This in turn will open the door to high-bandwidth, low-power interconnects that can be used for applications such as chip multi-processor interconnects or low-jitter chip-wide clock distribution networks . Nevertheless, there is still no consensus as to the specifics of how this integration will happen; only that it needs to happen [2, 3].
One of the main drawbacks of the integration of optics on the transistor layer is the need for extensive cladding material, typically a few micrometers of silica surrounding the silicon core waveguide. Although high-contrast optics in principle occupies small real estate, the optical wire - a typical Si channel waveguide (e.g. 450 nm wide x 250 nm thick), still requires around 1 um of SiO2 cladding on all sides. This optical buffer is needed mainly underneath the waveguide in order to eliminate crosstalk to the nearby substrate. In electronics however, only a small layer of SiO2 is needed. In fact, having more than a few hundred nanometers of SiO2 underneath the Si waveguide creates incompatibility with the CMOS transistor layer, which necessitates thermal conduction through the silicon substrate . Modern processes which use SOI (Silicon-On-Insulator) technology rely on a “thick” silica layer around 70 nm and better transistor performance can be achieved with a 40 nm BOX (Buried Oxide) layer . Yet even with older SOI CMOS stacks which rely on up to a 400 nm BOX , optical losses from radiation would be in the thousands of dB/cm. Comparatively from our simulations 1 μm of BOX would lead to 0.35 dB/cm an d 3 μm would lead to negligible loss assuming chips with several centimeters of waveguides between nodes.
One option for the integration of optics with electronics is the fabrication of the optics layer in the backend of the CMOS stack, alongside the metallization layers , however single-crystalline silicon would not be available as a guiding material, since it cannot be deposited. In addition this approach limits fabrication to low-temperature processes, when done monolithically. Alternatively one could envision using flip-chip bonding; however this would reduce the already limited area reserved for off-chip contacts. Instead it would be preferable if the optics could be built alongside the transistor layer where high-temperature processes are allowed and close contact with electronics is maintained, allowing the architect full flexibility in design.
Here we propose a fabrication process for enabling the integration of optics on the transistor layer. The process is based on the traditional electronic medium, namely a bulk silicon wafer and produces small or non-existing BOX for the electronics while providing an optical buffer for the optics sharing the layer.
2. Process definition and simulation
We generate high quality oxide in bulk silicon beneath our waveguides using thermal oxidation, having protected them with a material with very high oxidation temperature and CMOS compatibility: Si3N4. A similar technique is used in some CMOS fabrication in a process called LOCOS (LOCal Oxidation of Silicon), in which oxide spacers are created between transistors to avoid parasitic effects. LOCOS has been used to make waveguides, though typically they are large ridge waveguides with little confinement [7, 8]. Smith et al. have previously shown the formation of waveguides by excavating air pockets underneath waveguides made of polycrystalline silicon . This process requires depositing the guiding layer since it needs a buffer layer to protect the guiding material from the silicon-etching chemical. By maintaining the original crystalline silicon above our oxide layer we ensure a high quality optical guiding medium is used.
In order to induce oxidation from beneath the waveguide in order to optically isolate the waveguide form its substrate we use a full three-sided nitride cap as a protective cover over an etched pillar that will be formed into the final waveguide (see figure. 1). In electronics a similar process is used referred to as SWAMI (SideWAll Masked Isolation) and is used in some transistor fabrication . Using the Silvaco modeling program Athena we simulate the oxidation growth for our waveguide structure, shown in Fig. 1 . We generally find good agreement in the resulting shape of the structure in these simulations, though the simulation underestimated the oxidation time. In Fig. 1(a) the waveguide-like structure has been clad with Si3N4 and overetched by just under 1 μm before being subjected to oxidation. Under oxidation the structure narrows from either side (Fig. 1(b)) until it separates from the substrate at which point we can begin to see the makings of a “buried oxide layer” in Fig. 1(c). From this point we continue to oxidize for two reasons: 1) to increase the distance from the waveguide to the substrate and 2) to reduce the triangular “tail” of the waveguide to a flat surface as seen in Fig. 1(c). Further flattening can be achieved with increased oxidation time.
The fabrication process relies on a single step of lithography, deposition of Si3N4, etching and oxidation. We begin with a blank silicon wafer (Fig. 2(a) ), on which we deposit a 300 nm layer of Si3N4 using PECVD (Plasma-Enhanced Chemical Vapor Deposition) or LPCVD (Low-Pressure Chemical Vapor Deposition). This layer serves as the top cover of the protective mask (Fig. 2(b)).
We define the waveguide devices using a negative photo or electron-beam lithographic method resulting in a hardened resist material over the areas to be protected (Fig. 2(c)). The waveguides are defined to be 450 nm wide according with our standard geometry to maintain single-mode operation and tight bending radii . These structures are etched vertically down using an ICP (Inductively-Coupled Plasma) or RIE (Reactive-Ion Etching) tool. The results of this step are waveguide-like pillars 600 nm tall with a Si3N4 layer on top. We have made the pillars purposefully taller than the designed waveguide thickness of 250 nm since they need to be oxidized from underneath to create a flat bottom surface (Fig. 2(d)).
As a sidewall protection from the oxidation to the waveguides we deposit another 350 nm of Si3N4 (Fig. 2(e)). The Si3N4 layer is etched the same amount as was deposited. The verticality of the etch leaves Si3N4 on the sidewalls of the pillars. Given the initial layer of Si3N4 left on top we have as a result a three sided mask over all waveguiding structures (Fig. 2(f)). We refer to this step as being self-aligned, since the mask is left only over the waveguides without the need for an additional lithography step. We continue etching into the silicon substrate to reduce the amount of oxidation time and SiO2 generated on the sides (Fig. 2(g)). This step reduces the spacing necessary between adjacent waveguides or directionally coupled devices.
The wafer is placed in a wet oxidation chamber at 1100°C which grows SiO2 in the regions of exposed silicon. The SiO2 reaches underneath the structure creating the BOX layer (Fig. 2(h)). At first a triangular bottom is formed but extended oxidation into the underside of the Si pillars reduces the pinched point into a flat underside (Fig. 2(i)). At 1100°C the oxidation took a total of 16 hours which is a clear limitation but could be reduced considerably with a higher temperature process and by designing a narrower waveguide. The Si3N4 layers can be removed at this point, though from our simulation it does not disturb the mode profile and so we leave it on the waveguide. Finally the structures are clad with 3 μm PECVD SiO2 to complete the surrounding optical buffer (Fig. 2(j)).
The overall shape of the fabricated waveguide itself is rectangular (seen in Fig. 3(a) ) and provides a confined optical mode shown in Fig. 3(b), unaffected by the leftover Si3N4. One can see that using this process we indeed create a sizable BOX layer beneath our crystalline silicon waveguide. Figure 3(c) shows the 3.3 μm BOX layer beneath three adjacent waveguides.
The thicknesses of the two nitride layers were determined through various trials in order to avoid over-etching (visible in the thin top corners of the Si3N4 layer in Fig. 3(a)) that would lead to unwanted oxidation of the waveguides. The thicker cover however, coupled with the 12° sidewall angle produced by our ICP etcher and an additional patterning layer (150nm SiO2 hard-mask) resulted in an increase of the waveguide width. The outcome is a waveguide 740 nm wide. A smaller waveguide can be made in two ways: either writing 160 nm patterns which would result in 450 nm waveguides, or ideally using an etcher with higher verticality that would also reduce the necessary thicknesses of the two Si3N4 layers. Given a perfectly vertical etcher the thickness of each of the Si3N4 layers would need to be slightly over 100 nm each to provide the necessary protection for the given oxidation time .
Finally we tested the fabricated waveguides for propagation losses using the cut-back method. Fiber coupling was used to guide light at the standard telecom wavelength of 1550 nm, incident from the polished edge of the chip. Light was collected at the output edge with a collimating objective and power detector. We observed similar losses for TE and TM modes and report here on unpolarized light. We measured 2.92 dB/cm loss shown in Fig. 4 . From our simulations a BOX greater than 3 μm should result in radiation losses into the substrate of less than 0.001dB/cm. We believe the propagation losses could be significantly reduced with improved etching techniques and should be limited to single crystal silicon waveguide losses. It should be noted that a low quality PECVD Si3N4 was used in these samples which could result in some material absorption. This can easily be resolved through the use of LPCVD Si3N4.
The process described in this paper produces small (sub 1 um width) waveguides with channel geometry, on a common bulk silicon wafer with losses of 2.92 dB/cm, comparable to those of typical SOI waveguides. The waveguides are made of single-crystalline silicon, important for maintaining high contrast guiding in small footprint devices with low losses. The optical layer is made directly on a real CMOS compatible wafer with real CMOS compatible processes, such that it can be integrated in parallel to the transistor layer of a currently fabricated electronics chip. Finally the process requires only one lithography step, thereby reducing the variability in the fabrication of both the photonic material stack as well as the devices.
This work was performed in part at the Cornell NanoScale Facility, a member of the National Nanotechnology Infrastructure Network, which is supported by the National Science Foundation. This work is also partly funded by the Center for Nanoscale Systems, supported by the NSF and the New York State Office of Science, Technology and Academic Research.
References and links
1. A. Shacham, K. Bergman, and L. P. Carloni, “On the Design of a Photonic Network-on-Chip,” in Networks-on-Chip(2007), pp. 53–64.
2. R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008). [CrossRef]
3. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,” (IEEE Computer Society Press, 2009), pp. 8–21.
4. R. Koh, “Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET,” Jpn. J. Appl. Phys. 38(Part 1, No. 4B), 2294–2299 (1999). [CrossRef]
5. C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004). [CrossRef]
6. J. M. Fedeli, M. Migette, L. Cioccio, L. El Melhaoui, R. Orobtchouk, C. Seassal, P. Rojo-Romeo, F. Mandorlo, D. Marris-Morini, and L. Vivien, “Incorporation of a Photonic Layer at the Metallizations Levels of a CMOS Circuit,” in Group IV Photonics, 2006. 3rd IEEE International Conference on(2006), pp. 200–202.
7. F. Y. Gardes, G. T. Reed, A. P. Knights, G. Mashanovich, P. E. Jessop, L. Rowe, S. McFaul, D. Bruce, and N. G. Tarr, “Sub-micron optical waveguides for silicon photonics formed via the local oxidation of silicon (LOCOS),” in Silicon Photonics III(SPIE, San Jose, CA, USA, 2008), pp. 68980R–68984.
8. R. Pafchek, R. Tummidi, J. Li, M. A. Webster, E. Chen, and T. L. Koch, “Low-loss silicon-on-insulator shallow-ridge TE and TM waveguides formed using thermal oxidation,” Appl. Opt. 48(5), 958–963 (2009). [CrossRef] [PubMed]
9. C. W. Holzwarth, J. S. Orcutt, L. Hanqing, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Lasers and Electro-Optics, 2008 and 2008 Conference on Quantum Electronics and Laser Science. CLEO/QELS 2008.(2008), pp. 1–2.
10. D. Andriukaitis, and R. Anilionis, “Thermal Oxidation in LOCOS, PBL, and SWAMI Micro and nano Structures,” (2007), p. 75.
12. T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978). [CrossRef]