We demonstrate a silicon photonic platform using thin buried oxide silicon-on-insulator (SOI) substrates using localized substrate removal. We show high confinement silicon strip waveguides, micro-ring resonators and nanotapers using this technology. Propagation losses for the waveguides using the cutback method are 3.88 dB/cm for the quasi-TE mode and 5.06 dB/cm for the quasi-TM mode. Ring resonators with a loaded quality factor (Q) of 46,500 for the quasi-TM mode and intrinsic Q of 148,000 for the quasi-TE mode have been obtained. This process will enable the integration of photonic structures with thin buried oxide SOI based electronics.
©2010 Optical Society of America
Silicon photonics has emerged as a promising solution for electronic photonic integration [1,2]. Several electronic photonic integrated devices have been demonstrated including GHz modulators [3–6], switches , detectors  and transceivers . All demonstrations so far relied on large buried oxide to achieve optical confinement and low loss waveguiding [3–8]. However, commercial silicon-on-insulator (SOI), complementary metal oxide semiconductor (CMOS) electronics relies on thin buried oxide to reduce short channel effects  and avert thermal problems . Hence, it is of great interest to demonstrate a photonic platform using standard thin buried oxide substrates to achieve intimate integration with front-end-of-line (FEOL) SOI CMOS electronics. In this paper, we demonstrate a high confinement photonic platform using thin buried oxide SOI wafers.
Traditionally, silicon strip waveguides are made on SOI with a thickness less than 260 nm and buried oxide thickness greater than or equal to 1 µm [11–13]. The waveguide width is defined lithographically and etched into silicon with a width less than 500 nm to ensure single-mode operation. The propagation loss reported for such waveguides is between 1 and 5 dB/cm [11,12] with values smaller than 1 dB/cm reported for waveguides made using oxidation smoothing . The buried oxide on which the waveguide rests acts as a barrier preventing light leakage into the substrate and needs to be greater than 1µm to keep the substrate leakage loss to a value lower than 1 dB/cm [14,15]. For integration of waveguides on the same layer as SOI based CMOS, the thickness of buried oxide under the waveguides needs to match that used for electronics. The buried oxide for electronics is thinner and ranges from 100nm  to 400nm .It has been shown previously through simulations  that these buried oxide thicknesses would give losses > 100dB/cm for the strip waveguides.
In this paper, we achieve optical waveguiding on a thin buried oxide SOI wafers using a localized substrate removal method. A buried oxide thickness of 400nm is chosen due to ready availability, with the idea being that demonstration of waveguiding on a buried oxide of 400nm would act as proof of concept for further extension to thinner buried oxide layers. The substrate silicon is removed with an isotropic dry etch using xenon difluoride (XeF2) gas .The approach followed is similar to that used to fabricate polysilicon waveguides above the trench isolation layer of a CMOS process [19,20]. We have demonstrated that this technique can be used to thin buried oxide SOI and that the losses observed are comparable to that of the thick buried oxide SOI wafers. We also report the fabrication of ring resonators with a loaded Q of 46,500 for the TM mode and an intrinsic Q of 148,000 for the TE mode.
2. Localized substrate removal for nanophotonic devices on thin buried oxide SOI
The waveguides and ring resonators are fabricated on the 250 nm thick device layer of a SOITEC SOI substrate with a buried oxide thickness of 400 nm as shown in Fig. 1 . HSQ based negative e-beam resist (XR-1541) of thickness 130 nm is spin coated on top of the device layer. Waveguide are patterned on the resist using a JEOL 9300 e-beam lithography system and developed in AZ 300 MIF developer. The patterns are transferred to the silicon device layer using a Cl2 based ICP etch. Photoresist is then spin coated to a thickness of 3 µm and substrate removal etch windows are patterned using a 5 × i-line stepper. The etch windows are elliptical and are spaced 3 µm away from the waveguides. These windows are etched into the oxide using an RIE etcher with CHF3/O2 gases. The wafer is then diced before the substrate removal etch to allow for coupling through the ends of the waveguide. The substrate removal is performed in a XACTIX etcher by a pulsed xenon difluoride (XeF2) etch recipe to obtain a lateral undercut of 15 µm.
The openings in the oxide act as windows for XeF2 gas to reach the substrate. The undercut of silicon is decided depending on the desired air gap below the waveguide, the spacing between each of the etch windows and the spacing between etch windows and the waveguide. The photoresist protecting the device layer is removed after the XeF2 etch by the use of oxygen plasma. Figure 2 shows the SEM of a waveguide obtained with this process.The SEM shows an undesired undulation of buried oxide below the waveguides. The results presented in this paper are with waveguides on the non-flat oxide surface. The ripples on the buried oxide can be reduced by making the etch holes closer to the optical structure and removing a smaller region of substrate silicon thereby making the suspended region smaller.
3. Experimental setup and results
The transmission of light through the waveguides is measured for both quasi-TE and TM to characterize the waveguides and resonators. Light from a tunable laser is coupled into the waveguides via a polarization controller with the help of a tapered lensed fiber. The waveguides have a nanotaper  at the ends to convert the optical fiber mode into the waveguide mode. The light coming out of the waveguide is collected through a 40 × microscope objective and focused on a detector via a polarizer. A loss of 18 dB is obtained from laser input to the detector for waveguides of 9 mm in length.
3.1 Waveguide loss by cutback method
We obtain propagation losses using a cutback method  by fabricating meandering waveguides of different lengths. The number of bends for each of the waveguides is kept constant and the length of the straight section is increased in order to obtain waveguides of different length .The cutback method is limited by the variations in coupling loss to different waveguides. Figure 3 and Fig. 4 shows the data obtained from 2 different chips from the same wafer for waveguide loss measurement.. The loss obtained from the slope of the linear fit is 3.88 dB/cm for the quasi-TE and 5.06 dB/cm for the quasi-TM mode. This loss is comparable to silicon waveguides fabricated on buried oxide with thickness > 3 µm  showing that the loss due to substrate leakage has been eliminated in our process. The effective index obtained using COMSOL FEM software for the quasi-TE mode is 2.405 and the quasi-TM mode is 1.862 at λ0 = 1550 nm.
The fiber mode is coupled into the waveguide mode by an inverted nanotaper as shown in Fig. 5 . The waveguide is tapered in a parabolic fashion from a size of 90nm at the tip to the waveguide width of 450nm over a distance of 40µm . The loss for two of the nanotapers corresponds to the intercept of Fig. 3 and Fig. 4. The intercept for the TE mode is −14.77 dB corresponding to a loss of 7.385 dB per taper and for TM mode is −16.02 dB which gives a loss of 8.01 dB per taper. As seen from the SEM in Fig. 5, the nanotaper is etched 15 µm from the chip edge by the XeF2 etch. This is because of insufficient photoresist coverage at the edge exposing the tip of the taper to the etching gases. The input light is focused using a tapered lensed fiber held flush with the edge of the chip and having a focusing distance of 14 µm. The width of the taper at the focus is not optimal for coupling into the waveguide mode and leads to high losses. This loss can be reduced in the future by slightly recessing the nanotaper from the edge of the chip thereby ensuring better protection by the photoresist.
3.2 Ring resonators
The transmission spectrum of ring resonators was obtained by sweeping the tunable laser and recording the output of the waveguides from the detector onto a computer. The transmission spectrum for the quasi-TM mode for a ring resonator of radius 7.5 µm with a width of 450 nm and spaced 400 nm away from the waveguide is shown in Fig. 6 . The free spectral range (FSR) for the resonances is used to calculate group index using ng = λ0 2/(FSR∙L) , where λ0 is the free space wavelength and L is the length of the resonator . The measured free spectral range is 10.44 nm from which the group index is calculated to be 4.92 around 1557.6 nm.
The loaded Q of 46,500 is obtained for the resonance shown in Fig. 7 by fitting a Lorentzian. At critical coupling the intrinsic Q is double the loaded Q giving an intrinsic Q of 93,000. Under critical coupling condition, the losses in the ring are calculated from the intrinsic quality factor using [22,23]
3.3 Resonance splitting for quasi-TE mode
The transmission spectrum for a quasi TE resonance of a 7.5 µm radius ring with a width of 450 nm and 150 nm spacing from the waveguide is shown in Fig. 8 . A split resonance is obtained with a center wavelength of 1544.8 nm, a separation of 0.085 nm and an extinction ratio of 12 dB for each of the dips. Split resonances have been observed in ring resonators due to mode coupling between the clockwise and anticlockwise travelling modes . The mode coupling is caused by surface roughness which is introduced due to imperfections on the resist and etching process. The transfer function for the transmitted power to the input power is given by [24,25]Equation (2) assumes that the two coupled resonances modes have the same resonance frequency and quality factor.
The free spectral range observed for the resonances is 11.15 nm and gives a group index of 4.54. The intrinsic quality factor obtained by fitting the measured transmission spectrum to Eq. (2) is 148,000. The propagation loss per unit length obtained from the intrinsic quality factor using Eq. (1) is 5.43 dB/cm.
3.4 Etch hole placement
The xenon di fluoride etch is an isotropic etch. The etch holes need to be spaced such that the depth of silicon removed below the optical devices is large enough to reduce the optical losses. For shorter etches of a few microns, the etch holes need to be placed closer to the center of the device. For the waveguides presented in this paper, the holes were placed 3um to the device in order to accommodate for lithographic misalignment between the silicon device layer mask and the etch hole mask. The size of the opening is limited by the process parameters of depth of etch and etch rate required. The requirement for etch holes can limit the density of integration. However, compared to competing methods, having a single substrate substantially reduces the total footprint and the need for flip chip bonding, area for bond pads etc.
Thermal nonlinearities are also observed in the resonators at input powers of a hundred microwatts. This is because of the high optical quality factors and the only path of heat removal being along the buried oxide to the point where the oxide membrane is anchored to the substrate. By making the etch depth smaller and the etch holes closer, the path for heat leakage to the substrate can be shortened and the effect of nonlinearities can be reduced.
We have demonstrated a photonic platform on thin buried oxide SOI wafers using localized substrate removal. Strip waveguides have been obtained with a loss of 3.88 dB/cm for the quasi-TE and 5.06 dB/cm for the quasi-TM mode. Nanotapers for coupling light in and out of the waveguides have been demonstrated. We have fabricated ring resonators with an intrinsic Q of 46,500 for the quasi-TM and 148,000 for the quasi-TE mode giving a loss of 9.28 dB/cm for quasi-TM and 5.43 dB/cm for the quasi-TE modes. With CMOS scaling, the thickness of the silicon device layer has also been shrinking. The thin device layer would need wider waveguides and wider bend radius to reduce losses for the lower confinement waveguiding structures. The loss values measured for waveguides on the thin buried oxide are comparable to that obtained using thicker buried oxide. This gives the ability to make any nanophotonic device demonstrated on thick buried oxide SOI on a thin oxide CMOS SOI wafer, lowering the barriers to developing a common platform for CMOS electronics and Silicon photonics.
The authors wish to thank Sasikanth Manipatruni, Professor Michal Lipson and the Cornell Nanophotonics Group for useful discussions. This work was supported by the DARPA Young Faculty Award (Grant#: HR0011-08-1-0054) and was performed in part at the Cornell NanoScale Science and Technology Facility (CNF), a member of the National Nanotechnology Infrastructure Network (NNIN) (NSF Grant#: ECS-0335765).
References and Links
1. D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88(6), 728–749 (2000). [CrossRef]
2. M. Lipson, “Guiding, modulating and emitting light on silicon – challenges and opportunities,” J. Lightwave Technol. 23(12), 4222–4238 (2005). [CrossRef]
4. A. Liu, R. Jones, L. Liao, D. Samara-Rubio, D. Rubin, O. Cohen, R. Nicolaescu, and M. Paniccia, “A high-speed silicon optical modulator based on a metal-oxide-semiconductor capacitor,” Nature 427(6975), 615–618 (2004). [CrossRef] [PubMed]
5. S. Manipatruni, Q. Xu, B. Schmidt, J. Shakya, and M. Lipson, “High speed carrier injection 18 Gb/s silicon micro-ring electro-optic modulator,” The 20th Annual Meeting of the IEEE Lasers and Electro-Optics Society, LEOS 2007, 21–25 Oct. 2007, pp. 537–538.
6. C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006). [CrossRef]
7. M. R. Watts, D. C. Trotter, R. W. Young, and A. L. Lentine, “Ultralow power silicon microdisk modulators and switches,” The 5th IEEE International Conference on Group IV Photonics, 17–19 Sept. 2008, pp. 4–6.
8. S. Assefa, F. Xia, S. W. Bedell, Y. Zhang, T. Topuria, P. M. Rice, and Y. Vlasov, “CMOS-integrated high-speed germanium waveguide photodetector for optical interconnects,” Conference on Lasers and Electro-Optics, CLEO2009, 31 May 2009, paper CTuV1.
9. R. Koh, “Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 µm SOI-MOSFET,” Jpn. J. Appl. Phys. 38(Part 1, No. 4B), 2294–2299 (1999). [CrossRef]
10. L. T. Su, J. E. Chung, D. A. Antoniadis, K. E. Goodson, and M. I. Flik, “Measurement and modeling of self-heating in SOI NMOSFET’s,” IEEE Trans. Electron. Dev. 41(1), 69–75 (1994). [CrossRef]
11. M. Gnan, S. Thoms, D. S. Macintyre, R. M. De La Rue, and M. Sorel, “Fabrication of low-loss photonic wires in silicon-on-insulator using hydrogen silsesquioxane electron-beam resist,” Electron. Lett. 44(2), 115–116 (2008). [CrossRef]
13. K. K. Lee, D. R. Lim, L. C. Kimerling, J. Shin, and F. Cerrina, “Fabrication of ultralow-loss Si/SiO(2) waveguides by roughness reduction,” Opt. Lett. 26(23), 1888–1890 (2001). [CrossRef]
14. T. Baehr-Jones, M. Hochberg, C. Walker, and A. Scherer, “High-Q ring resonators in thin silicon-on-insulator,” Appl. Phys. Lett. 85(16), 3346–3347 (2004). [CrossRef]
15. P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bienstman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photon. Technol. Lett. 16(5), 1328–1330 (2004). [CrossRef]
16. J.-T. Park and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Trans. Electron. Dev. 49(12), 2222–2229 (2002). [CrossRef]
17. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron. Dev. 47(12), 2320–2325 (2000). [CrossRef]
18. P. B. Chu, J. T. Chen, R. Yeh, G. Lin, J. C. P. Huang, B. A. Warneke, and K. S. J. Pister, “Controlled pulse-etching with xenon difluoride,” International Conference on Solid State Sensors and Actuators, Transducers’97, 16–19 June 1997, pp. 665–668.
19. C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” Conference on Lasers and Electro-Optics, CLEO2008, 4 May 2008, paper CThKK5.
20. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009). [CrossRef]
22. B. E. Little, S. T. Chu, H. A. Haus, J. Foresi, and J.-P. Laine, “Microring resonator channel dropping filters,” J. Lightwave Technol. 15(6), 998–1005 (1997). [CrossRef]
24. Z. Zhang, M. Dainese, L. Wosinski, and M. Qiu, “Resonance-splitting and enhanced notch depth in SOI ring resonators with mutual mode coupling,” Opt. Express 16(7), 4621–4630 (2008). [CrossRef] [PubMed]
25. Q. Li, Z. Zhang, F. Liu, M. Qiu, and Y. Su, “Dense wavelength conversion and multicasting in a resonance-split silicon microring,” Appl. Phys. Lett. 93(8), 081113 (2008). [CrossRef]