Abstract

In order to achieve high-speed transmission over optical transport networks (OTNs) and maximize its throughput, we propose using a rate-adaptive polarization-multiplexed coded multilevel modulation with coherent detection based on component non-binary quasi-cyclic (QC) LDPC codes. Compared to prior-art bit-interleaved LDPC-coded modulation (BI-LDPC-CM) scheme, the proposed non-binary LDPC-coded modulation (NB-LDPC-CM) scheme not only reduces latency due to symbol- instead of bit-level processing but also provides either impressive reduction in computational complexity or striking improvements in coding gain depending on the constellation size. As the paper presents, compared to its prior-art binary counterpart, the proposed NB-LDPC-CM scheme addresses the needs of future OTNs, which are achieving the target BER performance and providing maximum possible throughput both over the entire lifetime of the OTN, better.

©2010 Optical Society of America

1. Introduction

An efficient use of an OTN throughout its entire lifetime, i.e. from the deployment stage to the end of life, is a main concern to the network providers. As an OTN ages, its quality of service drops gradually. In general, an OTN is equipped with an error-correcting code that provides a large performance margin in order to ensure an acceptable performance as long as the OTN is in service [1]. This, however, translates to underutilization of the resources at the initial stages of an OTN. To elaborate, since an OTN does not need a large performance margin at the beginning of life, instead of overprotecting the payload with unnecessary parity-check bits of an FEC code, we can utilize those bits to increase the throughput. As the quality in the OTN drops due to aging, the protection over the payload can be increased as necessary. Clearly, such a scheme requires code rate adjustments in the FEC module, which cannot be accomplished if the same FEC code is used to protect the data carried over an OTN throughout its lifetime.

In OTNs, neighboring wavelength division multiplexing (WDM) channels can carry traffic to different destinations depending on the network configuration. Therefore, two different WDM channels can have quite different optical signal-to-noise ratios (OSNRs) as signals on these channels are differently impacted by various channel impairments including polarization mode dispersion (PMD), chromatic dispersion, fiber nonlinearities, and filtering effects due to concatenation of optical filters, add/drop multiplexers, and interconnects [1], [2]. Since an OTN is expected to provide a target bit-error ratio (BER) performance regardless of the data destination, protecting data in each channel with an FEC code suitable to that channel is a must. Moreover, a WDM channel might be reconfigured on demand to link different points in the network, which in turn changes the impairments that it is facing tremendously over time. Even though different FEC codes can be used in an OTN to protect data on different WDM channels, unless their code rates can be adjusted according to changing channel conditions, the OTN cannot be utilized at its best performance in terms of data throughput and cost effectiveness.

In order to have seamless integrated transport platforms, in this paper, we propose the use of rate-adaptive non-binary low-density parity-check (LDPC)-coded polarization-multiplexed multilevel modulation with coherent detection. We employ a family of structured codes known as quasi-cyclic (QC) LDPC codes, whose common structural properties can be exploited by unified encoding and decoding architectures to reduce the complexity in implementation. There exist multilevel coded-modulation schemes, i.e. multi-level coding scheme [3], in which each level is protected with irregular LDPC codes whose code rates and degree distributions are optimized at each level to achieve a capacity-approaching performance. Due to the lack of structure in the parity-check matrices of irregular LDPC codes, however, the complexity of the hardware implementation of decoders for irregular LDPC codes is much higher than that of regular or to better put structured LDPC codes [4], [5]. The amount of routing resources required to successfully wire the variable and check nodes of an irregular LDPC code on a hardware platform, e.g. FPGA, ASIC, etc., is either very high or, in some cases, even prohibitive [4], [6]. Thus, structured LDPC codes like 
QC-LDPC codes that lend themselves to partially-parallel hardware implementations that can exploit the structure in the code to enable high-speed and high-throughput decoding are preferable in real-world applications [7]. As the VLSI technology improves, this burden on using irregular LDPC will be removed. However, due to technology limitations and the appealing encoding/decoding advantages and good error correcting performances offered by structured codes, coded-modulation systems with irregular component LDPC codes remain impractical for today’s high-speed and throughput-hungry optical communication systems. Therefore, we restrict our attention in this paper to coded-modulation systems with component LDPC codes which are structured and regular, in particular quasi-cyclic. We should also stress that by using a family of QC-LDPC codes instead of an unrelated set of irregular codes with optimized degree distributions as component codes, decoders with that can support a multitude of code rates can be designed more easily and with minimum hardware resources [8], [9]. We will elaborate more on quasi-cyclic LDPC codes, their properties and advantages in Section 3.

Multilevel modulation and polarization-multiplexing enables us to perform all related coding, signal processing and transmission at lower symbol rates (such as 25 Giga-Symbols/s), where dealing with fiber nonlinearities and PMD is more manageable, while the aggregate rate is kept at 100 Gb/s and above. As we show in the paper, when compared to prior-art bit-interleaved coded-modulation based on binary component codes [10], multilevel modulation based on non-binary component codes reduces latency in the system while providing either much better error correction performance or much lower computational complexity depending on the constellation size. In our rate-adaptive FEC scheme, depending on the OSNR or predicted OSNR in the link, we propose changing the FEC code rate to maximize the data throughput while providing sufficient protection on the payload bits. 
By sufficient, we mean neither an excessive nor an inadequate but just enough amount of protection that can meet the target bit error ratio (BER). Based on initial performance tests and channel information obtained from monitoring channels, we set up look-up tables to match FEC code rates with mutually exclusive OSNR ranges. If the OSNR or the predicted OSNR in the channel falls into the range assigned to the current FEC code rate, then we do not make any modifications on the FEC module. If the OSNR falls below the range that the current FEC code rate can support, then we use the code of the maximum code rate below the current code rate that can sufficiently protect the data. On the other hand, if the channel quality improves (e.g. after network maintenance or reconfiguration), then we increase the FEC code rate to the highest possible code rate that can sufficiently protect data and maximize the throughput. We encapsulate the information pertaining to the type of error correction used to protect the payload bits in the OTN frame header along with the data used for active routing so that the receiving unit can correctly perform decoding, as also mentioned in [2], [11].

We can list the contributions of our paper as follows:

  • 1) To the best of our knowledge, this is the first work proposing a rate-adaptive non-binary-LDPC-coded multilevel modulation scheme for optical transport networks (OTN) in order to simultaneously address the problems of high-speed data transmission and data throughput maximization over the entire lifetime of an OTN. Our proposed scheme accomplishes the first task by using multilevel modulation and the second task by adapting the code rate of the component forward error correction codes depending on the channel conditions and aging effects on the transmission link and the system components.
  • 2) This is the first time column-weight-3 non-binary QC-LDPC (NB-QC-LDPC) codes are being employed in a multilevel coded modulation scheme. Today, column-weight-2 (or cycle) non-binary LDPC codes are the most widely-used class (if not the only class) of non-binary LDPC codes [1215]. As we show in this paper, non-binary coded modulation schemes with component column-weight-3 NB-QC-LDPC codes designed over GF(4), GF(8), and GF(16) offer striking coding gains without requiring one to use complexity-boosting finite fields, like GF(64) or GF(128), in the code design as column-weight-2 codes do [1215].
  • 3) We provide a detailed analysis on the check node processing complexity of an FFT-based non-binary sum-product algorithm (SPA). Even though we used some preliminary results in our previous work [16], this is the first time that we present a thorough analysis on the check node processing complexity. We should also note that we provide an explicit complexity figure instead of stating it in the order of the field order and check node degree.
  • 4) With numerical results obtained through extensive simulations, we provide researchers a benchmark to compare binary and non-binary QC-LDPC-coded modulation schemes. We also accompany these results with complexity comparisons between the two schemes to help researchers better assess their figures of merit.

The rest of our paper is organized as follows. In Section 2, we explain our proposed 
NB-LDPC-CM scheme, describe its transmitter and receiver architectures, and note the similarities and differences between the proposed scheme and the bit-interleaved coded modulation. Section 3 introduces general properties of non-binary QC-LDPC codes, and briefly discusses their construction and decoding algorithms. We provide a detailed discussion on the MD-FFT-QSPA decoding of non-binary LDPC codes along with its complexity analysis in Section 3. In Section 4, we present numerical results and discuss their significance. Finally, Section 6 concludes our paper.

2. Proposed polarization-multiplexed NB-LDPC-CM scheme

Our proposed polarization-multiplexed non-binary-LDPC-coded modulation scheme is similar to its previously proposed binary counterpart based on bit-interleaved LDPC-coded modulation (BI-LDPC-CM) [10]. The similarity becomes more obvious as one compares the transmitter (Tx) and receiver (Rx) architectures of both schemes (see Fig. 1 and Fig. 2 for 
BI-LDPC-CM and NB-LDPC-CM Tx and Rx architectures, respectively). The key differences that the NB-LDPC-CM introduces can be listed as follows: (1) mi, i{x,y}, encoders/decoders corresponding to the i-polarization are combined into a single encoder/decoder, (2) the use of block (de-) interleavers, and binary-to-symbol and vice versa interfaces are eliminated, (3) the extrinsic information exchange between the APP demapper and the LDPC decoder(s) is eliminated. These changes mainly manifest themselves as reduction in the latency and complexity of the overall system. The details of BI-LDPC-CM and, in particular, the details on how iterative data processing between the APP demapper and LDPC decoders is performed can be found in [10]. Thus, below, we elaborate only on the use of the proposed NB-LDPC-CM scheme.

 

Fig. 1 (a) Transmitter and (b) receiver configurations for the BI-LDPC-CM scheme.

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Fig. 2 (a) Transmitter and (b) receiver configurations for the NB-LDPC-CM scheme.

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As depicted in Fig. 2(a), the transmitter accepts two independent streams of data of length Ki, i{x,y}, and encodes each data stream into a codeword with a qi-ary QC-LDPC(Ni,Ki) code where qi=2mi. (We should note that LDPC codes used in x- and y-polarization need not be the same.) At the time instant l, a qi-ary symbol in a given codeword is mapped to a point sl,i=(Il,i,Ql.i)=|sl,i|exp(jϕl,i) in a qi-ary signal constellation by Mapper i. After the outputs of the mapper blocks are modulated using the corresponding dual-drive Mach-Zender modulators (MZMs), they are combined using a polarization beam combiner (PBC). As seen in Fig. 2(a), the same DFB laser, separated by a polarization beam splitter (PBS), is used as the CW source with x- and y-polarizations. We present the receiver architecture employing a coherent detector in Fig. 2(b). At the time instance k, we sample the I- and Q-branches at the symbol rate Rs to obtain r=(rI,rQ) where rI=vI(t=kTs) and rQ=vQ(t=kTs), whereTs=1/Rs. Denoting the transmitted symbol at time instant k as s=(Ik,Qk), we can calculate the symbol log-likelihood ratios (LLRs) as in Eq. (1):

λ(s)=lnP(s|r)P(s0|r)=lnP(r|s)P(s)P(r|s0)P(s0),
where s0 is the referent symbol. (Note that we used Bayes’ rule in the second equality.) These LLRs are used to initialize the corresponding qi-ary LDPC decoders to obtain codeword estimates.

If the symbol rate is set to Rs GS/s, we can achieve 2Rslog2(q) bits/s transmission using the proposed polarization-multiplexed NB-LDPC-CM scheme, where q signifies the finite field order which is also equal to the constellation size of the modulation. For example, using Rs=25 GS/s, we can achieve 100, 150 and 200 Gb/s optical transmission using QPSK, 8-QAM and 16-QAM modulations, respectively.

We should note that apart from the Tx and Rx architectures that we proposed above for LDPC-coded modulation (with component binary or non-binary LDPC codes), various other coded modulation systems can be established. For example, for the binary case, a multi-level coding (MLC) [3] scheme with component binary LDPC codes can also be used to enable high-speed optical communications as shown in [17]. In MLC, code rates and degree distributions of component LDPC codes at each level are optimized such that the resulting coded modulation system with component irregular LDPC codes can achieve a capacity-approaching performance [3]. There are two disadvantages associated with the MLC approach compared to BICM approach [18]. First, as we elaborated the Introduction, the parity-check matrices of irregular LDPC codes with optimized degree distributions possess no structure which could be exploited in hardware implementation of their decoders. This inhibits their practical use in real-world applications. Especially, in optical communication applications, where high-throughput decoders are of critical importance, the structured LDPC codes like QC-LDPC codes are preferred over unstructured ones due to their hardware-friendly encoders/decoders. Second, the MLC scheme has a lower spectral efficiency compared to the BICM scheme. To see this, suppose that we have m levels in an MLC scheme with each level having an LDPC code of code rate Ki/N, 0i<m,where Ki is the information block size at the ith level and N is the codeword length, which is the same for all levels. Then, the spectral efficiency of the MLC scheme is given by (1/N)i=0m1Ki bits/symbol [3]. On the other hand, the BICM scheme achieves a spectral efficiency of m bits/symbol which is larger than the spectral efficiency of the MLC scheme. This manifests itself as a problem for the MLC scheme due to the fact that in order to achieve the same data rate as the BICM scheme, the MLC scheme has to increase the line rate of the transmission. This increase in line rate, in return, increases the deteriorating effects of residual chromatic dispersion, PMD and inter-channel nonlinearities on the received signal. Especially for very high transmission speeds as the ones we consider in our paper, the effects of these impairments become very severe and should be reduced as much as possible [10]. In the non-binary LDPC-coded modulation system, we do not perform iterative processing between demodulator and decoder. Thus, the second problem of MLC, namely the spectral efficiency problem, does not apply in this case. However, the prohibitive hardware complexity of decoders for irregular LDPC codes remains as the bottleneck for the use of optimized irregular non-binary LDPC codes as component codes.

3. Non-binary quasi-cyclic LDPC codes

LDPC codes form a class of linear block codes with the distinguishing characteristic that their parity-check matrices have a low density of non-zero elements [19]. A quasi-cyclic LDPC (QC-LDPC) code can be defined as an LDPC code for which every cyclic shift of a codeword results in another codeword [20]. The generator matrix of a q-ary QC-LDPC code can be represented as an array of circulant sub-matrices of the same size over the finite field (Galois field) of q elements, GF(q) [21]. Due to this favorable quasi-cyclic structure, QC-LDPC codes can encoded in linear time using simple shift-register-based architectures [22]. The parity-check matrices of q-ary QC-LDPC codes can also be put in the form of an array of sparse circulant sub-matrices of equal size over GF(q) as in Eq. (2) [23].

H=[H0,0H0,1H0,ρ1H1,0H1,1H1,ρ1Hγ1,0Hγ1,1Hγ1,ρ1],
where Hi,j, 0i<γ,0j<ρ, is a circulant sub-matrix of H. This modular structure in the parity-check matrices of QC-LDPC codes facilitates the decoding process, and reduces the routing complexity and hence the silicon area consumption in the hardware implementation of their decoders [7]. Such prominent advantages make QC-LDPC codes a particularly important sub-class of LDPC codes.

Sum-product algorithm (SPA) used for decoding binary LDPC codes was generalized to decode q-ary LDPC codes by Davey and MacKay [24]. We refer to this version of SPA as QSPA. In [24], the authors also proposed an efficient implementation of QSPA via fast Fourier transform, in short FFT-QSPA. FFT-QSPA was later analyzed and improved in [25]. We should note that FFT-QSPA is particularly efficient over the non-binary fields whose order is a power of 2 since the complex arithmetic due to FFT can be avoided. To exploit this property, in our paper, we use non-binary LDPC codes over the extension fields of the binary field, i.e. q = 2m for some positive integer m. In order to reduce the computational complexity, a variant of FFT-QSPA that carries out multiplications in the logarithm domain as additions and converts the results back to probability domain via exponentiation operation was proposed in [26]. We use this mixed-domain algorithm here, which we call as MD-FFT-QSPA. We present a detailed discussion on the complexity of MD-FFT-QSPA in Section 3.

If each column (row) of the parity-check matrix of an LDPC code has exactly γ (ρ) non-zero components, then it is a called a (γ,ρ)-regular QC-LDPC code; else, it is said to be irregular. Every LDPC code can be represented by a bipartite graph known as its Tanner graph. The performance of LDPC codes under SPA-based decoding is deteriorated by the short cycles (4-cycles in particular) in their Tanner graphs. Hence, LDPC codes should be designed without such short cycles. In this paper, we follow a two-stage code design technique that we elaborated on below.

As the starting point of our code design, we use girth-6 B-QC-LDPC codes generated as a by-product in the NB-QC-LDPC code design steps discussed in [23]. In [23], the authors first create a large parity-check matrix of girth 6 over GF(q) using the so-called dispersion method. Then, they randomly extract a (γ,ρ)-regular parity-check matrix from this large matrix while avoiding zero matrices to obtain a (γ,ρ)-regular NB-QC-LDPC code. In our design, we treat the large non-binary parity-check matrix of girth 6 discussed above as a binary parity-check matrix, i.e. all nonzero elements are set to 1. We then feed this mother matrix to the second stage. In the first step of the second stage, we use the well-known formula established by Fossorier [27] to extract γ rows and ρ columns of sub-matrices from the mother matrix such that the resulting (γ,ρ)-regular B-QC-LDPC code is of girth 8. In the last step, we assign nonzero elements from the field of interest to the 1s in the (γ,ρ)-regular binary parity-check matrix to construct a (γ,ρ)-regular parity-check matrix for a NB-QC-LDPC code. Various assignment schemes including a general scheme that constructs parity-check matrices for 
NB-QC-LDPC codes are discussed in detail in [28].

As opposed to the current trend of using column-weight-2 (or cycle) non-binary LDPC codes [1215], we employ column-weight-3 NB-QC-LDPC codes in our paper. As we have shown in [28], unlike cycle non-binary LDPC codes, column-weight-3 non-binary LDPC codes do not require the finite field order over which they are designed to be very large, e.g. 64, 128, or even 256 [1215], to perform well. Since the check node processing complexity for cycle codes over finite fields with such large field orders is prohibitively high, simplifications on the original FFT-QSPA was inevitable. To reduce this computational burden, Declercq and his colleagues proposed the extended min-sum (EMS) algorithm [12], [25], which similar to its binary counterpart min-sum SPA, reduces the computational complexity at the expense of some degradation in performance compared to the original decoding algorithm. Since column-weight-3 non-binary LDPC codes do not require the finite field over which they are designed to have very large field orders, the original FFT-QSPA can still be employed preventing any compromise from the error correction performance of the codes. One of the variants of FFT-QSPA called MD-FFT-QSPA, which do not incur any degradation in performance compared to FFT-QSPA, is discussed in the next section.

3. MD-FFT-QSPA decoding algorithm and its complexity analysis

In this section, we provide details on MD-FFT-QSPA and its computational complexity. In Fig. 3 , we depict the operations performed at the check nodes while running MD-FFT-QSPA over GF(q). At each edge of a check node, we perform qlogq additions per FFT/IFFT block and q additions to compute the extrinsic information vector. Hence, we have 2qlogq+q additions per edge. For a check node of edge degree dc, the summation block in the middle performs (dc1)q additions to compute the aggregate sum. Therefore, we perform in total of 2dcq(logq+11/(2dc)) additions in a check node of edge degree dc. We can deduce from this result that the computational complexity of the MD-FFT-QSPA increases as the field order increases.

 

Fig. 3 Operations performed at check nodes during MD-FFT-QSPA-based decoding.

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SPA and its low-complexity variants have been studied extensively [29]. As discussed in [29], there are variants of SPA that reduce computational complexity while incurring some degradation in performance. However, for a fair performance comparison between BI-LDPC-CM and NB-LDPC-CM, we decided to employ an SPA variant that does not incur any performance degradations when compared to the conventional SPA. Since our ultimate goal is hardware implementation of the coded-modulation schemes discussed in this paper, we also took the issues related to finite-precision hardware implementation into account while choosing the binary SPA variant. Out of the algorithms presented in [29], we have three SPA implementations that do not cause any performance degradations: a) tanh-based SPA (tanh-SPA), b) SPA based on Gallager’s approach (G-SPA), and c) Jacobian-based SPA (J-SPA). Since the tanh-based check node update rule involves multiplications, we ignored tanh-SPA due to increased computational complexity. As noted in Section III.B of [29], G-SPA is very suitable for software implementation where infinite precision can be achieved. However, as authors claim and then justify by using density evolution techniques in Section VI.B of [29], G-SPA is sensitive to quantization and round-off errors when implemented in hardware where only finite precision can be used. In addition, G-SPA requires at least 7 bits of precision which is very high for today’s electronics especially at the data rates of interest for optical communications (see [30]). J-SPA, on the other hand, even though being computationally more expensive than G-SPA, does not possess the hardware implementation problem that 
G-SPA suffers from. Furthermore, as shown in [9], [3133], 5-bit or even 4-bit implementation of J-SPA yields plausible results. As shown in [9] and [32], J-SPA is amenable to multi-rate decoder implementations which is an important asset for rate-adaptive systems like the one we describe in our paper. Therefore, in our paper, we decided to use J-SPA-based decoder for binary LDPC codes.J-SPA uses the forward-backward algorithm and some look-up operations to perform check node updates. The complexity of J-SPA is given by 15(dc2) additions per check node of edge degree dc [29]. In Table 1 of [29], the complexity of J-SPA (which is referred to as LLR-BP Jacobian in [29]) is given by 3(dc2) “core” operations where the core operation is stated to take 5 additions in the same table. Thus, the complexity figure of 15(dc2) additions stated above follows. The check node complexity of the J-SPA algorithm used for decoding a (γ,ρ)-regular B-QC-LDPC(N b, K b) code with M b = N bK b check nodes is then 15Mb(ρ2) additions. For a BI-LDPC-CM scheme employing a modulation format with 2m constellation points and using m identical (γ,ρ)-regular B-QC-LDPC(N b, K b) as component codes, the complexity term involves additions.

Tables Icon

Table 1. Parameters of Component NB-QC-LDPC Codes

15mMb(ρ2)

Consider, on the other hand, using a NB-LDPC-CM scheme employing the same modulation format (with 2m constellation points) but using a single component (γ,ρ)-regular q-ary QC-LDPC(N, K) code with M = NK check nodes, where q = 2m. If we use MD-FFT-SPA, the complexity of NB-LDPC-CM scheme is given in terms of additions as follows:

2ρqM(m+11(2ρ)).

In Section 4, we compare NB-LDPC-CM and BI-LDPC-CM schemes by using not only their error correction performances but also their computational complexities, which are calculated based on the tools developed in this section.

4. Numerical results

In this section, we analyze the performances of polarization-multiplexed BI-LDPC-CM and NB-LDPC-CM schemes assuming amplified spontaneous emission (ASE) noise dominated transmission scenario. We begin our study by comparing BI-LDPC-CM scheme with ITU-standard schemes to demonstrate the potential of LDPC-coded modulation. After that, we proceed by comparing BI-LDPC-CM and NB-LDPC-CM schemes from error correction performance point of view. To obtain a thorough understanding, we also perform a comparison between BI-LDPC-CM and NB-LDPC-CM based on their computational complexities. In our simulations employing the BI-LDPC-CM scheme, we used 25 decoding iterations in binary LDPC decoders and performed 3 outer iterations between the APP demapper and LDPC decoders. In NB-LDPC-CM simulations, on the other hand, we used 50 decoding iterations in the non-binary LDPC decoder. (Recall that NB-LDPC-CM is non-iterative; hence, it needs no outer iterations.) We should note that in terms of the total number of iterations allowed for decoding, BI-LDPC-CM has a slight advantage over the NB-LDPC-CM.

To demonstrate the potential of LDPC-coded modulation, we present in Fig. 4 the results of our comparison between BI-LDPC-CM with component codes of various code rates and two ITU-standard FEC codes. We should note that the symbol rate is Rs=25 GS/s and we employ QPSK modulation, and hence, the aggregate data rate attained by the BI-LDPC-CM scheme is 100 Gb/s. As depicted in the Fig. 4, regardless of the code rate of its component code, which ranges from 0.75 to 0.875, BI-LDPC-CM scheme outperforms the ITU-standard rate-0.82 BCH(128,113)xBCH(256,239) turbo-product code (TPC). The coding gain improvement that BI-LDPC-CM scheme provides over another ITU-standard rate-0.82 RS(255,239) + RS(255,223) concatenation code is much larger, i.e. 2.5 dB or more.

 

Fig. 4 BER performance curves for polarization-multiplexed systems employing BI-LDPC-CM with component codes at various code rates. Note that symbol rate Rs = 25 GS/s.

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Table 1 presents the parameters of the component NB-QC-LDPC codes of three different code rates employed in our rate-adaptive scheme. In order to keep the (transmission) data rate constant, we keep the codeword length of component codes, N, the same. This ensures that the impact of channel impairments such as chromatic dispersion, PMD, fiber nonlinearities, etc. on the transmitted signal remains unaffected as the code rates are altered [1]. In addition, by keeping the codeword length the same over the family of component codes, one keeps the frame synchronization circuitry intact and independent of the component code rate adjustments. As shown in Table 1, the column weight (γ) is the same for all component codes. Hence, changing the code rate is tantamount to changing the sub-block size (B) or the row weight (ρ). The intricacies of non-binary multi-rate decoder design deserve its own paper and hence will not be discussed here. One exemplary implementation that can support binary QC-LDPC codes with various sub-block sizes, code rates and even codeword lengths is presented in [8]. Instead, in this paper, we focus our attention on the benefits –from coding gain, decoding latency and complexity perspectives– of using non-binary QC-LDPC codes in place of their binary counterparts as component codes.

As Fig. 5 confirms, LDPC-coded modulation offers even a higher potential to be exploited if it is used with non-binary LDPC component codes rather than component codes over the binary field. We use component codes of code rate 0.875 as the base of our comparison between BI-LDPC-CM and NB-LDPC-CM. Also, we consider three different modulation formats, namely QPSK, 8-QAM and 16-QAM. We can observe from Fig. 5 that NB-LDPC-CM outperforms BI-LDPC-CM regardless of the modulation format used. A close look at Fig. 5 reveals that the coding gain improvement NB-LDPC-CM provides over the corresponding BI-LDPC-CM increases when we increase the constellation size of the modulation format. More specifically, NB-LDPC-CM with a component (3,24)-regular q-ary QC-LDPC(13680, 11970) code provides 0.4 dB and 0.78 dB additional coding gain at the BER of 10−7 compared to the corresponding BI-LDPC-CM with component (4,32)-regular binary QC-LDPC(28800, 25200) codes when 8-QAM, i.e. q = 8, and 16-QAM, i.e. q = 16, modulations are used, respectively. (Note that both binary and non-binary component codes are of girth 8.)Table 2 presents coding gains at the BER of 10−7 along with the net effective coding gains (NECG) at the BER of 10−12, obtained via extrapolation, for NB-LDPC-CM schemes depicted in Fig. 5.

 

Fig. 5 BER performance curves for polarization-multiplexed systems employing NB-LDPC-CM with component codes at various code rates. Note that symbol rate Rs = 25 GS/s.

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Tables Icon

Table 2. Coding Gains (in dB) of NB-LDPC-CM Scheme with Component Codes at Various Code Rates

From Fig. 5 and Table 2, we can conclude that in order to maximize the coding gain improvement offered by NB-LDPC-CM schemes, one can consider adapting not only the component code rates but also the employed modulation format. NB-LDPC-CM offers much higher coding gains than BI-LDPC-CM if modulation formats with high bandwidth efficiencies are used. However, this appealing benefit does not come without an expense since the complexity at the receiver front ends might increase in order to support different modulation formats.

Until now, we focused our attention only on the error correction performance of the corresponding NB-LDPC-CM and BI-LDPC-CM schemes. As the previous paragraph also alluded to, computational complexity is another important aspect apart from the error correction performance. Using the tools developed in Section 3 and the code parameters presented in Table 1, we can also compare the corresponding NB-LDPC-CM and BI-LDPC-CM schemes from the computational complexity standpoint. Let us again use in our analysis the NB-LDPC-CM and BI-LDPC-CM schemes with rate-0.875 component codes for which we performed performance comparison above. If we take the ratio of Eq. (4) with ρ = 24, M = 1710 for NB-LDPC-CM to Eq. (3) with γb = 4, ρb = 32, Mb = 3600 for BI-LDPC-CM, we can introduce a so-called complexity ratio (CR) term to compare the computational complexities of these two coded modulation schemes for different constellation sizes, q = 2m:

CR=2ρqM(m+11(2ρ))15mMb(ρ2)=193752m(m+1148)m193752m(m+1)m.

When m = 2, i.e. QPSK modulation, CR in Eq. (5) becomes 30.4%. That is, NB-LDPC-CM, which performs slightly better than BI-LDPC-CM for QPSK modulation, can achieve this performance with less than one-third of the complexity of BI-LDPC-CM. Setting m = 3 for 8-QAM, we see that CR = 54%. Thus, by using NB-LDPC-CM, we obtain 0.4 dB additional coding gain at the BER of 10−7 over BI-LDPC-CM while reducing the computational complexity by almost 50%. In the 16-QAM case where m = 4, CR = 101.3%; that is, the computational complexities of the two schemes are comparable. However, we should stress here that for the same computational load, NB-LDPC-CM offers 0.78 dB more coding gain at the BER of 10−7 compared to BI-LDPC-CM in addition to reduced latency due to structural simplifications. These are indeed important assets in link budget analysis.

5. Conclusion

We proposed a rate-adaptive polarization-multiplexed multilevel modulation scheme based on component non-binary QC-LDPC codes and coherent detection. Via rate adaptation, we discussed how the proposed scheme can maximize the throughput in the system while providing sufficient amount of protection for combating channel impairments. We briefly explained NB-QC-LDPC codes, which are used as component codes in our multilevel coded modulation scheme, but kept the discussion on the FFT-based decoding of non-binary LDPC codes more detailed to prepare enough tools for our complexity analysis. As our analyses on error correction performance and computational complexity revealed, our proposed scheme not only reduces latency in the system due to symbol-level instead of bit-level processing, but also provides either impressive reductions in computational complexity or striking improvements in coding gain depending of the constellation size when compared to bit-interleaved coded modulation. The trade-off between the computational complexity and coding gain improvement can be adjusted to suit the needs of the system under consideration, which gives the system designers yet another layer of flexibility. As we advocated in this paper, the proposed rate-adaptive polarization-multiplexed NB-LDPC-CM scheme is a strong candidate for FEC modules of future OTNs, which are not only constrained by good BER performance but also ever-increasing throughput demands.

Acknowledgments

The authors would like to thank anonymous reviewers and the Associate Editor for their constructive comments and suggestions that helped improve the quality of this manuscript.

References and links

1. A. J. de Lind Van Wijngaarden, R. C. Giles, S. K. Korotky, and X. Liu, “Rate-adaptive forward error correction for optical transport systems,” Lucent Technologies, Inc., US Patent Application Publication US 2009/0044079 A1, (2009).

2. O. Grestel, L. Paraschis, and P. Lothberg, “Variable forward error correction for optical communication links,” Cisco Technology, Inc., US Patent Application Publication US 2008/0256421 A1, (2008).

3. J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005). [CrossRef]  

4. E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003). [CrossRef]  

5. H. Zhong and T. Zhang, “Block-LDPC: a practical LDPC coding system design approach,” IEEE Trans. Circuits Syst. I 52(4), 766–775 (2005). [CrossRef]  

6. A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity check code decoder,” IEEE J. Solid-State Circuits 37–3, 404–412 (2002).

7. Z. Wang and Z. Cui, “Low-complexity high-speed decoder design for quasi-cyclic LDPC codes,” IEEE Trans. on Very Large Scale Integ. (VLSI) Syst. 15–1, 104 −114 (2007).

8. L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

9. C. P. Fewer, M. F. Flanagan and A. D. Fagan “A versatile variable rate LDPC codec architecture,” IEEE Trans. Circuits Syst. I 54–10, 2240–2251 (2007).

10. I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007). [CrossRef]  

11. R. D. Stieger, “Optical communication system with variable error correction coding,” Blakely, Sokolof, Taylor & Zafman LLP, US Patent Application Publication US 2003/0005385 A1, (2003).

12. A. Voicila, D. Declercq, F. Verdier, M. Fossorier, and P. Urard, “Low-complexity, low-memory EMS algorithm for non-binary LDPC codes,” in Proc. Int. Conf. on Commun., (Institute of Electrical and Electronics Engineers, Glasgow, Scotland, 2007), pp. 671–676.

13. R.-H. Peng, and R.-R. Chen, “Design of nonbinary LDPC codes over GF(q) for multiple-antenna transmission,” in Proc. Military Commun. Conf., (Institute of Electrical and Electronics Engineers, Washington, DC, 2006), pp. 1–7.

14. R.-H. Peng and R.-R. Chen, “Application of nonbinary LDPC cycle codes to MIMO channels,” IEEE Trans. Wireless Commun. 7–6, 2020–2026 (2008).

15. J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008). [CrossRef]  

16. M. Arabaci, I. B. Djordjevic, R. Saunders, and R. M. Marcoccia, “Rate-Adaptive Non-binary-LDPC-Coded Polarization-Multiplexed Multilevel Modulation with Coherent Detection for Optically-Routed Networks,” in Proc. Int. Conf. on Transparent Optical Networks (ICTON), (Institute of Electrical and Electronics Engineers, Azores, Portugal, 2009), Paper no. Tu.B2.2.

17. I. B. Djordjevic and B. Vasic, “Multilevel coding in M-ary DPSK/differential QAM high-speed optical transmission with direct detection,” J. Lightwave Technol. 24(1), 420–428 (2006). [CrossRef]  

18. I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Proposal for beyond 100 Gb/s optical transmission based on bit-interleaved LDPC-coded modulation,” IEEE Photon. Technol. Lett. 19–12, 874–876 (2007).

19. R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory 8(1), 21–28 (1962). [CrossRef]  

20. S. Lin, and D. J. Costello, Jr., Error Control Coding: Fundamentals and Applications (Prentice Hall, 2004).

21. C. L. Chen, W. W. Peterson, and E. J. Weldon Jr., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969). [CrossRef]  

22. Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006). [CrossRef]  

23. L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007). [CrossRef]  

24. M. C. Davey, Error-Correction using Low-Density Parity-Check Codes, Ph.D. dissertation, (University of Cambridge, 1999).

25. D. Declercq and M. Fossorier, “Decoding algorithms for nonbinary LDPC codes over GF(q),” IEEE Trans. Commun. 55–4, 633–643 (2007).

26. C. Spagnol, W. Marnane, and E. Popovici, “FPGA Implementations of LDPC over GF(2m) Decoders,” in IEEE Workshop on Signal Proc. Sys. (Institute of Electrical and Electronics Engineers, Shanghai, China, 2007), pp. 273–278.

27. M. P. C. Fossorier, “Quasi-cyclic low-density parity-check codes from circulant permutation matrices,” IEEE Trans. Inform. Theory 50–8, 1788–1793 (2004).

28. M. Arabaci, I. B. Djordjevic, R. Saunders, and R. M. Marcoccia, “High-rate non-binary regular quasi-cyclic LDPC codes for optical communications,” J. Lightwave Technol. 27–23, 5261–5267 (2009).

29. J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005). [CrossRef]  

30. T. Mizuochi, and Y. Miyata, “LDPC-based advanced FEC for 100 Gbps transmission,” in Digest of the IEEE/LEOS Summer Topical Meetings, (Institute of Electrical and Electronics Engineers, Acapulco, Mexico, 2008), pp. 33–34.

31. M. M. Mansour and N. R. Shanbhag, “High-throughput LDPC decoders,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11–6, 976–996 (2003).

32. M. Rovini, N. E. L’Insalata, F. Rossi, and L. Fanucci, “VLSI design of a high-throughput multi-rate decoder for structured LDPC codes,” in Proc. 8th Euromicro Conf. on Digital System Design, (Institute of Electrical and Electronics Engineers, Porto, Portugal, 2005), pp. 202–209.

33. M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006). [CrossRef]  

References

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  • |

  1. A. J. de Lind Van Wijngaarden, R. C. Giles, S. K. Korotky, and X. Liu, “Rate-adaptive forward error correction for optical transport systems,” Lucent Technologies, Inc., US Patent Application Publication US 2009/0044079 A1, (2009).
  2. O. Grestel, L. Paraschis, and P. Lothberg, “Variable forward error correction for optical communication links,” Cisco Technology, Inc., US Patent Application Publication US 2008/0256421 A1, (2008).
  3. J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
    [Crossref]
  4. E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
    [Crossref]
  5. H. Zhong and T. Zhang, “Block-LDPC: a practical LDPC coding system design approach,” IEEE Trans. Circuits Syst. I 52(4), 766–775 (2005).
    [Crossref]
  6. A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity check code decoder,” IEEE J. Solid-State Circuits 37–3, 404–412 (2002).
  7. Z. Wang and Z. Cui, “Low-complexity high-speed decoder design for quasi-cyclic LDPC codes,” IEEE Trans. on Very Large Scale Integ. (VLSI) Syst. 15–1, 104 −114 (2007).
  8. L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).
  9. C. P. Fewer, M. F. Flanagan and A. D. Fagan “A versatile variable rate LDPC codec architecture,” IEEE Trans. Circuits Syst. I 54–10, 2240–2251 (2007).
  10. I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007).
    [Crossref]
  11. R. D. Stieger, “Optical communication system with variable error correction coding,” Blakely, Sokolof, Taylor & Zafman LLP, US Patent Application Publication US 2003/0005385 A1, (2003).
  12. A. Voicila, D. Declercq, F. Verdier, M. Fossorier, and P. Urard, “Low-complexity, low-memory EMS algorithm for non-binary LDPC codes,” in Proc. Int. Conf. on Commun., (Institute of Electrical and Electronics Engineers, Glasgow, Scotland, 2007), pp. 671–676.
  13. R.-H. Peng, and R.-R. Chen, “Design of nonbinary LDPC codes over GF(q) for multiple-antenna transmission,” in Proc. Military Commun. Conf., (Institute of Electrical and Electronics Engineers, Washington, DC, 2006), pp. 1–7.
  14. R.-H. Peng and R.-R. Chen, “Application of nonbinary LDPC cycle codes to MIMO channels,” IEEE Trans. Wireless Commun. 7–6, 2020–2026 (2008).
  15. J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
    [Crossref]
  16. M. Arabaci, I. B. Djordjevic, R. Saunders, and R. M. Marcoccia, “Rate-Adaptive Non-binary-LDPC-Coded Polarization-Multiplexed Multilevel Modulation with Coherent Detection for Optically-Routed Networks,” in Proc. Int. Conf. on Transparent Optical Networks (ICTON), (Institute of Electrical and Electronics Engineers, Azores, Portugal, 2009), Paper no. Tu.B2.2.
  17. I. B. Djordjevic and B. Vasic, “Multilevel coding in M-ary DPSK/differential QAM high-speed optical transmission with direct detection,” J. Lightwave Technol. 24(1), 420–428 (2006).
    [Crossref]
  18. I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Proposal for beyond 100 Gb/s optical transmission based on bit-interleaved LDPC-coded modulation,” IEEE Photon. Technol. Lett. 19–12, 874–876 (2007).
  19. R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory 8(1), 21–28 (1962).
    [Crossref]
  20. S. Lin, and D. J. Costello, Jr., Error Control Coding: Fundamentals and Applications (Prentice Hall, 2004).
  21. C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
    [Crossref]
  22. Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
    [Crossref]
  23. L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
    [Crossref]
  24. M. C. Davey, Error-Correction using Low-Density Parity-Check Codes, Ph.D. dissertation, (University of Cambridge, 1999).
  25. D. Declercq and M. Fossorier, “Decoding algorithms for nonbinary LDPC codes over GF(q),” IEEE Trans. Commun. 55–4, 633–643 (2007).
  26. C. Spagnol, W. Marnane, and E. Popovici, “FPGA Implementations of LDPC over GF(2m) Decoders,” in IEEE Workshop on Signal Proc. Sys. (Institute of Electrical and Electronics Engineers, Shanghai, China, 2007), pp. 273–278.
  27. M. P. C. Fossorier, “Quasi-cyclic low-density parity-check codes from circulant permutation matrices,” IEEE Trans. Inform. Theory 50–8, 1788–1793 (2004).
  28. M. Arabaci, I. B. Djordjevic, R. Saunders, and R. M. Marcoccia, “High-rate non-binary regular quasi-cyclic LDPC codes for optical communications,” J. Lightwave Technol. 27–23, 5261–5267 (2009).
  29. J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
    [Crossref]
  30. T. Mizuochi, and Y. Miyata, “LDPC-based advanced FEC for 100 Gbps transmission,” in Digest of the IEEE/LEOS Summer Topical Meetings, (Institute of Electrical and Electronics Engineers, Acapulco, Mexico, 2008), pp. 33–34.
  31. M. M. Mansour and N. R. Shanbhag, “High-throughput LDPC decoders,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11–6, 976–996 (2003).
  32. M. Rovini, N. E. L’Insalata, F. Rossi, and L. Fanucci, “VLSI design of a high-throughput multi-rate decoder for structured LDPC codes,” in Proc. 8th Euromicro Conf. on Digital System Design, (Institute of Electrical and Electronics Engineers, Porto, Portugal, 2005), pp. 202–209.
  33. M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
    [Crossref]

2008 (1)

J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
[Crossref]

2007 (2)

I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007).
[Crossref]

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[Crossref]

2006 (4)

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[Crossref]

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[Crossref]

I. B. Djordjevic and B. Vasic, “Multilevel coding in M-ary DPSK/differential QAM high-speed optical transmission with direct detection,” J. Lightwave Technol. 24(1), 420–428 (2006).
[Crossref]

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

2005 (3)

H. Zhong and T. Zhang, “Block-LDPC: a practical LDPC coding system design approach,” IEEE Trans. Circuits Syst. I 52(4), 766–775 (2005).
[Crossref]

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[Crossref]

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[Crossref]

2003 (1)

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[Crossref]

1969 (1)

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[Crossref]

1962 (1)

R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory 8(1), 21–28 (1962).
[Crossref]

Abdel-Ghaffar, K.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[Crossref]

Anantharam, V.

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[Crossref]

Chen, C. L.

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[Crossref]

Chen, J.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[Crossref]

Chen, L.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[Crossref]

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[Crossref]

Cvijetic, M.

Dholakia, A.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[Crossref]

Djordjevic, I. B.

Eleftheriou, E.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[Crossref]

Fong, W.

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[Crossref]

Fossorier, M.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[Crossref]

Gallager, R. G.

R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory 8(1), 21–28 (1962).
[Crossref]

Hou, J.

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[Crossref]

Hu, X.-Y.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[Crossref]

Huang, J.

J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
[Crossref]

Lan, L.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[Crossref]

Li, Z.-W.

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[Crossref]

Lin, S.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[Crossref]

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[Crossref]

Lui, H.

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

Mansour, M. M.

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[Crossref]

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[Crossref]

Milstein, L. B.

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[Crossref]

Nikolic, B.

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[Crossref]

Peterson, W. W.

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[Crossref]

Shanbhag, N. R.

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[Crossref]

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[Crossref]

Shi, C.-J. R.

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

Siegel, P. H.

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[Crossref]

Tai, Y. Y.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[Crossref]

Vasic, B.

Wang, T.

Weldon, E. J.

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[Crossref]

Willett, P.

J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
[Crossref]

Xu, L.

Yang, L.

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

Yeo, E.

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[Crossref]

Zeng, L.

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Figures (5)

Fig. 1
Fig. 1 (a) Transmitter and (b) receiver configurations for the BI-LDPC-CM scheme.
Fig. 2
Fig. 2 (a) Transmitter and (b) receiver configurations for the NB-LDPC-CM scheme.
Fig. 3
Fig. 3 Operations performed at check nodes during MD-FFT-QSPA-based decoding.
Fig. 4
Fig. 4 BER performance curves for polarization-multiplexed systems employing BI-LDPC-CM with component codes at various code rates. Note that symbol rate Rs = 25 GS/s.
Fig. 5
Fig. 5 BER performance curves for polarization-multiplexed systems employing NB-LDPC-CM with component codes at various code rates. Note that symbol rate Rs = 25 GS/s.

Tables (2)

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Table 1 Parameters of Component NB-QC-LDPC Codes

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Table 2 Coding Gains (in dB) of NB-LDPC-CM Scheme with Component Codes at Various Code Rates

Equations (5)

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λ ( s ) = ln P ( s | r ) P ( s 0 | r ) = ln P ( r | s ) P ( s ) P ( r | s 0 ) P ( s 0 ) ,
H = [ H 0 , 0 H 0 , 1 H 0 , ρ 1 H 1 , 0 H 1 , 1 H 1 , ρ 1 H γ 1 , 0 H γ 1 , 1 H γ 1 , ρ 1 ] ,
15 m M b ( ρ 2 )
2 ρ q M ( m + 1 1 ( 2 ρ ) ) .
CR = 2 ρ q M ( m + 1 1 ( 2 ρ ) ) 15 m M b ( ρ 2 ) = 19 375 2 m ( m + 1 1 48 ) m 19 375 2 m ( m + 1 ) m .

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