Electro-optic polymer-clad silicon slot waveguides have recently been used to build a new class of modulators, that exhibit very high bandwidths and extremely low drive voltages. A key step towards making these devices practical will be lowering optical insertion losses. We report on the first measurements of low-loss waveguides that are geometrically suitable for high bandwidth slot waveguide modulators: a strip-loaded slot waveguide. Waveguide loss for undoped waveguides of 6.5 ± 0.2 dB/cm was achieved with 40 nm thick strip-loading, with the full silicon thickness around 220 nm and a slot size of 200 nm, for wavelengths near 1550 nm.
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A slot waveguide consists of two ridges of high index material, such as silicon, narrowly separated from each other by a fully-etched trench, which is to be filled with a lower index material. The fundamental TE optical mode tends to be highly concentrated in the void region between the two ridges due to the dielectric discontinuity . The narrow spacing of the dielectric arms and high field concentration provide fundamental advantages for building electro-optic modulators based on slot waveguide geometries [2–4].
The very first nonlinear polymer-clad silicon slot waveguide Mach-Zehnder modulator reported already achieved a half wave voltage of 0.25V , though at slow speeds. To achieve high-bandwidth modulation, low-resistance electrical contact between the slot arms and the driving electrodes must be made. In the 0.25V result , a series of fully etched contacting arms were used to achieve electrical contact between the slot waveguide and the driving electrodes in a 110 nm thick silicon layer. One problem with this approach was that the contact arms were extremely small, which required electron-beam lithography to fabricate., Also, as will be discussed later, large surface areas exposed to an etching process are likely to have surface-state based electrical conductivity problems. Another approach has been to use photonic crystals to constrain the mode laterally, which shows significant promise .
In this paper, we fabricate and characterize strip-loaded slot waveguides [8,9] with an un-etched silicon layer of ~220 nm and strip-loading thicknesses ranging from 40 to 70 nm. The resultant waveguide dimensions make it suitable to fabricate these waveguide through a photolithography-based CMOS compatible process. In the following sections, we will first discuss the waveguide designs, then present fabrication and metrology details, followed by measurement results. These are, to our knowledge, the first measurements of the waveguide loss of strip-loaded slot waveguides in silicon.
2. Strip-load waveguide design constraints and figures of merit
The strip-loaded silicon slot waveguide consists of two silicon arms (un-etched silicon) each with a wide strip-loading region (partially etched silicon), as shown in Fig. 1 . Electrical contact could then be made by putting metal electrodes on top of the strip-loading at a clearance from the waveguide once the silicon strip-loading is doped. However, the measurements we present here are for undoped, uncontacted strip-loaded slot waveguides. The losses we demonstrate here are likely to be useful starting points for further engineering efforts involving these waveguides.
We chose the thickness of un-etched silicon to be 220 nm because making the silicon too thin makes strip-loading design difficult, while making it too thick makes the waveguide multimode; 220 nm thickness is a good intermediate value that is both single-mode, and supports strip-loading thicknesses of reasonable height. In addition to the thickness of the un-etched silicon layer, there are a number of parameters that define each waveguide. Probably the most important parameter is the width of the slot: a narrower slot will lead to lower drive voltages , but will also be harder to fabricate. In several commonly used processes, for example, slots must be at least 200 nm in size for guaranteed yield . The thickness of the strip-loading region is an important consideration, as it (combined with the doping that will need to be done when building an electro-optic modulator upon waveguide) will determine the electrical resistance. Highly doped silicon can cause increased waveguide loss , therefore, to achieve a given amount conductivity, making the strip-loading thicker and use lower doping concentration is desirable However, the waveguide design becomes more challenging in the presence of thicker strip-loading.
Surface-state based depletion is also anticipated, which makes the effective height of the strip-loading for current flow less than its physical height. For a surface terminated by a chemical oxide, the surface state density is about 1012 cm−2 . These surface states will “pin” the Fermi-level near the center of the band . It should be noted that the surface states would cause more severe depletion in segmented slot waveguide, due to much larger etched surface in the segments region.
In evaluating strip-loaded slot designs, there are several key figures of merit to consider. Most importantly, a well-confined TE0 mode must be supported, and the TE1 mode should be cutoff at the wavelength of interest to keep the waveguide from being multi-mode. Ideally, the TM0 mode would not be supported either, but coupling from the TE0 to TM0 mode is expected to be minimal, so this is less important. Furthermore, for each waveguide, the figure of merit for nonlinear operation should be characterized, which determines the ultimate VπL product that can be achieved . To predict the dispersion properties and modal patterns of these waveguides, we used commercially available full-vectorial mode solver software .
In the case of an un-etched silicon thickness of 220 nm, based on simulations we predict 80 nm to be the maximum thickness that allows reliable strip-loaded slot waveguides to be built; thicker silicon would result in the TE0 mode being cut-off. We use strip-loading thicknesses of 40 nm to 70 nm to be conservative. With an eventual doping concentration of 1018 /cm3, the surface state depletion would be 10 nm, extending for only a fraction of the strip-loading height. Based on this, we predict that this strip-load thickness will be compatible with future high-bandwidth strip-loaded slot waveguide based modulators. Incidentally, we are presuming that the surface state concentration on the silicon to bottom-oxide interface is negligible.
Figure 2 shows dispersion diagram for a strip-loaded slot waveguide with 230 nm wide arms, 200 nm wide slot and 70 nm thick strip-loading. The dimensions were chosen for the waveguide to be reliably built with photolithography and to have a decent value. The refractive index of the cladding material is assumed to be 1.5, which is close to that of the nonlinear polymer [15,16]. The range of wavelength, where the waveguide can operate as single-mode, is also marked. The of this design in 1.5 cladding is 0.19 um−1, which leads to a VπL of 0.79 V-cm assuming r33 = 50 pm/V. The modal pattern of |Ex| in TE0 mode for this waveguide is shown in Fig. 1(a). Simulations indicate similar performance would be seen with cladding refractive index up to 1.7.
3. Fabrication and measurement
The fabrication of the slot waveguides was done on Silicon-On-Insulator (SOI) wafers with two self-aligned photolithography steps on a 193 nm stepper and two Si dry etching steps. The SOI wafers have a 220 nm thick silicon layer, and a 2 µm thick buried oxide layer. The process started with a hardmask of 80 nm High Temperature Oxide (HTO) layer on top of the silicon layer [Fig. 3(a) ]. First, the waveguide arms/slot were patterned [Fig. 3(b)]. In this photolithography step, we varied the exposure doses to account for etch bias of the slot. After that, an RIE silica etch with C4F8 was used to remove the hardmask. The quality of the edges is given by the resist roughness and by the recipe of the hard mask etching. The silicon exposed was then partially etched with HBr gases and the remaining thickness of silicon was measured by ellipsometry. As an example, Fig. 3(c) shows that a 70 nm silicon is left in the etched area, which will finally lead to ~60nm strip-loading.
In the second lithography step, the remaining hardmask served as a self-alignment, so that the resist to slot overlay became non-critical [Fig. 3(d)]. Then a full silicon etch removed the remaining silicon inside the slot and cut the strip-loading so that each waveguide is electrically and optically isolated [Fig. 3(e)]. A 10 nm thin thermal oxide, consuming 4.4 nm silicon , was then employed to smooth the waveguide sidewalls [Fig. 3(f)]. The remaining hardmask and the thin oxide were removed by a 30 nm SiO2 chemical etch [Fig. 3(g)]. After the thin oxide was removed, CDSEM measurements were taken at various sites to determine the actual dimensions of the slots and arms for three different exposure doses in the 1st photolithography step, which were 17.8 mJ/cm2, 19.0 mJ/cm2 and 20.2 mJ/cm2. Finally, another thermal oxidation was done for the purpose of passivation [Fig. 3(h)] which should yield 10 nm oxide and consume another 4.4 nm silicon. The final strip-loading would therefore be 60 nm. With this process, we actually fabricated waveguide with 40nm, 60nm and 70nm strip-loading.
Finally, in order to closely match the expected eventual index of the electro-optic polymers that will be used for actual modulators, we coated the chips in polymethyl methacrylate (PMMA) (MicroChem 950PMMA A 11% solids in Anisole), which has index close to 1.49 and low optical losses on the order of 0.2 dB/cm . A spin-coating was used, typically with spin speed 2000 rpm for 45 seconds, and a bake time of 90 seconds at 180 °C, which should have resulted in a film thickness of the PMMA of 3 μm .
To study the waveguide loss, we put five waveguide runouts with lengths ranging from ~1 mm to ~8 mm. on each chip. A diagram of the runout structure geometry is shown in Fig. 4(a) . Coupling onto the chip is achieved by a series of grating couplers , which had typical 3 dB bandwidths of 35 nm, and a typical insertion loss of 9 dB per coupler. A short section of single-mode ridge waveguide was used to lead the light to the strip-loaded slot waveguide; the coupling between ridge and the strip-loaded slot was achieved with butt-coupler, with losses predicted by FDTD  of 3 dB. A y-junction is present to allow on-chip mixing for an unrelated experiment. According to FDTD simulations, the y-junction introduces 3.6 dB insertion losses to the runouts. Because each runout structure is identical in all respects, except for the length of the slot waveguide, the losses due to the grating couplers, butt-couplers and y-junctions should not affect our measurements of slot waveguide loss. In order to get similar performances for the grating couplers, these waveguide runouts are compactly laid out, so that they take up only a small fraction of the chip and thereby minimize a possible fabrication non-uniformity .
Devices were measured with a fiber-coupled Agilent 81980A laser and 81636B detector. Spectra were taken using the built-in sweeping ability of the laser. The laser power used was 6dBm except as noted elsewhere. Typical fiber-to-fiber insertion losses for the entire testing system, including all fiber wiring, the fiber array, and the integrated optical devices under test were around 35 to 45 dB, which gave us a signal-to-noise ratio of at least 20 dB. On each chip, we tested the five waveguide runouts and fit the spectrum to a quadratic function using the data points near the peak transmission wavelength (the interval was a 40 nm region centered where the wavelength where the optical output signal is at its maximum). Then a regression is employed to fit the peak transmission value extracted from the fitted quadratic function against the waveguide lengths, where we can get waveguide loss in dB per length from the slope of the linear fitting. The linear regression and associated uncertainties in the fitted parameters were computed using standard statistical techniques .
Figure 5 shows example fittings of the spectrum and the linear regressions for two chips we tested. We attribute the slight fluctuations seen on the transmission spectrum to be the results of back-reflections from the grating couplers, the y-junction and the ridge to slot-waveguide butt-coupler. As is evidenced in the low uncertainty of our results, these fluctuations do not impair our ability to measure the waveguide loss of the strip-loaded slot waveguides.
Data from chips with strip-loading of 40 nm, 60 nm and 70 nm are listed in Table 1 . The final strip-loading thickness is estimated by subtracting 8.8 nm from the ellipsometry measurement, which was done on silicon strip-loading before the two successive 10 nm oxidation. The final slot width is estimated by subtracting 8.8 nm from the CDSEM measurement considering that during the following final 10 nm passivation oxidation the slot was effectively widened by 4.4 nm towards both sides. For the chips that were not covered in CDSEM, we did linear interpolation with the slot width versus photolithography dose data points. It should be noted that the maximum deviation in the slot size from 200 nm - 186.4 nm - is not different enough to cause a significant change in mode size or other parameters.
For the same strip-loading thickness the data from chips that have different exposure doses in the 1st photolithography step are also presented in the first two cases. No appreciable nonlinear loss was observed in a control experiment where we varied the laser power from −1 dBm to 6 dBm. It is striking to note that the 40 nm thick strip-loaded waveguides show statistically significantly lower waveguide loss than the waveguides with thicker strip-loading, even when the optical doses are identical. We believe it is likely that thinner strip-loading causes a more confined optical mode–since there is less overlap with the partially etched silicon, lower losses are observed.
We have experimentally demonstrated low loss strip-loaded slot waveguides with photolithography in SOI. The waveguides that we present data for have not been doped or contacted. With low-optical losses, and a relatively thick silicon strip-loading, high bandwidth slot-waveguide electro-optic polymer modulators can be built . We also show elsewhere that with this type of waveguide and proper transmission line design, high-speed low drive-voltage electro-optic modulators with lengths approaching a centimeter and bandwidths of 20 GHz or more can be built . We believe this is an important step towards realizing practical slot-waveguide polymer devices. We have also found that making a thinner strip-loading section appears to lead to lower losses. Future slot-waveguide modulator designs will likely need to trade optical loss against electrical performance to determine the optimal strip-loading thickness and doping concentrations.
The authors would like to thank Gernot Pomrenke, of the Air Force Office of Scientific Research, for his support through an AFOSR Young Investigators Program Grant, FA9550-08-1-0101, and would like to acknowledge support from the National Science Foundation (NSF) STC MDITR Center, DMR0120967 and the Washington Research Foundation.
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