Abstract

We present a 1x4 reconfigurable demultiplexing filter based on cascaded thermally tunable silicon racetrack resonators with ultralow tuning powers. The use of free-standing silicon resonators with undercut structures significantly reduces the tuning power, with a figure of ~2.9 mW per free spectral range. Even with the presence of thermal crosstalk between two adjacent resonators, we demonstrate multiplexing functionality for channel spacings of 200 GHz, 100 GHz, and 50 GHz, with channel wavelengths aligned to International Telecommunication Union (ITU) grid specifications. Crosstalk values for 200 GHz and 50 GHz channel spacings are less than −20 dB and −11.5 dB, respectively. The total power to achieve this performance is in the range of 1.84 mW to 2.4 mW. Such low-power, compact, and reconfigurable filters are particularly useful in chip-scale optical interconnects.

© 2010 OSA

1. Introduction

As clock speeds in computing machines increase, metal wire interconnects become inadequate in terms of power consumption and wire density and optical solutions are envisioned. Silicon photonics in particular is expected to provide an exceptional platform for chip-level interconnect technology [13]. The power budget required is projected to be sub-pJ per bit for an optical link [4,5]. Another constraint for the optical approach is the need for compactness to conserve silicon chip area. In order to provide high bandwidth and low power consumption, wavelength division multiplexing (WDM) is required, as proposed for several on-chip optical networks [58]. Low power and compact multiplexing filters are perceived to be one of the most critical components and are yet to be demonstrated with acceptable performance. There are at least three major challenges to achieve high performance silicon WDM filters in optical interconnects. First, in order to achieve compactness, submicron silicon waveguides, which can have bending radii down to a few microns, are commonly used in silicon WDM filters and these waveguides are very sensitive to fabrication tolerance since the effective index and group index have high variation with dimensional errors from fabrication. For example, 1 nm of dimensional error in waveguide cross section in a ring resonator may result in a wavelength shift of ~100 GHz for a waveguide geometry of ~0.5 µm by ~0.25 µm [9]. Such index variations also increase the channel crosstalk in WDM filters based on gratings or Mach-Zehnder interferometers (MZIs). Second, silicon has a relatively high thermo-optic coefficient (1.86x10−4 /°C), which results in a resonance shift of about 0.1 nm/°C (this occurs for all types of WDM filters). Third, even with the use of submicron silicon waveguides, previously demonstrated WDM filters based on arrayed waveguide gratings and echelle gratings have an area usually >5000 µm2 per channel [1012]. Increasing the channel number may significantly increase the device footprint since the areas for these grating-based devices are usually proportional to the square of channel number. Significant reduction of filter area is required for inter- and intra-chip optical interconnects [4].

Cascaded thermally tunable microcavities may address all of these challenges [13]. Large tunable ranges can be realized by utilizing silicon’s thermo-optic effect, which can compensate resonance variation from both fabrication and environmental temperature fluctuations. Silicon microcavities can have a bending radius down to a few microns, resulting in a channel area possibly less than 100 µm2. In addition, as the resonant wavelength can be tuned individually for each microcavity, the filters can be configurable in both wavelength and channel spacing. Another important advantage is that each microcavity can have independent add-drop functionality and therefore be flexibly positioned on chips. The key challenge, however, is to reduce tuning powers. Previously demonstrated thermally tunable microcavities usually have relatively large tuning powers of 20 mW-100 mW to achieve one free spectral range (FSR) [1319]. For a transmission data rate of 25 Gbps, this thermal tuning power will add up to 1-4 pJ per bit in an optical link. Recently, it was demonstrated that the tuning power can be as low as 2.4 mW per FSR using free-standing silicon microcavities [20,21]. With this amount of power, the energy consumption is about 10-100 fJ/bit for a data rate of 25 Gbps, depending on how large a tuning range is required. These results further validate the use of silicon microcavities in chip-level optical interconnects.

In this paper, we report a 1x4 reconfigurable demultiplexing filter based on cascaded thermally tunable silicon microcavities with ultralow tuning powers. The use of free-standing silicon microcavities with undercut structures significantly reduces the tuning power, with a figure of ~2.9 mW per free spectral range. Even with thermal crosstalk between two adjacent resonators, we demonstrate multiplexing functionality for channel spacings of 200 GHz, 100 GHz, and 50 GHz, with channel wavelengths aligned to International Telecommunication Union (ITU) grid specifications. The achieved channel crosstalk values for 200 GHz and 50 GHz channel spacings are less than −20 dB and −11.5 dB, respectively.

2. Device structure and fabrication

(De)Multiplexing filters can be constructed by cascading silicon microcavities with one common bus waveguide but with individual drop waveguides. Our thermally controlled resonators are realized by putting micro-heaters on top of the resonator cladding [13]. In our previous paper [21], we have presented the design and fabrication of thermally tunable single microcavities with undercut beneath the cavities. Due to excellent thermal isolation by the air gap between the microcavities and substrate silicon, the heating efficiency can be improved about 10 times, compared with devices without undercuts [21]. As shown in Fig. 1 , we have fabricated a four channel WDM filter with cascaded racetrack resonators with undercut structures. In these devices, the resonators have a racetrack shape with straight coupling lengths of 11 µm and bending radii of 10 µm. The edge-to-edge distance between neighboring resonators is 13 µm. There are always concerns about the mechanical stability of the suspended structures. It is seen that the suspended membranes are supported by oxide beams to avoid bending. In general, the thicker the suspended membranes, the more stable the structures in terms of mechanical stability. Our suspended membranes have a total thickness of about 5 µm [21], and very few devices are found broken after full fabrication and polishing. The optical waveguides are designed to be protected by the upper oxide cladding and buried oxide [21]. However, the stress accumulated during the film depositions and undercut release may degrade the optical performance of the micro-resonators.

 

Fig. 1 Tilted top-view SEM for a fully fabricated WDM filter using free-standing resonators.

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3. Heater efficiency and thermal crosstalk

We characterize the heater efficiency and thermal crosstalk by measuring the drop-port transmission spectra with different heating powers. As we apply heating powers on one of the four resonators, thermal crosstalk may induce resonance red shifts in adjacent resonators. We can define Cij (i,j = 1-4) as the resonance shift of resonator j with unit heating power applied on resonator i. Where Cii represents the heating efficiency of heater i, Cij (i ≠ j) presents the information on the thermal crosstalk between resonator i and resonator j. From spectra such as those shown in Fig. 2(a)2(d), we can calculate Cij from the resonance shift as a function of power. We list the measured results in Table 1 . The thermal tuning efficiency is ranged from 2.30 to 2.43 nm/mW. Since the free spectral range is 6.9 nm, the tuning power is on average 2.9 mW per FSR tuning. The thermal crosstalk between two adjacent resonators is about 13%, and it is negligible between resonators not next to each other (i.e., thermal crosstalk is negligible if the edge-to-edge distance between two resonators is more than 57 µm). For easy thermal control, it would be better if there was no thermal crosstalk since every microcavity can be independently tuned. Compared to thermal crosstalk without undercut structures, as reported in Ref [13], undercuts actually increase thermal crosstalk between adjacent resonators. Removing the silicon substrate underneath the resonator forces heating flux in the free standing membranes, resulting in larger thermal crosstalk. However, in our opinion, this should not be a limiting factor to achieving compact WDM filters using free standing microcavities. In chip-level optical interconnects, each add-drop resonator may locate close to its own transmitter/receiver site, therefore far away from each other to avoid thermal crosstalk.

 

Fig. 2 Drop port spectra for resonators 1-4 (a-d) with various heating powers on resonator 1.

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Tables Icon

Table 1. Measured thermal efficiency

4. Demonstration of reconfigurable WDM filter

We demonstrate reconfigurable multiplexing functionality by aligning the four resonant wavelengths to ITU grid wavelengths. Four source-meters are used to drive four heaters. With the heating efficiency from the last section, the resonance shift can be expressed by

Δλ=CP
where Δλand P are the vectors of the required wavelength shift and the applied powers, the matrix Cincludes the elements Cij obtained in the last section. The above equation has already included the effect of thermal crosstalk. From Eq. (1), we calculate the required heating power as

P=C1Δλ

As an example, we present spectra before tuning and after tuning to achieve 200 GHz channel spacing and ITU channels 45-51 in Fig. 3 . The calculated powers from Eq. (2) are (0.30, 0.14, 0.61, 0.62) mW and the experimentally applied powers are (0.32, 0.15, 0.66, 0.71) mW. They agree reasonably well. Total power to achieve this WDM filtering functionality is 1.84 mW. The drop spectra in Fig. 3 are normalized to the maximal power at the through port. The transmissions at resonance approximately represent device insertion loss from the resonators themselves, which are 1.5-2.5 dB for four resonators. The quality factors are 9000 for the first three resonators but 12000 for the fourth resonator. The quality factor variation may come from the gap variation between the bus waveguide and resonators. The worst-case optical crosstalk among four resonators is less than −20 dB, as shown in Fig. 3(b). Reconfigurablity is demonstrated by aligning the four resonances to ITU grid wavelengths with channel spacings of 100 GHz and 50 GHz, as shown in Fig. 4 . For 100 GHz, the chosen wavelengths are channels ITU 37 – ITU 40. For 50 GHz, the chosen wavelengths are ITU 38 – ITU 39, and their 50 GHz offset wavelengths. The total powers applied are 2.4 mW and 2.16 mW for Fig. 4(a) and 4(b), respectively. As we decrease the channel spacing, the optical crosstalk between different channels increases. We achieve <-16 dB and <-11.5 dB crosstalk for 100 GHz and 50 GHz, respectively. Design of narrower bandwidth resonators would reduce the optical crosstalk further. However, this limits the data rates of transmitted signals. Careful trade-off between resonator bandwidth and channel crosstalk needs to be considered in applications. Using high-order coupled-ring resonators can reduce the channel crosstalk, at the expense of higher tuning power and larger device area [22].

 

Fig. 3 (a) Drop port spectra before tuning. (b) Drop port spectra after thermal tuning to achieve 200 GHz channel spacing.

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Fig. 4 Drop port spectra after thermal tuning to achieve 100 GHz (a) and 50 GHz (b) channel spacing.

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5. Discussion and conclusion

In this paper, we demonstrate the feasibility of reconfigurable WDM filtering functionality using cascaded thermally tunable microcavities. We solve the key challenge of tuning power by using free-standing silicon resonators with undercuts. The low thermal tuning power is realized due to the excellent thermal isolation from the air gap between resonators and silicon substrates. As presented in Ref. [21], the tuning time is about ~170 µs, which may be fast enough for tuning the wavelength. Considering the achieved low tuning power of 2.9 mW per FSR for an individual resonator, it would add a maximum power of 11.6 mW to realize fully reconfigurable WDM filters. The demonstrated WDM filters have advantages which include compactness, reconfigurablility, and the ability to compensate resonance variations from both fabrication and temperature variations. However, some challenges still remain, such as closed-loop control of resonances. We note that a few attempts have been made to solve this problem, by either using on-chip temperature sensors [23] or detecting scattering light from ring resonators [24]. Further optimization of thermal control techniques without costing too much power is necessary. Nevertheless, the demonstrated low power/energy consumption in this paper validates the use of silicon microcavities to realize WDM filters in chip-level optical interconnects.

Acknowledgements

The authors acknowledge partial funding of this work by Defense Advanced Research Projects Agency (DARPA) MTO office under UNIC program supervised by Dr. Jagdeep Shah (contract agreement with SUN Microsystems HR0011-08-9-0001). The authors greatly acknowledge Dr. C.-C. Kung, Dr. J. Fong and Dr. B. J. Luff from Kotura Inc. for their work in fabricating of the device and revising the manuscript, and Dr. K. Raj from Sun Labs at Oracle for helpful discussions. The views, opinions, and/or findings contained in this article/presentation are those of the author/presenter and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense. Approved for Public Release, Distribution Unlimited.

References and links

1. R. A. Soref, “The past, present and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006). [CrossRef]  

2. L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

3. B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006). [CrossRef]  

4. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97, 1166–1185 (2009). [CrossRef]  

5. A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009). [CrossRef]  

6. A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008). [CrossRef]  

7. J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009). [CrossRef]  

8. A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009). [CrossRef]  

9. M. Popovic, Theory and design of high-index-contrast microphotonic circuits, PhD thesis, (MIT 2008).

10. J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008). [CrossRef]  

11. F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009). [CrossRef]  

12. T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004). [CrossRef]  

13. P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010). [CrossRef]   [PubMed]  

14. M. Geng, L. Jia, L. Zhang, L. Yang, P. Chen, T. Wang, and Y. Liu, “Four-channel reconfigurable optical add-drop multiplexer based on photonic wire waveguide,” Opt. Express 17(7), 5502–5516 (2009). [CrossRef]   [PubMed]  

15. S. Xiao, M. H. Khan, H. Shen, and M. Qi, “Multiple-channel silicon micro-resonator based filters for WDM applications,” Opt. Express 15(12), 7489–7498 (2007). [CrossRef]   [PubMed]  

16. F. Gan, T. Barwicz, M. A. Popovic, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kartner, “Maximizing the thermo-optic tuning range of silicon photonic structures,” in Photonics in Switching (2007), pp. 67–68.

17. H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008). [CrossRef]  

18. D. Geuzebroek, E. J. Klein, H. Kelderman, and A. Driessen, “Wavelength tuning and switching of a thermooptic microring resonator,” Proc. ECIO, pp. 395–398 (2003).

19. M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic Resonant Microrings (ARMs) with directly integrated thermal microphotonics,” in Proceedings of Conference on Quantum electronics and Laser Science Conference (CLEO/QELS 2009), pp. 1 – 2.

20. J. E. Cunningham, I. Shubin, X. Zheng, T. Pinguet, A. Mekis, and A. V. Krishnamoorthy, “Highly-efficient thermally-tuned resonant filters,” IEEE Summer Topical Meet. On Optical Networks and Devices for Data Centers 18, 8406–8411 (2010).

21. P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010). [CrossRef]   [PubMed]  

22. M. S. Dahlem, C. W. Holzwarth, A. Khilo, F. X. Kartner, H. I. Smith, and E. P. Ippen, “Eleven-channel Second-order silicon microring-resonator filterbank with tunable channel spacing,” in Proceedings of Conference on Lasers and Electro-Optics (CLEO/QELS 2010), paper CMS5.

23. C. T. DeRose, M. R. Watts, D. C. Trotter, D. L. Luck, G. N. Nielson, and R. W. Young, “Silicon microring modulator with integrated heater and temperature sensor for thermal control,” in Proceedings of Conference on Quantum electronics and Laser Science Conference (CLEO/QELS 2010), paper CThJ3.

24. Q. Xu, “Silicon modulator based on coupled microring resonators,” in Integrated Photonics Research, Silicon and Nanophotonics (OSA 2010), paper IWA3.

References

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  1. R. A. Soref, “The past, present and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
    [CrossRef]
  2. L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).
  3. B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
    [CrossRef]
  4. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97, 1166–1185 (2009).
    [CrossRef]
  5. A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
    [CrossRef]
  6. A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
    [CrossRef]
  7. J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
    [CrossRef]
  8. A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
    [CrossRef]
  9. M. Popovic, Theory and design of high-index-contrast microphotonic circuits, PhD thesis, (MIT 2008).
  10. J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
    [CrossRef]
  11. F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
    [CrossRef]
  12. T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
    [CrossRef]
  13. P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010).
    [CrossRef] [PubMed]
  14. M. Geng, L. Jia, L. Zhang, L. Yang, P. Chen, T. Wang, and Y. Liu, “Four-channel reconfigurable optical add-drop multiplexer based on photonic wire waveguide,” Opt. Express 17(7), 5502–5516 (2009).
    [CrossRef] [PubMed]
  15. S. Xiao, M. H. Khan, H. Shen, and M. Qi, “Multiple-channel silicon micro-resonator based filters for WDM applications,” Opt. Express 15(12), 7489–7498 (2007).
    [CrossRef] [PubMed]
  16. F. Gan, T. Barwicz, M. A. Popovic, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kartner, “Maximizing the thermo-optic tuning range of silicon photonic structures,” in Photonics in Switching (2007), pp. 67–68.
  17. H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
    [CrossRef]
  18. D. Geuzebroek, E. J. Klein, H. Kelderman, and A. Driessen, “Wavelength tuning and switching of a thermooptic microring resonator,” Proc. ECIO, pp. 395–398 (2003).
  19. M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic Resonant Microrings (ARMs) with directly integrated thermal microphotonics,” in Proceedings of Conference on Quantum electronics and Laser Science Conference (CLEO/QELS 2009), pp. 1 – 2.
  20. J. E. Cunningham, I. Shubin, X. Zheng, T. Pinguet, A. Mekis, and A. V. Krishnamoorthy, “Highly-efficient thermally-tuned resonant filters,” IEEE Summer Topical Meet. On Optical Networks and Devices for Data Centers 18, 8406–8411 (2010).
  21. P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010).
    [CrossRef] [PubMed]
  22. M. S. Dahlem, C. W. Holzwarth, A. Khilo, F. X. Kartner, H. I. Smith, and E. P. Ippen, “Eleven-channel Second-order silicon microring-resonator filterbank with tunable channel spacing,” in Proceedings of Conference on Lasers and Electro-Optics (CLEO/QELS 2010), paper CMS5.
  23. C. T. DeRose, M. R. Watts, D. C. Trotter, D. L. Luck, G. N. Nielson, and R. W. Young, “Silicon microring modulator with integrated heater and temperature sensor for thermal control,” in Proceedings of Conference on Quantum electronics and Laser Science Conference (CLEO/QELS 2010), paper CThJ3.
  24. Q. Xu, “Silicon modulator based on coupled microring resonators,” in Integrated Photonics Research, Silicon and Nanophotonics (OSA 2010), paper IWA3.

2010 (2)

2009 (6)

M. Geng, L. Jia, L. Zhang, L. Yang, P. Chen, T. Wang, and Y. Liu, “Four-channel reconfigurable optical add-drop multiplexer based on photonic wire waveguide,” Opt. Express 17(7), 5502–5516 (2009).
[CrossRef] [PubMed]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97, 1166–1185 (2009).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

2008 (3)

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

2007 (1)

2006 (3)

R. A. Soref, “The past, present and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

2004 (1)

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Ahn, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Ahn, J.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Apsel, A. B.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Asanovic, K.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Asghari, M.

Baba, T.

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Baets, R.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Batten, A.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Beals, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Beausoleil, R. G.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Bergman, K.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Binkert, N.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Bogaerts, W.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Brouckaert, J.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Carloni, L. P.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Carothers, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Chen, P.

Chen, Y.-K.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Conway, T.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Cunningham, J. E.

P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010).
[CrossRef] [PubMed]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Davis, A.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Dong, P.

Dumon, P.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Fattal, D.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Feng, D.

Feng, N.-N.

Fiorentino, M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Fukazawa, T.

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Geng, M.

Gill, D. M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Green, W. M. J.

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

Grove, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Ho, R.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Holzwarth, W.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Hong, C.-Y.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Horst, F.

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

Hoyt, J. L.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Jalali, B.

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

Jia, L.

Joshi, J.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Jouppi, N. P.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Kartner, F. X.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Khan, M. H.

Khilo, B.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Kimerling, L. C.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Koka, P.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Krishnamoorthy, A. V.

Lexau, J.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Li, D.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Li, G.

P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010).
[CrossRef] [PubMed]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Li, H. Q.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Liang, H.

Lipson, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Liu, J.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Liu, Y.

Martinez, J.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

McLaren, M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Michel, J.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97, 1166–1185 (2009).
[CrossRef]

Moss, C.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Ng, H.-Y.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Offrein, B. J.

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

Ohno, F.

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Orcutt, A.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Pan, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Panepucci, R. R.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Paniccia, M.

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

Patel, S. S.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Pathak, K.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Pomerene, A. T.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Popovic, M. A.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Qi, M.

Qian, W.

Ram, R. J.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Rasras, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Reed, G.

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

Santori, C. M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Schreiber, R. S.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Schwetman, H.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Selvaraja, S.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Shacham, A.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Shafiiha, R.

Shen, H.

Shubin, I.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Smith, H. I.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Soref, R. A.

R. A. Soref, “The past, present and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

Sparacin, D. K.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Spillane, S. M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Stojanovic, V.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Tu, K.-Y.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Van Thourhout, D.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Vantrease, D.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Vlasov, Y. A.

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

Wang, M. R.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Wang, T.

Wang, X.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

White, A. E.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Wong, C. W.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Xiao, S.

Xu, Q.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Yang, L.

Zhang, L.

Zheng, X.

P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010).
[CrossRef] [PubMed]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Appl. Phys., A Mater. Sci. Process. (1)

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

IEEE J. Sel. Top. Quantum Electron. (1)

R. A. Soref, “The past, present and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

IEEE Micro (1)

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

IEEE Microw. Mag. (1)

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

IEEE Photon. Technol. Lett. (2)

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

IEEE Trans. Comput. (1)

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Jpn. J. Appl. Phys. (1)

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Opt. Eng. (1)

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Opt. Express (4)

Proc. IEEE (2)

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97, 1166–1185 (2009).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Proc. SPIE (1)

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Other (8)

F. Gan, T. Barwicz, M. A. Popovic, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kartner, “Maximizing the thermo-optic tuning range of silicon photonic structures,” in Photonics in Switching (2007), pp. 67–68.

M. S. Dahlem, C. W. Holzwarth, A. Khilo, F. X. Kartner, H. I. Smith, and E. P. Ippen, “Eleven-channel Second-order silicon microring-resonator filterbank with tunable channel spacing,” in Proceedings of Conference on Lasers and Electro-Optics (CLEO/QELS 2010), paper CMS5.

C. T. DeRose, M. R. Watts, D. C. Trotter, D. L. Luck, G. N. Nielson, and R. W. Young, “Silicon microring modulator with integrated heater and temperature sensor for thermal control,” in Proceedings of Conference on Quantum electronics and Laser Science Conference (CLEO/QELS 2010), paper CThJ3.

Q. Xu, “Silicon modulator based on coupled microring resonators,” in Integrated Photonics Research, Silicon and Nanophotonics (OSA 2010), paper IWA3.

D. Geuzebroek, E. J. Klein, H. Kelderman, and A. Driessen, “Wavelength tuning and switching of a thermooptic microring resonator,” Proc. ECIO, pp. 395–398 (2003).

M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic Resonant Microrings (ARMs) with directly integrated thermal microphotonics,” in Proceedings of Conference on Quantum electronics and Laser Science Conference (CLEO/QELS 2009), pp. 1 – 2.

J. E. Cunningham, I. Shubin, X. Zheng, T. Pinguet, A. Mekis, and A. V. Krishnamoorthy, “Highly-efficient thermally-tuned resonant filters,” IEEE Summer Topical Meet. On Optical Networks and Devices for Data Centers 18, 8406–8411 (2010).

M. Popovic, Theory and design of high-index-contrast microphotonic circuits, PhD thesis, (MIT 2008).

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Figures (4)

Fig. 1
Fig. 1

Tilted top-view SEM for a fully fabricated WDM filter using free-standing resonators.

Fig. 2
Fig. 2

Drop port spectra for resonators 1-4 (a-d) with various heating powers on resonator 1.

Fig. 3
Fig. 3

(a) Drop port spectra before tuning. (b) Drop port spectra after thermal tuning to achieve 200 GHz channel spacing.

Fig. 4
Fig. 4

Drop port spectra after thermal tuning to achieve 100 GHz (a) and 50 GHz (b) channel spacing.

Tables (1)

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Table 1 Measured thermal efficiency

Equations (2)

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Δ λ = C P
P = C 1 Δ λ

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