A chip-scale optical buffer performs autonomous contention resolution for 40-byte packets with 99% packet recovery. The buffer consists of a fast, InP-based 2x2 optical switch and a silica-on-silicon low loss delay loop. The buffer is demonstrated in recirculating operation, but may be reconfigured in feed-forward operation for longer packet lengths. The recirculating buffer provides packet storage in integer multiples of the delay length of 12.86 ns up to 64.3 ns with 98% packet recovery. The buffer is used to resolve contention between two 40 Gb/s packet streams using multiple photonic chip optical buffers.
©2009 Optical Society of America
All-optical routers have the potential to offer greater bit-rate transparency and protocol flexibility than electrical routers while reducing power consumption . One proposed solution toward realizing these goals is optical packet switching (OPS), which provides an efficient use of bandwidth by multiplexing data packets in time as well as wavelength and is the solution closest to the current Internet Protocol (IP) . However, a remaining challenge in OPS is to resolve contention between packets competing for router resources. In electrical routers packets may be stored indefinitely in RAM. To avoid dropping packets or adding unnecessary latency in optical routers, optical memory, or buffering, is needed.
Previously, there has not been an optical buffering solution that is compact, scalable, and operates with data at high bit rates . Optical memory technology must be able to buffer data from practical packet streams; this includes packet lengths of at least 40 bytes at bit rates of 40 Gb/s and higher with guard bands no more than several nanoseconds in length. At the same time, there are additional considerations such as cost, power consumption, and footprint that would limit the possible success of the technology. Delay line buffers dominate the proposed buffering approaches and have demonstrated successful buffering [4–6], but would offer more promise as a commercial memory element as an integrated technology. Integration has been shown to offer benefits such as lower cost, improved performance and better reliability . Slow light buffers are interesting in the push to reduce footprint [8-9], but have fundamental limitations, largely in the form of a bandwidth-delay limit .
In this paper, we demonstrate the first optical buffering of 40-byte packets of 40 Gb/s data using an on-chip optical buffer. The device consists of an InP-based, fast 2x2 switch and a silicon oxynitride waveguide delay. The buffer is flexible in implementation, but is demonstrated here in the recirculation configuration, thus offering longer storage times in a smaller footprint. A schematic illustrating the use of the buffer elements for packet storage is shown in Fig. 1. A detailed description of the optical buffering device will be provided in Section 2. The experimental results and discussion on the characterization and system demonstrations are presented in Section 3.
2. Device structure and design
2.1 Buffer approach
The chip-scale buffering device presented here has been designed to provide a prototype toward a fully integrated device that offers flexibility in implementation. Two material systems are used to achieve both large gain (InP-based) and high transparency (silica-based). The base buffer cell is comprised of a fast InP 2x2 switch with monolithic amplifiers to compensate for propagation and coupling losses from a silica waveguide delay line. This base cell can be cascaded to allow for simultaneous storage of more packets. The array may be used either as FIFO (first-in-first-out) memory, or can allow for packets to be re-ordered if prioritization is implemented. For the most common packet length of 40 bytes (acknowledgement packets in TCP/IP), the devices should be used in recirculating operation to minimize the number of cells needed. Longer packet lengths are limited in recirculating operation by the length of the delay line, but an array of cells can provide for feed-forward operation (Fig. 1b) and unlimited packet length. With the addition of second read and write ports, the buffer can also be used for speed-up (Fig. 1c). In this report the devices are used as recirculating buffers, both as single base cells and arrayed.
2.2 InP 2x2 switch
The 2x2 switching device affords negligible power penalty for a data rate of 40 Gb/s, the ability to switch within packet guard bands (<2 ns), high extinction ratios (>40 dB) for cascadability, and enough gain to compensate for its own insertion loss as well as that of the delay loop. A semiconductor optical amplifier (SOA) gate matrix is used as the switching structure to guarantee low crosstalk and for fast switching. Four gain amplifiers are monolithically integrated with the six switching amplifiers and are all less than 650 μm to reduce saturation effects. The schematic of the switch with the delay is shown in Fig. 2. Details of the switch operation and characterization were reported previously in .
2.3 Silica recirculation loop
The recirculating loop is the other essential component of the buffer, important for providing nearly transparent delay. A silica-on-silicon buried ridge waveguide of core dimensions 5.5 by 5.5 microns provided the necessary low propagation loss at the small expense of large bend radii. The index contrast using silicon oxynitride was 0.76%, standard for the foundry, ANDevices. The waveguide design is conservatively limited to a minimum bend radius of 6 mm, but was spiralled on the chip to reduce space. The area needed for 2 m of delay is 6.4 cm2. Passive measurements were taken over a wavelength range from 1525 nm to 1575 nm for the silica waveguides to verify that long lengths of delay are possible. Measurements show propagation losses of less than 0.04 dB/cm at 1550 nm, varying less than 0.001 dB/cm over the 50 nm span. Polarization dependent loss for 200 cm of waveguide was approximately 1 dB and chromatic dispersion was approximately 130 ps/nm•km.
3. Results and discussion
3.1 Measurement setup
The InP devices were soldered and wirebonded to aluminum nitride submounts and cooled to approximately 20°C. The silica delay chip was held using a stage with 6 degrees of freedom to align the two pairs of waveguides simultaneously. The optical signal (1560 nm) was modulated and analyzed using an SHF 50 Gb/s BERT with RZ 231-1 pseudo-random bit sequence (PRBS) data at 40 Gb/s. A variable attenuator and a polarization controller were placed in the setup before the device to maintain a TE-polarized input since the amplifiers are polarization dependent. A 1.2-nm bandpass filter was placed before the receiver to reduce the amplified spontaneous emission (ASE).
Optical data packets at 40 Gb/s were generated to test multiple circulations. Layer 2 packet measurements used 40-byte packets that were analyzed with a PC as the BERT cannot synchronize with data that contains long blank spaces. The packet consists of a 32 bit idler, 64 bit identifier, 8 bit label, and 216 bits of repeated PRBS 27-1. The label strings allowed for packet reordering and the identifiers were evaluated upon receipt for bit errors to determine if the packet was recovered. The switch timing was synchronized with the packet arrival using a payload envelope detect circuit and field programmable gate array (FPGA) based board.
3.2 Device characterization
The photonic chip buffer is comprised of the InP switch and silicon oxynitride waveguide delay and achieved 64 ns of packet storage (5 circulations). The total loop loss without gain is estimated to be 30 dB; composed of 8 dB of silica propagation loss, 14 dB for two couplings between the chips, and the remainder from the InP circuit losses. The four amplifiers in the path provide slightly more gain for one circulation, but the buildup of amplified spontaneous emission (ASE) lessens the gain for greater numbers of circulations. In order to find the optimal input power and the dynamic range of the buffer, the power penalty at a BER of 10-9 was measured for one circulation. Figure 3a shows that the dynamic range was approximately 15 dB, thus making it practical for system use and allowing for multiple devices to be cascaded. Negative power penalty was observed due to the reduction of noise between packets from the gating SOAs as well as from slight pulse reshaping from the SOAs. Packet memory was then tested with the photonic chip buffer and 5 circulations (64 ns) was reached with 98% packet recovery (98% of packet identifier strings having no incorrect bits) (Fig. 3b).
3.4 Contention resolution
The remaining demonstrations used two on-chip buffers cooperating to resolve contention. The buffers ran autonomously using a payload envelope detect circuit to discern upcoming contention, an arbiter to make buffering decisions, and electronic channel processors to send signals to the buffer device. Buffer operation without pre-programmed switching was important to demonstrate that the buffers would be successful in a larger system, specifically a router linecard. To enable autonomous operation, half of the incoming data was split to payload envelope detect (PED) circuits that give the two electronic channel processors (ECP) knowledge of packet arrival (Fig. 4). Each ECP sends port requests to the arbiter board (ARB) which tracks the packets and performs logic. The arbiter sends signals to the ECPs which send gating control signals to the optical buffers for read, write, or bypass state operation.
The first experiment used buffers on two separate channels to perform contention resolution under autonomous control. A stream of three packets was used to exercise several buffering states (Fig. 5). The buffers were required to delay a total of four of the six packets (three packets on each channel) in order to avoid temporal collisions at the output port when the two streams were combined (tunable delay lines (TDL) were set to make the distance to the buffer the same for both arms). The sensitivity packet measurements show that all packets had greater than 99.5% packet recovery (Fig. 6). Several of the packets show negative power penalty due to the gating performed by the switch which will decrease the ASE level and also reshaping from the amplifiers as seen in device bit error rate measurements.
The second experiment demonstrated the use of two photonic chip buffers inline on one channel to provide contention resolution for an empty channel, and more importantly show simultaneous multiple packet storage. Inline the two buffering devices represent one buffer with two memory cells. The firmware in the arbiter was changed to reflect the new positions and roles of the buffers, whereas all hardware remained the same except that the buffers were placed inline (Fig. 7). The same stream of three packets was sent through the first buffer in which the third packet was buffered for one time slot. The stream then passed through the second buffer which delayed the first and third packet for one time slot and the second packet for two time slots (Fig. 8). Greater than 99% packet recovery was measured for all packets (Fig. 9). The results for the concatenated buffers were slightly better than the parallel buffers, due to better alignment between the InP and silica chips.
The packet capacity and maximum storage time of this buffering approach can be increased to provide a realistic solution for optical routing. Recent work in buffer sizing shows that with little sacrifice in performance, optical core routers can be equipped with much less memory capacity than what is currently used in electrical routers. Enachescu et al. report that 10–20 packet buffers may be sufficient for 80–90% link utilization if there are many aggregate flows which can serve to smooth burstiness . Although more conclusive work is needed, optical buffering appears to be more practical than was initially assumed.
The optimization of the amplifier material platform and a decrease in loop losses are highly important. In order to lengthen the storage time the output saturation power of the amplifiers should be increased and, even more importantly, the noise figure should be decreased. The key to a low noise figure is a decreased internal loss, especially for amplifiers with small confinement factors. In addition, a decrease of 15 dB of total loop loss would result in increasing the maximum number of circulations from 5 to 25 for a noise figure of 6, assuming an OSNR of 20 dB is required. This decrease in loop loss may be realized by reducing the coupling loss between the InP and silica waveguides using spot size converters.
The first on-chip optical buffer for 40-byte packet lengths and a bit rate of 40 Gb/s demonstrated successful contention resolution between two packet streams. A single memory element showed up to 5 circulations, or 64 ns of storage, with 98% packet recovery. Significant increases in storage time can be made with simple improvements to reduce the loop loss and the noise figure of the amplifiers. Autonomous contention resolution was performed with 99% packet recovery for a packet capacity of 2, as well as for 2 separate buffered channels. The results presented used the buffers in a recirculating configuration, but the buffer can also be used in feed-forward operation for longer packet lengths. These strengths show that optical buffering elements consisting of SOA-gated switches and silica waveguides offer a promising solution for populating buffers in optical routers. Multiple delay lines can be efficiently packed into the same size by interleaving waveguides in the same spiral. Consequently, up to 100 such buffers could be integrated onto a single die.
This work is supported by DARPA and the Army under contract #W911NF-04-9-0001. The authors thank J. Shah, M. Haney, and W. Chang for helpful discussions.
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