The fastest ever 6Gb/s real-time FPGA-based optical orthogonal frequency division multiplexing (OOFDM) transceivers utilizing channel estimation are experimentally demonstrated, for the first time, with variable power loading being incorporated to effectively compensate for the rapid system frequency response roll-off effect. The implemented transceivers are constructed entirely from off-the-shelf components and incorporate crucial functionalities of on-line performance monitoring and live optimization of key parameters including signal clipping, subcarrier power and operating conditions of directly modulated DFB lasers (DMLs). Real-time end-to-end transmission of a 6Gb/s 16-QAM-encoded OOFDM signal over 300m OM1 multi-mode fiber with a power penalty of 0.5dB is successfully achieved in an intensity-modulation and direct-detection system employing a DML.
©2009 Optical Society of America
Since the original proposal of the concept of optical orthogonal frequency division multiplexing (OOFDM) in 2005 , great effort has been expended on investigating the transmission performance of various OOFDM variants for different optical network scenarios including long-haul systems [2,3], metropolitan area networks [4,5] and local area networks [6,7], this is because the OOFDM technique has demonstrated a number of unique and inherent advantages including, for example, great resistance to dispersion impairments, efficient utilization of channel spectral characteristics, potential for cost-effective implementation due to the rapid advances in modern digital signal processing (DSP) technology, dynamic provision of hybrid bandwidth allocation in both the frequency and time domains, and significant reduction in optical network complexity.
However, all the experimental works reported so far [1–7] have been undertaken using off-line DSP approaches, which do not consider the limitations imposed by the precision and speed of practical DSP hardware required for realizing real-time OOFDM transmission. The experimental demonstration of real-time OOFDM transceivers is critical for not only rigorously evaluating the OOFDM technique but also establishing a solid platform for exploring the feasibility of the technique for practical implementation in optical networks of various architectures. The implementation of highly complex, computationally intense and high-speed signal processing algorithms with sufficient precision and the availability of high-speed data converters with large number of quantization bits are the major challenges in experimentally demonstrating real-time OOFDM transceivers. It is, however, noted that multi-gigabit real-time OOFDM receivers have been demonstrated in coherent transmission systems, where off-line DSP approaches are still adopted in corresponding transmitters [8,9].
In April 2009, we made a significant breakthrough in experimentally demonstrating the world-first real-time OOFDM transceivers based on real-time DSP implemented with Altera Stratix II GX field-programmable gate arrays (FPGAs) . The implemented transceivers support real-time end-to-end transmission of a 1.5Gb/s differential quadrature phase shift keying (DQPSK)-encoded OOFDM signal over a 500m multi-mode fibre (MMF)-based, intensity-modulation and direct-detection (IMDD) system incorporating a directly modulated DFB laser (DML) . In May 2009, considerable improvement in the real-time OOFDM transceiver architectures was made, and real-time end-to-end transmission of a 3Gb/s DQPSK-encoded OOFDM signal with a bit error rate (BER) as low as 3.3×10−9 was successfully achieved over a 500m MMF with excellent performance robustness to various offset launch conditions [11,12]. In June 2009, we proposed, implemented and experimentally verified a novel pilot subcarrier-assisted channel estimation technique , which offers a number of salient features including high accuracy, low complexity, small pilot bandwidth usage, excellent stability and buffer-free data flow. Based on the channel estimation technique, 3Gb/s 16-quadrature amplitude modulation (QAM)-encoded real-time end-to-end OOFDM transmission has been demonstrated, in one case over a 75km MetroCor single-mode fibre (SMF) with a −2dB power penalty in a DML-based IMDD system without in-line optical amplification and chromatic dispersion compensation . As strong evidence of the accuracy of the proposed channel estimation technique, BERs as low as 1.0×10−10 have been observed . In July 2009, the fastest ever 6Gb/s real-time OOFDM transceivers using 16-QAM encoding in a DML-based IMDD MMF transmission link was achieved and announced in the presentation of our OECC’2009 postdeadline paper .
In this paper, the 6Gb/s real-time 16-QAM OOFDM transceiver architecture is reported in detail. The design is an adaptation of a previously reported architecture using DQPSK at 3Gb/s [11,12]. 16-QAM encoding/decoding is also utilised by incorporating the novel pilot subcarrier-assisted channel estimation technique developed and rigorously validated in . In addition, a variable power loading scheme is also implemented experimentally here, for the first time, in real-time OOFDM signal transmission. Furthermore, enhanced functionalities of on-line performance monitoring and live parameter optimisation are exploited. The improved transceiver architecture provides opportunities for not only the use of high modulation formats but also the on-line performance monitoring of the system frequency responses, based on which variable power loading on different subcarriers can be performed providing pre-equalisation to compensate for any amplitude variations in the system frequency response. Live parameter optimisation provides an effective means of optimising, during signal transmission, key parameters including, for example, signal clipping, subcarrier amplitude and operating conditions of DMLs. The live optimisation is conducted based on on-line monitoring of individual subcarrier BER and total channel BER.
With the improved OOFDM transceiver design, the fastest ever real-time end-to-end transmission of 6Gb/s 16-QAM-encoded OOFDM modulated data is achieved over 300m OM1 MMFs in DML-based IMDD transmission systems. Here, it is worth emphasising that such ground-breaking results are obtained by adopting
- • Off-the-shelf electrical components including FPGAs, digital-to-analogue converters (DACs) and analogue-to-digital converters (ADCs)
- • Cost-effective conventional optical components such as DMLs
- • Worst-case OM1 MMFs
- • An extremely simple single-channel IMDD system configuration without utilising optical amplification and mode-selective techniques .
2. Real-time OOFDM transceiver architecture and experimental system setup
Figure 1 shows the detailed architectures of the real-time transmitter (top) and the real-time receiver (bottom) implemented in FPGAs. As detailed descriptions of the real-time transceiver architectures using DQPSK have already been made in , here an outline of the real-time transceivers using 16-QAM is provided with emphasis being given to the practical implementations of channel estimation, variable power loading and improved functionalities of on-line performance monitoring and live parameter optimisation.
2.1 IFFT/FFT logic function
The core algorithms required for OFDM signal processing are the inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT). We have developed our own custom implementation of a 32 point IFFT/FFT logic function employing a radix-2 decimation-in-time structure consisting of 2-point butterfly elements as the core computational building blocks [10–14]. To achieve high-speed performance, the IFFT/FFT logic function design is based on a highly pipelined architecture using a number of extensively paralleled processing stages. In comparison with using commercially available functions, the self-developed IFFT/FFT logic function has a number of salient advantages listed as followings :
- • Full control and optimisation of key logic function parameters. The parameters include computational precision at each stage of the IFFT/FFT function, as well as clipping and quantization of output samples.
- • Ease of scalability for accommodating a larger number of subcarriers and excellent adaptability for supporting higher clock speeds.
- • Control of FPGA logic resource usage.
2.2 Real-time transmitter
In the transmitter, the 32 point IFFT logic function supports 32 equally spaced subcarrier frequencies of which 15 are located in the positive frequency bins occupying the whole Nyquist band, therefore no oversampling is adopted for the system considered in this paper. A 56-bit wide parallel pseudo random bit sequence of length 88,500 words (4.779x106 bits) is employed as information data. One extra parallel bit sequence of a fixed 4-bit wide pattern is used to represent pilot data. To maximise the signal to noise ratio of the received pilot data in the receiver, the fixed pilot pattern corresponds to one of the four diagonal end points of the 16-QAM constellation. Prior to feeding 15 16-QAM encoders, the pilot data is embedded in the information data in such a way that the pilot data occurs on successive subcarriers in consecutive OOFDM symbols . Such pilot data allocation allows highly accurate, interpolation-free channel estimation on all the subcarriers across the entire signal spectrum. In addition, it does not require buffering of the information data transported on the other subcarriers, as there are always 14 subcarriers available in each symbol to convey information data. The 60-bit wide data constructed from the information and pilot data bit sequences is employed to feed the 15 parallel 16-QAM encoders. The peak signal amplitude is fixed for each encoder according to the power loading distribution in use. To control the total signal power the amplitudes of the 15 subcarriers, carrying either the encoded information data or pilot data, can be adjusted with a common scaling factor stored in the embedded memory, which can be updated during live data transmission via the JTAG interface. Such live amplitude adjustment can also be easily extended to allow independent subcarrier power control, which is crucial for implementing advanced power and bit loading algorithms .
At the input of the IFFT, the aforementioned 15 subcarriers and one extra subcarrier having zero power at zero frequency are arranged to satisfy the Hermitian symmetry with respect to their complex conjugate counterparts. The self-developed IFFT logic function is then employed to perform the IFFT to all the 32 subcarriers. At the output of the IFFT, real-valued OOFDM symbols having 32 samples are produced.
After the IFFT, the 32 signed, real-valued samples are clipped and quantized. The clipping level is also stored in the embedded memory and can be updated, during live transmission, to optimise the transceiver performance. The number of quantization bits is set to 8 to match the resolution of the employed DAC. To mitigate the inter-symbol interference (ISI) effect caused by optical dispersion, a cyclic prefix of 8 samples is added to each symbol, giving rise to 40 samples per symbol. The internal system clock is set to 100MHz, and the parallel signal processing approach results in a 100MHz symbol rate. The 100MHz symbol rate and 40 samples per symbol give a sample rate of 4GS/s. The signed samples are converted to unsigned values by adding an appropriate DC offset, as the DAC requires positive values only. After performing sample ordering and bit arrangement, the unsigned 40 samples are streamed to the DAC interface at 4GS/s. The entire symbol consisting of 320 bits is fed in parallel to 32 high speed 10:1 dedicated hardware serialisers, the interface thus consists of 4 samples transferred in parallel at a rate of 1GHz, giving the required aggregated sample rate of 4GS/s. The DAC generates an analogue electrical OOFDM signal having a maximum peak-to-peak voltage of 636mV, the electrical signal is then used to directly modulate a DML, as described in Section 2.4.
2.3 Real-time receiver
At the receiver, after performing optical-to-electrical conversion using a PIN, the analogue electrical signal is amplified as necessary, low pass filtered and then digitised by an 8-bit ADC operating at 4GS/s. A digital interface, which is identical to that of the DAC in the transmitter, transfers the digital samples at 4GS/s to the second FPGA. The 32 high-speed, 1:10, dedicated hardware deserialisers capture 40 received samples in parallel. Bit rearrangement and sample ordering is also performed to reconstruct the samples in the correct order. As required by the FFT function, the samples must be converted to signed values by subtracting the corresponding ADC DC level.
Symbol synchronisation is vital to ensure that the 40 parallel samples captured by the deserialisers in the receiver originate from the same symbol generated in the transmitter. Symbol synchronisation is performed by continuous transmission of symbols of known fixed patterns over the transmission system. By using the FPGA embedded logic analyser (SignalTap II) via a JTAG connection to a PC, the captured samples of the fixed pattern symbols can be viewed, thus the sample offset is determined and subsequently compensated by adjusting the inserted sample offset accordingly. It should be pointed out, in particular, that such a symbol synchronisation process is performed only once at the establishment of a transmission connection.
After symbol synchronisation, the first 8 samples of each of the captured symbols are removed, as they correspond to the cyclic prefix added in the transmitter. This gives rise to 32 samples per symbol for input to the 32 point FFT function, which determines the phase and amplitude of each subcarrier.
At the FFT output, 15 subcarriers in the positive frequency bins are selected for channel estimation and subsequent data recovery. As described in detail in , at the start of transmission, the position of a symbol with its first subcarrier being the pilot subcarrier is first detected, which is regarded as a pilot subcarrier reference point. Based on the reference point, all the pilot subcarriers in the subsequent symbols can be identified easily based on their fixed relative positions. Making use of the assigned and received pilot subcarriers, the system frequency response, (k= 1, 2, …Ns ), can be obtained by performing the operation given below13]. It should be noted that all other channel estimation parameters that are not explicitly mentioned above, are taken to be the values identical to those presented in .
Having obtained the system frequency response, channel equalization is conducted using the following operation13]. In addition, use is also made of the measured system frequency response to adjust the subcarrier amplitude in the transmitter to enable the implementation of variable power loading.
The recovered bit sequence is analysed by a BER logic function. Both the total channel bit error count and the individual subcarrier error counts over 88,500 symbols are continuously measured, updated and displayed with the BER analyser. This allows the calculation and display of the total channel BER, , and the subcarrier BER, , which have the following relationship
For the current transceiver design, system clocks for both the transmitter and the receiver are generated from a common reference source. The FPGAs use a 100MHz reference clock and both the DAC and ADC use a 2GHz reference clock. Here, it is worth mentioning that, very recently we have proposed and theoretically verified a high-speed and accurate synchronisation technique, which automatically performs clock recovery and symbol alignment in the FPGA of the receiver without requiring highly stable and expensive voltage controlled oscillators. The implementation and transmission performance of such an advanced clock recovery technique in the real-time OOFDM transmission systems is beyond the scope of the present paper and will be reported elsewhere in due course.
2.4 Experimental system setup
Figure 2 shows the real-time experimental system setup. The voltage level of the electrical signal from the DAC is first attenuated as required to provide, after voltage to current conversion, an optimum modulating current. The optimised modulating current is then combined with an adjustable DC bias current to drive a single-mode 1550nm DFB laser with a 3-dB modulation bandwidth of approximately 10GHz and a maximum optical output power of about 0dBm. The OOFDM signal emerging from the DML is coupled, via a SMF patch chord, to a variable optical attenuator, which is utilized to control the optical power launched into the MMF link. The attenuated optical signal is coupled, via a mode-conditioning patch cord, into a 300m 62.5/125μm OM1 MMF having a 3-dB optical bandwidth of approximately 675MHz∙km and a linear loss of 0.6dB/km.
At the receiver, the OOFDM signal transmitted through the MMF link is detected using a MMF pigtailed, 20GHz PIN detector with TIA. The PIN has a receiver sensitivity of −17dBm (corresponding to 10Gb/s non-return-to-zero data at a BER of 1.0×10−9). The optical-to-electrical converted signal is first amplified with a 2.5GHz, 20dB RF amplifier, then attenuated as necessary to optimise the signal amplitude to suit the ADC’s input range of ±250mV. Such adjustment also provides electrical gain control to compensate for optical signal attenuation. After passing through an electrical low-pass filter, the signal is converted via a balun to a differential signal and then digitized by a 4GS/s, 8-bit ADC in the receiver.
3. Experimental results
As already discussed in Section 2, with the 100MHz FPGA operating speeds and the 4GS/s sample rates of the DAC/ADC, the fastest ever 6Gb/s real-time OOFDM signals are produced when 16-QAM is taken on all the 15 information-bearing subcarriers. It should be pointed out, in particular, that the obtained 6Gb/s transmission capacity can be utilised almost entirely to carry useful data. This originates from the following three facts: 1) the 6Gb/s signal bit rate is obtained after subtracting the transmission capacity corresponding to the cyclic prefix from the raw signal line rate of 7.5Gb/s; 2) as described in Section 2.3, subcarrier-assisted channel estimation requires an extremely low overhead, and 3) no other training sequences are employed in the transmission system. In this section, extensive use is made of the 6Gb/s 16-QAM-encoded OOFDM signals to explore: 1) the effectiveness of the variable power loading scheme, and 2) the transmission performance of the 6Gb/s 16-QAM-encoded real-time OOFDM signals over the DML-based IMDD OM1 MMF system illustrated in Fig. 2. The performance and stability of the channel estimation technique has already been presented in detail in , therefore no further discussions on such a topic are made in this paper. All the experimental measurements presented in this section are based on an optimised DFB bias current of 37mA, which gives an optical output power of −4.2dBm.
3.1. Effectiveness of the variable power loading scheme
The measured frequency responses of the transmission systems from the IFFT in the transmitter to the FFT in the receiver are shown in Fig. 3 for two different scenarios: a) a transmission system with the 300m OM1 MMF being considered, and b) an analogue back-to-back case, where the electrical attenuator in the transmitter is directly connected to the low-pass filter in the receiver, as shown in Fig. 2. In obtaining Fig. 3, equal digital subcarrier amplitudes in the transmitter are applied, and the resulting frequency responses are normalised to the first subcarrier power. It can be seen from Fig. 3 that the system frequency responses decay very rapidly within the signal spectral region from 0.125GHz to 1.875GHz. Comparisons between the curves for these two frequency responses imply that the system frequency response roll-off effect is mainly due to effects of the analogue electrical elements including, for example, DAC output filtering and the sin(x)/x response inherent to a zero-order hold DAC output, as the associated digital electronics have flat frequency responses. In addition, as demonstrated in Fig. 3, the inclusion of optical components in the transmission system decreases further the frequency response in the high frequency region. The 300m MMF employed is the major contributor to the optical component-induced frequency response roll-off effect, as both the DFB modulation bandwidth and the PIN bandwidth are much larger than that corresponding to the 300m MMF. The observed rapid system frequency response roll-off effect indicates that the use of variable power loading is essential to achieve acceptable BERs over all subcarriers.
In the 300m MMF transmission system, the implementation and effectiveness of the variable power loading scheme are explored in Fig. 4 , where the received digital subcarrier amplitudes prior to channel equalization are plotted against subcarrier number for the cases of utilising equal power loading and variable power loading. In Fig. 4, the variable power-loaded digital subcarrier amplitudes in the transmitter are also given, together with the relative error bits defined as a percentage ratio between the total number of detected error bits on a specific subcarrier and the corresponding total number of error bits aggregated over the entire transmission channel.
It can be seen in Fig. 4 that, for equal power loading, the received digital subcarrier amplitudes are very similar to the system frequency response presented in Fig. 3, thus resulting in significant amplitude differences between the low and high frequency subcarriers. As a direct result, the complex values of the low frequency subcarriers at the output of the FFT may overflow the range of the 8-bit signed value, whilst the constellation points of the high frequency subcarriers may start to merge together. The severity of the above-mentioned phenomena can be easily understood by examining Fig. 5 , where the constellations recorded before channel equalization in the receiver are shown for the 1st, 8th and 15th subcarriers. In such a case, the measured total channel BER is worse than 1.0×10−2.
In sharp contrast, experimental measurements show that the total channel BER can be reduced significantly to a value as low as 3.4×10−4 when use is made of a variable power loading scheme, which just consists of three discrete power levels, as seen in Fig. 4. For a specific transmission system, the subcarrier amplitude at each level is adjusted to ensure that similar error bits occur over different subcarriers and the total channel BER is also minimized simultaneously. As shown in Fig. 4, the optimised stair-like subcarrier amplitude distribution in the transmitter brings about a reduced variation in received subcarrier amplitude, and more importantly, an almost uniform distribution of relative error bits over different subcarriers. The resulting constellations recorded prior to channel equalisation (corresponding to a total channel BER of 3.4×10−4) for the 1st, 8th and 15th subcarriers are given in Fig. 6 , in which clearly distinguishable constellations are observed. The above analysis indicate that variable power loading is very effective in compensating for the system frequency response roll-off effect, and that the use of a coarse variable power loading scheme with just three power levels is sufficiently accurate for the systems of interest of the present paper.
It is worth mentioning that, experimental investigations are currently being undertaken using adaptive power and bit loading algorithms on each subcarrier to further improve the real-time transceiver performance. Results will be reported elsewhere in due course.
3.2. Transmission performance of 6Gb/s real-time 16-QAM-encoded OOFDM signals with variable power loading
Based on the optimised three-level variable power loading scheme, the fastest ever real-time end-to-end transmission of 6Gb/s 16-QAM-encoded OOFDM signals is achieved experimentally over a 300m OM1 MMF IMDD system involving a DML. Figure 7 shows the corresponding total channel BER performance for both the 300m MMF system and the optical back-to-back configuration.
It is shown in Fig. 7 that, for the case of 300m MMF transmission (optical back-to-back), a minimum BER of 3.4x10−4 (3.3x10−4) is obtainable at a received optical power of −7.7dBm (−7.2dBm). At a BER of 1.0×10−3 a power penalty of ~0.5dB is observed, mainly resulting from the differential mode delay (DMD) effect  and the modal noise effect . In comparison with the performance of real-time 3Gb/s 16-QAM-encoded OOFDM signals over 500m MMFs [11,12], here, the minimum received optical power required for achieving a BER of 1.0×10−3 is increased by 5.8dB, and the power penalty is decreased by 1.5dB. The increase in received optical power is because the 6Gb/s OOFDM signals have twice the spectral bandwidths, which are more severely impacted by the system frequency response roll-off effect, whilst the reduced power penalty arises from the decrease in the DMD effect due to the shorter transmission distance .
The corresponding received constellations measured before conducting channel equalization at a BER of 1.0×10−3 for the 1st, 8th and 15th subcarriers are shown in Fig. 8 and Fig. 9 for the optical back-to-back and 300m MMF cases, respectively. In Fig. 8, the first subcarrier constellations are the worst, this originates mainly from subcarrier beating-induced signal spectral distortions in the vicinity of the optical carrier upon direct detection in the receiver .
It is also observed in Fig. 7 that error floors exist for both considered cases. This is mainly due to the existence of spurious constellation points, which are circled in red in Fig. 6. Based on the measured constellations of the subcarriers shown in Fig. 6, a BER of <3.0x10−5 is calculated if the red-circled spurious points are removed. These spurious points may arise due to timing irregularities in the ADC interface, as a BER of zero is obtainable in the digital back-to-back configuration, and very similar minimum BERs are observed in the analogue back-to-back configuration compared to the optical back-to-back case. Experimental investigations are currently underway to eliminate these spurious constellation points.
Based on a recently proposed pilot subcarrier-assisted channel estimation technique and a simple three-level variable power loading scheme, the fastest ever 6Gb/s real-time FPGA-based OOFDM transceivers have been experimentally demonstrated, for the first time, which have crucial functionalities of on-line performance monitoring and live optimization of key parameters including signal clipping, subcarrier power and DML operating conditions. The developed transceivers use commercially available components with FPGAs for real-time DSP and 4GS/s, 8bit DACs and ADCs. It has been shown that variable power loading is an effective means for compensating for the rapid system frequency response roll-off effect. Real-time end-to-end transmission of a 6Gb/s 16-QAM-encoded OOFDM signal over a 300m OM1 MMF with a power penalty of 0.5dB and a spectral efficiency of 3 bit/s/Hz has been successfully achieved in a DML-based IMDD system.
This work was partly supported by the European Community's Seventh Framework Programme (FP7/2007-2013) within the project ICT ALPHA under grant agreement n° 212 352, in part by the U.K. Engineering and Physics Sciences Research Council under Grant EP/D036976, and in part by The Royal Society Brian Mercer Feasibility Award. The work of X.Q. Jin was also supported by the School of Electronic Engineering and the Bangor University.
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