We present the design and numerical simulation results for a silicon waveguide modulator based on carrier depletion in a linear array of periodically interleaved PN junctions that are oriented perpendicular to the light propagation direction. In this geometry the overlap of the optical waveguide mode with the depletion region is much larger than in designs using a single PN junction aligned parallel to the waveguide propagation direction. Simulations predict that an optimized modulator will have a high modulation efficiency of 0.56 V·cm for a 3V bias, with a 3 dB frequency bandwidth of over 40 GHz. This device has a length of 1.86 mm with a maximum intrinsic loss of 4.3 dB at 0V bias, due to free carrier absorption.
©2009 Optical Society of America
Optical modulation is an essential function in optical interconnects and telecommunications systems. There has been a recent surge of interest in silicon waveguide modulators, due to their compatibility with mature CMOS electronics fabrication technology [1–4]. For most of the work reported so far on silicon modulators, high speed optical modulation is achieved by varying the carrier density to change the local index of refraction [1–4]. Three device configurations have been studied: carrier injection in forward-biased PN diodes [5–7], carrier accumulation in metal-oxide-semiconductor (MOS) capacitors , and carrier depletion in reverse-biased PN junctions [9–15].
Forward biased PIN diodes are widely used to obtain refractive index change by carrier injection into the lightly-doped i-region of the diode. The overlap between the i-region and the waveguide optical mode is large, giving rise to a high modulation efficiency at low voltages of ~1.5V. On the other hand, minority carrier injection into a forward biased diode is slow, and the intrinsic frequency bandwidth of a normal diode is less than 1 GHz. One practical solution is to incorporate a high-pass filter into the electronic drive circuit. So far, the response speed of the modulator has been extended to a cut-off frequency of 5 GHz .
The MOS capacitor based modulator reported in 2004  was a break-through in the intrinsic response speed. By employing carrier accumulation near the dielectric layer of a capacitor, modulation at 10 Gbps was achieved for the first time in a silicon electro-optic device. Since free carriers are accumulated within a very thin layer near the dielectric film, the refractive index variation overlap with the optical mode is very small, yielding low modulation efficiency of Vπ·Lπ ~3.3 V·cm. Here the modulation efficiency Vπ·Lπ is the product of the modulation arm length Lπ and the corresponding reverse bias Vπ necessary to produce a π phase shift. The smaller this product, the more efficient the modulator is. Therefore, MOS modulators require a large footprint (3.5 ~15 mm long) and a high driving voltage (4 ~10 V), which is a roadblock to integration of large number of modulators using CMOS driving circuits.
Recent work has focused on free carrier depletion in reverse biased PN junctions, where the response time can be less than 10 ps  in theory. Operation at over 30 GHz without using a pre-emphasized drive signal has been demonstrated experimentally in devices based on four terminal p+pnn+ diodes [10,12–15], with response times as short as ~25 ps at a reverse bias of 4 V . In all of these designs, the PN junction is parallel to the light propagation direction, either along the horizontal wafer plane (referred to as Parallel-H), or vertical to it (Parallel-V), as described in Table 1 . The poor optical field overlap with the carrier modulation region causes the efficiency of the depletion and accumulation based devices to be far inferior to what can be achieved in PIN carrier injection modulators (~0.04 V⋅cm ), and the voltage of 4 - 10 V required for achieving π phase shift are higher than what is available from conventional CMOS circuits. Table 2 shows the figures of merit of several recently reported PN junction based modulators. As a result special high voltage driver circuits are required, a similar limitation as the commercial LiNbO3 modulators.
For modulators with junctions aligned along the waveguide propagation direction (Parallel-V or Parallel-H), the position of the depletion or accumulation layer can be chosen to coincide with the maximum intensity of the waveguide mode profile. To optimize the overlap of the depletion layer and optical mode, depletion modulators have used relatively low doping (~1 × 1017 cm−3) [9–13]. While higher doping concentration increases the local index change in the depletion layer [14,15], the total depletion thickness at a given voltage is reduced. Thus the mode-depletion layer overlap decreases, limiting the achievable electro-optic modulation efficiency.
The key to high efficiency is to increase the optical mode and depletion layer overlap, for PN junctions with moderate doping levels (~1 × 1018 cm−3). To accomplish this, we have proposed the modulator structure shown in Fig. 1 , where interleaved PN junctions are periodically distributed along the waveguide and oriented perpendicular to the light propagation direction (Ortho-V in Table 1). Since each PN-junction extends across the entire waveguide cross-section, the total overlap between the depletion regions and the optical mode is determined by the ratio of the depletion width to the PN junction array period. The resulting high modulation efficiency allows the modulators to operate at low driving voltages of 1 - 3 V, with minimal dopant induced absorption loss and modulation lengths less than Lπ = 0.2 cm. This opens the possibility of using modulator driving circuits compatible with CMOS/Bi-CMOS devices.
The remainder of this paper is organized as follows. In Section 2 the novel design (Ortho-V) of periodically interleaved PN junction based silicon optical modulator is introduced. In Section 3 simulation method is described, and the calculated effects of doping level, segment length and segment width on modulator performance are presented. The design parameters and the figures of merit for several representative designs are summarized. The driving conditions are discussed in section 4 and the optical return loss is discussed in section 5. The paper ends with conclusions in section 6.
2. Modulator design
The basic optical structure is a rib SOI waveguide of width W0, with a rib height H and an etched slab height h, as shown in Fig. 1(a). Interleaved doping regions are formed with a segment length L and a segment width W1, as shown in Fig. 1(b), with the same concentration N1 for N- and P- type doping. Highly doped N+ and P+ contact regions (N+ = P+ = 1 × 1019 cm−3) are separated from the rib by a buffer region of width W2 and a doping concentration N2 for both the P and N dopants. The metal electrodes are assumed to overlap the N+ and P+ contact regions. The electrical simulations performed are in two dimensions (x-z plane), and the range of waveguide dimensions analyzed encompasses the dimensions of recently reported parallel PN junction modulators [10,15], with the rib waveguide height of H ~500 nm. For comparison with previously published results, we start with a baseline design (Design A) using W0 = W1 = 600 nm and doping concentrations N1 = N2 = 2 × 1017 cm−3. From analytical calculations for a planar PN junction under a 3 V reversed bias, the depletion layer thicknesses with the P-type and N-type doping levels of 2 × 1017 cm−3 , 1 × 1018 cm−3 and 4 × 1018 cm−3 are approximately 230 nm, 100 nm and 50 nm, respectively. For maximum modulation efficiency at the applied bias, these widths should ideally be comparable to the doping segment length L. In Design A, we chose L = 300 nm. In section 3, the dependence of modulator performance on the interleaved segment length L, segment width W1, and doping concentrations N1 and N2 will be analyzed.
As discussed earlier, the key to high efficiency is to increase the optical mode and depletion layer overlap for PN junctions with moderate doping levels (~1 × 1018 cm−3). Ortho-V type (Fig. 1) is a good candidate. The light signal passes through the depletion regions in succession, so the total overlap between the depletion regions and the optical mode is multiplied by the number of the PN junctions. The electro-optic modulation efficiency increases due to the large total overlap. This permits the low voltage operation of PN junction based modulators, without excessive phase shifter length and only moderate penalty in absorption loss.
3. Modulator performance simulations
For modulator operation, there are four key performance parameters: modulation efficiency, insertion loss, response speed and return loss. Our investigation focuses on the effects of doping concentration N1, interleaved doping segment length L and segment width W1 on these key parameters.
3.1 Simulation method
In the following we describe the parameters used in the modulator performance analysis. A free-space wavelength of λ = 1550 nm is used in all the following simulations. The changes of the refractive index and the absorption coefficients in silicon and due to the free electron and hole concentrations and can be expressed as :Fig. 1), z is propagation direction and is the optical intensity profile of the waveguide mode. The mode profiles depends on the Si thickness H, ridge width W0, and ridge etch depth H - h. However, since the electrical simulations available are carried out in a two dimensional slab model, it is not possible to calculate an exact overlap integral of the waveguide mode and a three dimensional carrier distribution. Therefore, a simple top-hat function having the waveguide width W0 is used to represent the optical field profile in this work, as shown in Fig. 1(c). While the results obtained using this approximation will underestimate the modulation efficiency and overestimate the response speed at a given bias voltage, we expect the differences will be of the order of 10% or less when compared with the results of a rigorous calculation. This conclusion is supported by the relatively slow variation of the calculated modulation efficiency and speed on the modulator segment width found in section 3.4. Using the and functions calculated using Eq. (2), the phase shift per unit length Δφ (π/mm) and the free carrier absorption loss Δα (dB/mm) can be obtained by integrating over one period (with length 2L) of the interleaved PN junction structures.17]. In order to simplify the calculation, the electrical simulations are performed for a planar structure in 2-dimensions, in the x-z plane shown in Fig. 1 (b). Thus for the electrical simulations it is assumed that in the y-axis direction H = h = H0 = 1 µm (the default value in the 2-D simulation package used). For the simplest model and symmetric mesh grids, a slice consisting of one interleaved period is chosen for the computing window, as shown in Fig. 1 (b), with both P-type and N-type doping regions having the same areas. The grid points of horizontal (x) and vertical (z) mesh nodes are 90 and 100, respectively. The intrinsic carrier concentration of silicon is chosen to be 1 × 1010 cm−3 at a temperature of T = 300 K. The lifetimes of free carriers are 700 ns and 300 ns for electrons and holes, respectively
The transient response of the modulator is simulated by applying a square wave voltage pulse with an amplitude of 1 - 3 V, a 0 to100 percent ramp time of 1 ps and a duration of 1 ns, unless specified otherwise. The rise and fall times are defined as the time for ∆φ to change from 10% to 90% or 90% to 10% of its maximum amplitude, respectively. The 3 dB bandwidth is defined as BW3dB = 0.35 / tMAX , where tMAX is the longer of the fall time and the rise time.
3.2 Dependence on the doping level N1 of interleaved segments
Table 3 gives a summary of our several representative designs discussed in the text. They have different geometries and doping levels for a high modulation efficiency with a balanced frequency bandwidth.
We begin the analysis with the baseline structure (Design A) described in section 2. The doping concentrations N1 = N2 = 2 × 1017 cm−3 are similar to previously reported designs [9,10], and W0 = W1 = 600 nm. The segment length of L = 300 nm was chosen for a modulator designed for 3 V operation. This length is slightly larger than the depletion layer thickness (~230 nm) of a planar PN junction of the same dopings. Figure 2 (a, b) shows the free carrier distributions of the periodically interleaved segments for Design A without and with a reverse bias of 3V. The dotted lines show the interfaces between p-doped and n-doped regions. It is observed that the depletion layer thickness is not uniform due to the geometry, and there is a fraction of undepleted area which is also a function of the segment width W1.
The dependence of the phase shift Δφ, loss Δα, and bandwidth BW3dB with doping concentration is shown in Fig. 3 , for several operating voltages. For Design A operating at a 3 V bias, the modulation efficiency is Vπ·Lπ = 1.62 V·cm, and the length of the modulation arm to achieve a π phase shift is Lπ = 5.4 mm. This value is lower than the value of 2.5 V·cm reported in  for a parallel PN junction modulator with similar doping concentrations. The maximum calculated absorption loss is α π = 2.09 dB at zero bias. When the device is biased at reverse 3 V, the loss is reduced to a small value of α π = 0.79 dB. With a voltage ramp time of 1 ps, the phase response rise and fall times are approximately 6.9 ps and 10 ps respectively, corresponding to a frequency bandwidth of BW3dB = 35 GHz.
The phase shift Δφ is approximately proportional to the driving voltage in the range from 1 V to 3 V for Design A, since the interleaved segment is not fully depleted even at 3 V. Increasing the dopant concentration increases the phase shift for a given drive voltage, as shown in Fig. 3 (a). However, the absorption loss also increases substantially (Fig. 3(b)) with increasing doping concentration in both the biased and unbiased states. When N1 and N2 for both P-type and N-type rise to 1 × 1018 cm−3 (Design B), the loss increases to α π = 6.8 dB at a bias of 0 V and α π = 5.1 dB at a reverse bias of 3 V, for a modulator of length Lπ = 2.64 mm. For a much higher concentration of 4 × 1018 cm−3 for both types of dopings, the bandwidth increases to ~60 GHz but the loss also increases to α π = 16.8 dB without bias (Lπ = 1.47 mm). Such absorption losses are prohibitively large for a π phase shifter.
Interestingly, the bandwidth increases from 35 GHz to 54 GHz when the doping N1 and N2 increases from the baseline values of 1 × 1017 cm−3 in Design A to 1 × 1018 cm−3 in Design B. This is mainly related to the reduced resistance of interleaved segments, although the capacitance is larger than that of the baseline design. The higher admittance permits more free carriers to be extracted from and returned to the interleaved segments through the un-depleted segment, as shown in Fig. 2 (b). Moreover, a higher doping level enhances recombination processes such as Auger recombination to produce a shorter carrier lifetime, which is helpful for the faster response of a PN junction modulator.
3.3 Segment length optimization
Here we discuss how to improve the performance of Design B, by adjusting the segment length L appropriately. In this section N1 = N2 = 1 × 1018 cm−3. Figure 4 (a) shows the phase shift Δφ as a function of segment length L for different reverse biases. For L << 100 nm, the phase shift per unit length Δφ is very small (< 0.1 π/mm), since the structure is already almost fully depleted at zero bias. When L is large, e.g. in Design B with L = 300 nm, only a fraction of each doping segment is depleted and contributes to the phase shift, and so Δφ decreases. For other operating voltages, the trends are similar. The maximum Δφ is obtained when L is close to the depletion thickness for a given dopant concentration and bias voltage. Design C is taken to have the same parameters as Design B (a 1 × 1018 cm−3 doping at 3 V reverse bias), except that L is taken to be 100 nm, near the optimal response at L = 110 nm.
Figure 4(b) shows that the absorption loss per unit length Δα improves with decreasing L, due to similar reasons described above, i.e. with L decreasing, a larger fraction of the waveguide is depleted at a given bias, so loss is reduced. At the same time, Δφ is increased by choosing a smaller L, yielding a smaller Lπ. The total loss in a π phase shifter α π = Lπ ⋅Δα decreases at a greater rate with decreasing L, as described above.
For an operation at a reverse bias of 1 V, the case of a short L = 100 nm is calculated. Here Lπ = 2.38 mm (Design D) with Vπ·Lπ = 0.238 V·cm and α π varies from 3.8 dB (0 V) to 2.2 dB (3 V). This is the most efficient case for the reverse PN junction based modulators. This simulation indicates that it is possible to drive a PN junction based modulator at a bias as low as 1 V with high modulation efficiency.
On the other hand, the BW3dB decreases with decreasing L, as shown in Fig. 4(c). This can be explained by the narrower undepleted regions. Since carrier transport can only occur through the undepleted regions, it takes more time for the free carriers to be re-injected back into the interleaved PN junctions after the bias voltage falling edge. The speed for Design D is not very fast due to near full depletion, giving a bandwidth of 16 GHz. For a more balanced performance in both speed and efficiency, the optimal value of L for this doping level is L = 150 nm (Design E). By doing so, the bandwidth improves to 27 GHz while the modulator efficiency is Vπ·Lπ = 0.44 V·cm, and the loss α π varies from 3.1 dB (0 V) to 1.45 dB (3 V). At a lower operating voltage of 1 V, the bandwidth shows little change (Fig. 4(c)), but the modulator efficiency is lower and the loss higher. These results suggest that the optimal segment length L is larger than the thickness of a fully-depleted layer at that operating bias.
3.4 Segment width optimization
As shown in Fig. 2, the depletion layer thickness is non-uniform in the interleaved sections, and its exact shape is dependent on the segment width W1. Figure 5(a) shows the phase shift Δφ as a function of W1, for a constant waveguide width of W0 = 600 nm (See Fig. 1). When W1 decreases from 700 nm to 150 nm, Δφ decreases rapidly. As the segment width W1 becomes much narrower than the waveguide mode width W0, the total depleted region occupies only a small fraction of the waveguide mode cross-sectional area, and the modulation efficiency is reduced. The maximum phase shift is obtained when W1 ≈W0. On the other hand, as W1 decreases relative to W0, the absorption loss Δα increases, as shown in Fig. 5(b), since the un-depleted region occupies a larger fraction of the waveguide. Note that the case of W1 = 0 approximately corresponds to the “Parallel-V” structure. This graph shows how the interleaved structure increases the response compared to the Parallel-V structure. For low biases, where the width Wd of the depletion region is small, the volume of the depletion region is approximately (L + W1)WdH. For Parallel-V, the volume of the depletion region is LWdH. Thus the improvement of the interleaved structure compared to the Parallel-V structure is approximately 1 + W1/L, which fits the slope of the curve in Fig. 5 (a) in the range of 150 - 600 nm.
As the segment width is made smaller, the response speed increase, as shown in Fig. 5 (c), due to the shorter distance for carrier transport. When W1 changes from 600 nm to 450 nm, the response speed improves from 27 GHz to 41 GHz. Hence in Design F we chose the value W1 = 450 nm as a good balance between efficiency and speed.
The choice of buffer width W2 and its doping N2 also affect the modulator performance (see Fig. 1). So far we have assumed the same doping for the interleaved PN junction region and the buffer region, i.e. N1 = N2. If the buffer is lightly doped, e.g. 2 × 1017 cm−3, the resistance of the whole PN modulator increases. Using a larger buffer width W2 has the same effect. The transient process at the voltage falling edge is delayed due to the lower speed of free carrier injection. For an interleaved segment doping of N1 = 1 × 1018 cm−3, and an increased buffer doping of N2 = 3 × 1018 cm−3, we obtain a large bandwidth of 49 GHz (3 V operation). This however comes with the penalty of a higher loss and lower efficiency. We obtained optimized modulator structure, Design F, by balancing several conflicting performance criteria. This design has high modulation efficiency (~0.6 V·cm), low driving voltage (3 V), low absorption loss (< 5 dB), and fast response speed (~40 GHz), with a moderate doping of N1 = N2 = 1 × 1018 cm−3. At a lower driving voltage of 1 V, Design F maintains a similar bandwidth, at the expense of reduced efficiency and increased loss.
4. Driving condition
Figure 6 (a) and (b) show the driving signal, the junction current density (A/mm) and the phase shift (π/mm) as a function of time at two driving signal ramp rates, for the modulator Design F. The peak current density per unit length along the waveguide at the leading and trailing edges of the driving pulse are Jp = 1.24 A/mm for a ramp rate of 1 ps, as shown in Fig. 6 (a). For a simplified case, we choose H = h = 300 nm, the peak driving current for Design F with Lπ = 1.86 mm is Ip = JpLπH/H0 = 692 mA for a bandwidth of 41 GHz with 3 V driving voltage, corresponding to a peak power of ~2.1 W. This power level is smaller than the reported experimental results of ~3 W RF power dissipation [8,10], which is readily available from driving circuits. In an actual modulator structure, we would need to use a slab height h < H. The intrinsic bandwidth of the modulator is approximately limited by the RC time constant for a simple analysis. Since the resistance of the device is proportional to the height of slab waveguide h, the device with a low h (h < H) would have a lower bandwidth. Therefore, in order to maintain the same bandwidth as the device assuming h = H, the buffer region should have an increased doping level.
For Design F, using a longer voltage ramp time of 20 ps, the device time response follows the driving signal, exhibiting a 3 dB bandwidth of ~25 GHz. The transient peak current density reduces to approximately 0.25 A/mm, as shown in Fig. 6 (b). The peak driving current becomes Ip ~140 mA for H = h = 300 nm.
5. Modulator return loss
The interleaved PN junction modulator consists of P-type and N-type segments of equal length, and each segment is partially depleted at the given reverse bias. Due to the periodicity in the resulting refractive index modulation along the waveguide, a return loss arising from Bragg reflection may be expected from such structures. This mechanism has even been proposed as the basis for highly compact modulators that use the resonant back-reflection . The following analysis shows, however, that the reflection in our structures is negligible.
When the period length of an optical grating is equal to half of its operation wavelength, the grating has a resonance in reflection. The effective index of the propagating mode in the rib waveguide (dimensions as H = 500 nm, h = 300 nm and W0 = 600 nm) is ~3.17 (quasi-TE mode), and the optical grating period should be approximately 246 nm. In the previously discussed designs with the segment lengths of 100 nm, 150 nm or 300 nm, the Bragg reflection condition is not satisfied. We have calculated the back-reflection using the transmission matrix method (TMM), including the effect of free carrier absorption loss in doped silicon. The TMM calculations indicate that the grating effect of interleaved segments with periodic doping is weak for most cases with different geometries and doping levels. Only when the period of the interleaved region is near the Bragg condition (2L = 246 nm) back-reflection can be observed under bias. The high absorption loss in the undepleted regions is the main reason for the weak grating effect, even when the optical thickness of the segments matches the Bragg condition.
For Designs A – F summarized in Table 3, the maximum back-reflection with respect to the bias voltage is less than 10−4, corresponding to a return loss of less than −40 dB.
We have described a novel design for a silicon optical modulator with fast response, high efficiency and low operating voltage. The modulator is comprised of periodically interleaved PN junctions, which are oriented perpendicular to the light propagation direction and operate under reverse bias. Unlike previously reported modulators with a single PN junction oriented parallel to the waveguide light propagation direction, we employ a periodically doped structure where the light travels through a large number of PN junctions in succession, increasing the interaction between the optical mode and the depletion regions.
The modulator performance is governed by the doping level in the modulator, and the geometrical parameters including the interleaved segment length and width. Simulations indicate that a higher doping level in the PN junction increases the modulation efficiency as well as the bandwidth, but with the penalty of a higher absorption loss. The segment length L can be reduced for structures with higher doping to decrease the absorption from the un-depleted regions. The reduction of L, however, also restricts the current transport, leading to a reduced bandwidth. The segment width W1 affects the overlap with the optical mode, as well as the depletion thickness distribution and carrier transport distance.
A number of designs are examined using a moderate doping of 1 × 1018 cm−3 in PN junctions. For modulator Design D in Table 3, an operating bias of 1 V can still provide a bandwidth of 16 GHz and a modulation efficiency of Vπ⋅Lπ ~0.24 V⋅cm, which is one order of magnitude lower than previously reported values. The free carrier absorption loss is 3.8 dB when unbiased, and ~2 dB under 1 V bias.
For an optimized design with a segment length L = 150 nm and a segment width W1 = 450 nm (Design F), the bandwidth is improved to BW3dB > 40 GHz. The modulation efficiency is Vπ⋅Lπ ~0.56 V·cm for 3 V operation, and Vπ⋅Lπ ~0.62 V⋅cm for 1 V operation. The maximum return loss is less than −40 dB in these designs.
This modulator configuration is therefore promising for monolithic integration of silicon optical chips for high performance applications including optical coding and switching, using readily available CMOS modulator driving circuits.
This work is a part of a collaboration between Institute for Microstructural Sciences (IMS), National Research Council (NRC) Canada, and Institute of Semiconductors (IS), Chinese Academy of Sciences (CAS). It was supported in part by the National 973 Program of the Ministry of Science and Technology of China (Grant No. 2006CB302803), and the National Science Foundation of China (Grant No. 60537010 and 60877036).
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