A novel optical time-to-live (TTL) method based on the use of logic XOR gates is proposed. All-optical decrementing of a packet’s TTL field is demonstrated employing a cascade of two SOA-based Mach-Zehnder interferometers. The principle of operation is validated by means of simulations, showing a good extinction ratio (higher than 10 dB) at the output of the 1-bit subtractor.
© 2008 Optical Society of America
The tremendous growth in the telecommunication services demand over the last years is pushing the bandwidth of optical networks to manage this traffic increase. Nowadays, wavelength division multiplexing (WDM) is a convenient and low cost way to increase the capacity of optical links by multiplexing many channels at different wavelengths within the same fiber. However, the rather coarse granularity of WDM is a handicap for the future dynamically reconfigurable optical transport networks which offer different types of services.
In this dynamic scenario, optical packet switching (OPS) arises as a flexible technique to provide the bandwidth efficiency and granularity required in this kind of networks.
The main advantages of optical networks are high capacity and transmission rates. However, when a cable breaks a lot of gigabits of data are lost. Therefore network reliability is a vital issue and optical performance monitoring (OPM) has attracted great interest during the last years mainly due to the progress in optical networking techniques [1–2]. To assess the health of optical signals, several parameters are usually monitored at the physical layer: optical power or channel wavelength, optical signal-to-noise ratio (OSNR), chromatic dispersion, Q-factor, Bit Error Rate (BER), PMD and time jitter. But these parameters require a direct measurement over the optical signal and most of them are not valid for optical packets. On the other hand, the processing of optical packet labels allows new optical signal processing technologies to be implemented to facilitate high-performance packet routing and networking, such as optical time-to-live (TTL). Routing loop is a serious problem in packet-switched networks, which can cause severe overload and congestion in the network. TTL is one way to loop mitigation where each hop will reduce the value of the TTL field and will discard the packet when the packet’s TTL value reaches zero. Indeed this method can also be effective as an OPM technique. Every time a packet goes through one hop in the network its quality is reduced. So the maximum degradation that a packet can support matches a maximum number of router hops (TTL value). Recent works have demonstrated optical TTL using ultra- short pulse bursts and nonlinear effects [3–4], but these methods are complex and difficult. Another TTL method is based on OSNR  which requires electronic label processing. However, all-optical techniques are desirable in high-speed OPS because they provide low latency and can process the optical packets on-the-fly.
In this paper, a novel TTL method based on the use of optical logic XOR gates is proposed. All-optical decrementing of a packet’s TTL field is demonstrated employing a cascade of two SOA-based Mach-Zehnder interferometers (SOA-MZIs). The principle of operation is validated by means of simulations, showing a good extinction ratio (higher than 10 dB) at the output of the 1-bit subtractor. The maximum number of subtraction operations is limited by the ASE noise levels.
2. Principle of operation
2.1. 1-bit binary subtraction
Decrementing a TTL field by “1” requires the implementation of a binary subtraction algorithm. Considering any arbitrary starting binary word this results in the least-significant-bit (LSB) being inverted (1 minus 1 is 0, while 0 minus 1 results in 1). If the LSB is a “1” bit, the subtraction is complete, as no borrowing is necessary. However, if the LSB is a “0” bit, the next higher column must be reduced by “1” as a result of the borrowing process. This process continues with additional borrowing until a “1” bit is encountered. After inverting the “1” bit, the subtraction is completed. Next the 1-bit subtraction process is shown with two examples:
i) 1 0 0 1 0 0 - 1=1 0 0 0 1 1
ii) 1 0 0 0 1 1 - 1=1 0 0 0 1 0
As it can be seen, this results in a set of bits being replaced by their conjugates (beginning with the LSB up-to-and-including the first “1” bit).
2.2. Architecture of the 1-bit binary subtractor
As commented before, previous approaches to implement an all-optical binary subtractor are complex. In our case, we propose a method based on optical logic XOR gates implemented in SOA-MZI devices. The architecture of the 1-bit binary subtractor is shown in Fig. 1(a). It is mainly based on two SOA-MZI devices configured as a Boolean logic XOR gate . Both SOA-MZIs are normally off (i.e. π phase difference between the arms), so the control pulses only appear at the output if both data inputs are different. The proper interconnection between the two XOR gates leads to the desired subtraction operation explained above.
The power of the incoming TTL word is split: one fraction enters the first XOR gate (XOR1) through port #1 after a 1-bit time delay, whereas the other enters the second one (XOR2) through port #1. The logic XOR1 gate has a feedback loop which redirects its output pulses as a control signal for the successive incoming bits . These control pulses act as enabling signal for the XOR gate. The feedback loop consists of an optical amplifier, an optional band-pass filter and a delay element for time synchronization between pulses. The optical filter, centred at the control signal wavelength, reduces the propagation of ASE noise through the feedback loop. Moreover, the optical amplifier adjusts the power level of the output pulses so that a feedback loop gain close to the unity is achieved. To avoid lasing at the operating wavelength, a phase shifter may be used. For high-speed operation, a photonic-integrated feedback loop is required . The maximum overall loop delay allowed by the gate is given by 1/R, where R is the bit rate (100 ps @ 10 Gb/s, or 25ps @ 40 Gb/s).
As a result of the interconnection set-up of Fig. 1(a), optical pulses are obtained at the output port #2 of XOR1 as long as the two data bits (input ports #1 and #3) are different and the control signal (port #4) is at high level. If there is a bit comparison between two data bits which are the same, then no output pulse is obtained at port #2 and the gate is disabled, as the control signal will be at low level from now on. The output from XOR1 is then used as one of the two data inputs to XOR2. In this case, the control signal is a pulse train. At the output of XOR2, a 1-bit decremented TTL field is obtained. Finally, the signal is amplified and filtered again, as well as power equalized using a saturable absorber. An example of operation of the 1-bit subtractor is schematically depicted in Fig. 1(b), whereas its Boolean logic principle of operation is explained in Fig. 2. The gate requires control pulses to do the XOR operation. Otherwise it is disabled and no output is obtained. So the control input is also used to disable the gate when required (after the first “1” bit in the TTL input). The initial pulse is needed to enable the XOR gate initially and must be synchronized with the TTL signal. Synchronization issues can be addressed in a similar way to that shown in .
3. Results and discussion
The proposed TTL decrementing technique was tested by means of simulations using the Virtual Photonics Inc. software. These simulations aimed to demonstrate the subtraction operation employing practical devices. The input TTL signal at 1558 nm was generated by externally modulating at 10 Gb/s an RZ Gaussian pulse source (FWHM=5 ps). The initial pulse (one pulse at the beginning of each subtraction operation) and control pulse train were characterized with the same parameters. The data and control peak powers were adjusted at 3 mW at the SOA-MZI inputs. Moreover, the SOAs (600-µm length) were biased at 250 mA.
The simulation results are shown in Fig. 3. The incoming TTL field (1101000) is depicted in Fig. 3(a), whereas the output of the subtractor (1100111) is depicted in Fig. 3(b). The LSB enters first in time into the subtractor. As it can be seen, the architecture works properly (a set of bits being replaced by their conjugates, beginning with the LSB up-to-and-including the first “1” bit: 1101000 - 1=1100111). In order to equalize the power levels of the output signal, a saturable absorber was used in the results of Fig. 3(c). The performance of the technique was assessed by means of the extinction ratio, obtaining values higher than 10 dB. Although RZ signals were used, the proposed system also works for a NRZ TTL input provided that RZ control pulses are injected into the XOR gates.
After that, in order to validate the cascading functionality, the output of a first subtractor was used as the input of a second one and so on up to four iterations. Figure 4 shows the obtained results. As it can be seen, the TTL field is decremented by 1 bit each time from an initial value of 100 in Fig. 4(a) to a final zero value in Fig. 4(e). The TTL decremented field emerged with a time delay of 29 ps in our simulations. This delay does not depend on the number of bits, but on the XOR gate processing time. Basically, the TTL processing time slightly increases the latency of the optical node. As the TTL field is used to estimate the possible signal quality degradation (OPM technique) in terms of router hops, when this field reaches zero a control signal could be generated so that the router drops the packet. To this end an optical flip-flop circuit may be used .
Finally, in order to test the performance of the proposed technique, the Q-factor was measured at the output of the subtractor for several recursive operations. The simulation results are depicted in Fig. 5, showing that the approach may be limited for a high number of operations. Obviously, the maximum number of subtractions (TTL field initial value) depends on specific parameters of the SOA-MZI devices and the ASE noise generated. These results are provided as a proof of concept and should be assessed during the experimental phase. To this end, a photonic-integrated feedback loop is required in the first XOR gate . Short loops have long been a major deterrent for feedback based optical logic. To obtain a 100-ps round-trip time in the feedback loop (10 Gb/s operation), small radius waveguide bends are needed which can be achieved employing high-index silica waveguides (~1-mm radius) or other fabrication technologies such as a deep/shallow double etching process (~100-µm radius) . For 40 Gb/s operation and beyond, the use of new promising technologies such as two-dimensional photonic crystal (2D-PC) slabs for manufacturing ultra-small PICs are a suitable choice to implement the proposed architecture solving the speed constraint of the feedback loop.
We have shown by means of simulations that SOA-MZI devices acting as logic XOR gates can be used as the main functional blocks to implement an all-optical TTL subtractor. The simulation results show a proper operation with good performance (extinction ratios higher than 10 dB). Therefore, the optical TTL decrementing method proposed here is a valuable technique for optical performance monitoring in packet-switched networks. The maximum TTL field value (number of node hops), however, is limited by the ASE noise introduced by the SOA-MZIs after each operation.
This work was supported in part by the Spanish Government (Ministerio de Educacion y Ciencia) under project TEC2005-04554. The work of R. Vilar is also supported by the Spanish Government through an FPU grant.
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