A forward-biased p-i-n diode integrated with a ridge waveguide forms a basic Si attenuator building block. Disruptive power improvement was achieved through a recessed contact configuration by limiting the amount of Si volume for carrier recombination. A device model was established by using realistic surface recombination velocities instead of effective carrier lifetime concept to understand the device physics of the afore-mentioned Si attenuator.
©2008 Optical Society of America
A silicon-on-insulator (SOI) single or multi-moded ridge waveguide integrated with a lateral or vertical p-i-n diode forms a basic Si-photonic building block. This device operates as either an optical amplitude and phase modulator, a phase shifter, or an electronically-controlled attenuator. The key feature of this solid-state device is its MHz bandwidth and submicrosecond response time. Following Soref’s equation , the amount of phase shift or amplitude change (in decibel scale) is almost a linear function of the carrier concentration within the optical waveguide. An efficient Si attenuator therefore establishes a carrier concentration in the waveguide with a minimum amount of applied electrical power.
This paper describes a recessed contact design that improves the power efficiency of the Si attenuator . The tradeoff between the power efficiency and the device speed is also investigated. In order to elaborate why the proposed device structure is more favorable than many alternative configurations, a series of numerical experiments were conducted to simulate the device steady-state and transient behavior, and the numerical models were validated against experimental data to justify its soundness.
The waveguide size selected in this study was 4x4 µm2, larger than the micron  or submicron [4–6] waveguide devices investigated by many other groups. The 4 µm, technology is manufactured by Kotura, Inc. and is installed in many field applications . It has a low coupling loss to a single-mode fiber through a 3-dimensional mode transformer technology, which expands the 4x4 µm2 mode on wafer to 12x12 µm2. Per side coupling loss is less than 0.4 dB for both polarizations across the C-band. The designed waveguide is usually polarization independent.
2. Numerical model
A schematic diagram of the Si attenuator cross-section is displayed as Fig. 1. The Si attenuator to be investigated has a waveguide height of 4 µm. A buried oxide (BOX) thickness of 400nm is used for vertical confinement. Without losing generality, we assume a 40% etch-down to form a ridge waveguide of 4 µm width. Energy contour of the TE fundamental mode is presented in Fig. 2, TM mode is similar but slightly less power spreading in the slab. Ion implantation forms p- and n-junctions of 0.5 µm in depth adjacent to the waveguide, since it is not practical/economical to make heavy doping deeper than 0.5 µm. The doping levels are 6x1019 cm-3 for the P side and 4x1019 cm-3 on the N side. As long as the doping level is high enough for ohmic contact, variation of doping level has little effect on the attenuator performance. The background doping is 1015 cm-3, p-type, which has no practical effect on the light traveling through an attenuator length of 1 cm. The structure forms a lateral p-i-n diode, which, in forward bias, injects electrons and holes into the waveguide.
used Silvaco (Silvaco Data Systems, Santa Clara, CA)  as the modeling tool in this work, but the discussion shall generally apply to other simulation softwares. Physical mechanisms included in the model were Concentration dependent Shockley-Read-Hall (CONSRH) recombination model, Auger recombination, Klaassen’s Unified Low Field Mobility Model (KLA), bandgap narrowing (BGN), and Fermi-dirac statistics. Shockley-Read-Hall (SRH) recombination carrier lifetimes were assumed to be: τ n0=100 µs, τ p0=100 µs for electrons and holes, respectively. This is a conservative estimation, real device numbers are usually even longer than this. As for the waveguide dimension of interest, surface recombination and/or transit time dominates over intrinsic SRH , so this number is not critical, and underestimation is more harmful than overestimation.
Most silicon-on-insulator (SOI) wafers used in the industry are made from either the SIMOX or the Smart-Cut process. The SOI thickness is typically only 100-200 nm. Epitaxial Si is grown on top to make a waveguide 4-µm thick. Bulk carrier lifetimes measured in the epitaxial Si layer on a near intrinsic test wafer in the same batch exceeded 100 µs.
Surface recombination velocities (SRV) are estimated to be 100 cm/s for both electron and holes at the top Si- thermal oxide interface, and 20 cm/s for the Si-BOX interface [10–11]. For either SIMOX or SmartCut SOI wafers, a high temperature (> 1000 °c) annealing assures a low density of dangling bonds or sites for recombination. The upper (etched) Si surface is normally smoothed and passivated by either high temperature thermal oxidation or wet chemical oxidation process . It is generally believed that both the roughness of the etched surface and dangling bonds could affect the SRV value. The literature shows a large variation of the SRV, but the medium values are consistent with those used in this simulation.
A series of numerical experiments were conducted to see the impact of including different device physics models on the attenuator behavior. In particular, the attenuation vs drive current relationship for a 1 cm long Si attenuator, as exhibited in Fig. 1, was calculated. For an optical wavelength of 1550 nm, the light attenuation for a device of length L is estimated as:
Where n and p are electron and hole concentrations in the waveguide assuming they are uniform across the optical mode. Otherwise an overlap integral of light intensity and carrier concentration has to be calculated. The original equation was published by Soref from doped Si experiments [1, 13].
The baseline simulation run included all the physical mechanisms mentioned previously. In Fig. 3 different physical models were used to simulate the structure of Fig. 1 to see the consequence of missing or adding certain mechanisms. If Auger recombination mechanism is omitted, calculated effective carrier lifetime will be longer, which means a higher carrier concentration under the same drive current. In consequence, this leads to an over-estimated attenuation efficiency. Using SRH or CONSRH recombination model did not generate any noticeable difference in attenuation efficiency. Use of the combination of CONMOB & FLDMOB instead of Klaassen’s low field mobility model predicted higher attenuation efficiency. Klassssen’s model agreed well with experimental data, and this was more a model validation issue. There are many different mobility models we could choose, however, for the relative comparison of different device structures, as long as we stick to one model, it shall not alter the relative efficiency between different designs. Due to the relatively-large size of the Si attenuator, a Si attenuaotr working between forward and small reverse bias won’t reach velocity saturation, therefore adding field dependency (FLDMOB) on top of the KLA won’t change the results. Removing BGN ended up with significantly over-estimated attenuation efficiency.
Validation of the numerical model against experimental data will be presented near the end of this paper.
3. Current efficiency of different designs
3.1 The baseline design
We select an amplitude modulation swing between 0dB and 3dB at 100 kHz rate. The rise/fall slope of the square wave drive current is 25ns. The device current (or voltage) is adjusted to achieve a carrier concentration sufficient for 3 dB attenuation. Figure 4 exhibits the electron concentration contour under a bias voltage of 0.798v or current of 17.370 mA, which produces 3dB attenuation at a power of 13.860 mW. The electron concentration along A-A′ is presented in Fig. 5. Because the concentration is uniform over the optical field, attenuation can be calculated using the concentration near the center of the optical mode. This value, according to Eq. (1), is 4.764x1016 cm-3, which is the target concentration for comparing the electrical operating power of alternative designs.
The carrier concentrations in regions to the left of the anode and to the right of the cathode are outside the optical field and are therefore superfluous. Designs that reduce the superfluous charge will necessarily require less electrical power to achieve the same attenuation. Four designs will be evaluated: 1) Through SOI doping, 2) Trench isolation, 3) Recessed contact, and 4) Touch-down recessed contact.
3.2 Through SOI doping
The Through-SOI doping structure is illustrated in Fig. 6. Note that the doping is very deep extending to the BOX. The 2-D electron concentration (corresponding to 3dB of attenuation) is displayed in Fig. 7 and the carrier concentration along B-B′ is given in Fig. 8. Carrier concentrations in regions labeled RL and RR in Fig. 6 are significantly reduced compared to Figs. 4 and 5. Here 3-dB attenuation is achieved at 0.782v, 5.416 mA, and 4.236 mW.
3.3 Trench isolation
Another way to reduce the superfluous charge is to add an isolation trench adjacent to the high p- and n-doping. This structure is illustrated in Fig. 9. A similar approach was suggested by P. D. Hewitt and G. T. Reed . In this case, 3dB attenuation is reached at 0.796v, 16.476 mA, and 13.120 mW.
It is straightforward to expect that the carrier concentration across the whole SOI area is uniform, similar to the case of Fig. 4. Because in any simulation, the left and right simulation window boundary do not allow current to flow through, which is equivalent to an isolation trench.
3.4 Recessed contact
Another approach is to bring the p- and n-doping closer to the BOX as illustrated in Fig. 10.
Figure 11 gives the electron concentration contour corresponding to 3 dB optical attenuation, which is attained at 0.796v, 12.976mA, and 10.324 mW.
3.5 Touch-down recessed contact(TDRC)
Finally, we simulate the Touch-down recessed contact configuration. This design connects the highly-doped area with the BOX layer, as shown in Fig. 12. This configuration minimizes the supefluous carriers. . Note that the carrier concentrations to the left of P+ region and to the right of the N+ region are negligible. The electron concentration contour is given in Fig. 13, again corresponding to 3 dB of attenuation. The electron concentration profile along C-C′ is displayed as Fig. 14. The bias condition is 0.798v; the device consumes 3.467 mA of current and 2.766 mW of power.
Attenuation versus drive current curves are plotted for all 4 alternative designs against the baseline structure in Fig. 15. The Touch-down recessed contact (TDRC) configuration is the most efficient attenuator requiring the least electrical power compared to the alternative designs examined. It is quite obvious that the volume argument can’t explain the big difference between the Touch-down recessed contact structure and the rest. It is informative to evaluate how the thickness of remaining Si (called “recess thickness” in Fig. 13) affects the attenuation efficiency. In Fig. 16, Si attenuator attenuation efficiency is compared between two different recess thickness and the Through SOI layer doping structure, the latter in a sense is a structure with zero recess. It is observable that the device efficiency is very sensitive to the recess thickness, and not sensitive to the device volume. Since higher device efficiency translates into setting up a higher carrier concentration in the waveguide, minimization of recombination is preferred. It seems reasonable to hypothesize that minimizing the amount of volume in the p+ and N+ region exposing to the carriers is the key to high efficiency. In Fig. 13, on the p+ doping side, there is a gradient of electron concentration, and it diminishes to negligible numbers very fast. The reason is that heavy doping could enhance carrier recombination  significantly, and the P+ region therefore serves as a “drain” for electron; and equivalently, N+ region functions as a “drain” for holes.
3.6 Impact on speed
It is natural to exam the impact of different device structures on the transient speed. To make a fair comparison, 0 to 3 dB transient speed is compared among 3 device structures, 0.5 µm TDRC, 1.0 µm TDRC, and the baseline (marked as “no recess” in the figure). A voltage pulse is applied to the device with a period of 4 µs, the ramp up and ramp down time are 25 ns, different voltage levels have to be applied to different structures to achieve 3 dB of attenuation. The result, as displayed in Fig. 17 fall within our expectation that the baseline (no recess) structure has the fastest speed, while TDRC structure with 0.5 µm of Si recess is the slowest. The latter happens to be the most current efficient attenuator. Philosophically higher speed and higher energy efficiency is contradictory to each other for a similar design.
3.7 Diode efficiency
After comparing the efficiency of different diode structures as an IR attenuator, it is interesting to see how they match up to each other as a diode. Figure 18 plots the simulated IV curves of the afore-mentioned device structures, assuming a p-type specific contact resistivity of 1.030x10-5 Ω·cm2 and n-type specific contact resistivity of 3.670x10-6 Ω·cm2. It is worthwhile to point out that the TDRC structure turns out to be the most inefficient diode in contrast to the baseline structure, which is the most efficient diode. The latter has the lowest ideal factor and delivers the largest amount of current at any given voltage.
4. Validation of the numerical model
The credibility of arguments used in this paper largely depends upon the validity of the device model used. To validate the numerical model, we fabricated attenuators with waveguide core sizes of 4 µm. The starting wafers have SOI layer thicknesses of 200 nm with a p-type doping level of 1015 cm-3, doping-free epitaxial Si was adopted to grow Si to the required waveguide thicknesses, due to background doping, we found the actual doping in the epitaxial Si layer was 2x1013 cm-3 p or n type uncontrollable. The waveguide was etched to about 40% of the height and its width equaled the height. Thermal oxide grown at 1050°C was used to passivate the upper Si surface and serves as the upper cladding. The length of the fabricated device was 2.5 mm.
A process model reflecting the detailed epi-growth, etching, doping, oxidation and other thermal process steps was established and its output was used for the device simulation. The device physics used and key device parameters were described in section 2. A comparison of modeling against experimental result was displayed in Fig. 19. Attenuation was measured using an Agilent 83438A ASE source at room temperature near 22°c. The agreement is very reasonable, considering that there are no particular fitting parameters used.
Introduction of recessed contact doping, namely P+ and N+, proved to be very effective to establish certain carrier concentration in the waveguide region. All curves presented were attenuation versus the drive current. For a diode, if the series resistance is low, I-V curve is usually very steep, therefore a current efficient attenuator will translate into a power efficient attenuator.
Considering practical implantation projected ranges and doses (typical commercial implanter supports 15-200 kev of implantation energy, and Sb, B, As, P elements), high level uniform doping could be achieved in about 1 µm depth range with some considerable level of cost, 0.3-0.5 µm in depth is much more preferable. Considering these factors, as we shrink the waveguide height to about 1 µm, and still do a 40% depth etch to form a ridge waveguide and maintain single mode condition, we automatically take advantage of the benefit from the Touch-down recessed contact structure. For waveguide height between 1 and 10 µm, in general we have to conduct two etches: one for ridge formation, the other to form a recessed contact area.
All device structures used in this study assumed the same waveguide width and ridge etch depth, which made it easy for comparison. Referring to Fig. 2, it is easy to see that as long as the light in the slab does not see the P++ and N++ doping and cause free carrier absorption loss, the edge of the highly doped area shall be placed as near to the ridge as possible. Narrowing down the distance between the two doped area could not only improve the power efficiency of the Si attenuator, but also improve its speed. Waveguide height, ridge etch depth, waveguide width, and even contact size would affect the attenuation efficiency of the attenuator, however, the power advantage of TDRC still exists, as long as we compare waveguide with the same height, width, ridge depth, and the ridge to heavily-doped area distance. A more detailed discussion on how these parameters affect the attenuation power efficiency goes beyond the scope of this paper. In case we want to use this attenuator as a phase shifter, TDRC structure would still be the most power efficient because carrier concentration uniquely sets the phase shift. If the attenuation is the same, then the phase shift would be almost the same, because the different contact geometry did not change the optical mode. The difference in carrier concentration distribution was not that big, only optical energy and carrier concentration overlap integral will give a more rigorous answer.
A power efficient Si attenuator design utilizing a recessed contact structure was introduced. A Silvaco device model was established using realistic surface recombination velocities and SRH carrier lifetimes, instead of effective carrier lifetimes. Various device structures were compared to understand why the aforesaid attenuator was more efficient than other alternative designs. Speed and power efficiency tradeoffs were also investigated.
The authors are grateful to many Kotura colleagues for stimulating discussions through years of Variable Optical Attenuator development. In particular, we like to thank Dr. R. Shafiiha for the optical mode simulation, and C. C. Kung, W. Qian, and J. Fong for testing device fabrication.
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